JP2007071944A - Current output type integrated circuit and gradation data signal supply method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve higher enhancement of gradation accuracy of output while suppressing the number of transistors, a plurality of which are arranged and formed like a cell array and which generate prescribed output currents. <P>SOLUTION: An output section 7 of a current output type source driver of an organic EL display device 1 includes a reference current source 11, an output control circuit 12, a transistor cell array section 13, a switch SW1 to SW13, a Miller transistor NTK for distribution, and a output terminal OUT. The transistor cell array section 13 includes output transistors NT1 to NT31 which are disposed for the purposes of correspondence to gradations 5bit (32 gradations), are composed of Nch MOS transistors, and generate prescribed output currents in 31-pieces array form in parallel. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a current output type integrated circuit applied to a source driver such as an FPD (Flat Panel Display).

  FPD includes liquid crystal (LCD Liquid Crystal Display), FED (Field Emission Display), ELD (Electroluminescent Display), PDP (Plasma Display Panel), etc., and is applied to various fields. Among them, an organic EL display (also called OLED (Organic Electroluminescence Display)) can obtain high brightness even in a low voltage region, it is easy to see and power-saving, and the light emitting material is organic, so that the substrate can be used. In recent years, it has attracted attention as a display that can be bent like plastic.

  An active matrix organic EL display device as a display device includes a power supply circuit, a signal control circuit, an organic EL drive circuit, a display screen, and the like. The organic EL driving circuit includes a scanning-side vertical driver (hereinafter referred to as a gate driver) and a data-side horizontal driver (hereinafter referred to as a source driver). A current output type source driver as an organic EL drive circuit has a function of mainly outputting a data signal for display to a data line. On the other hand, a gate driver as an organic EL driving circuit has a function of outputting a scanning signal to a scanning line. In the output section of the current output type source driver, a plurality of output MOS transistors that generate a constant output current are arranged in a cell array along the horizontal direction or the vertical direction (see, for example, Patent Document 1).

  In the output MOS transistors arranged in a plurality in the cell array, the output current of the output MOS transistor at the other end is increased or decreased as compared with the output current of the output MOS transistor at the other end due to process variations due to manufacturing processes. So-called linear function fluctuations occur, or so-called quadratic function fluctuations occur in which the output current of the output MOS transistors at both ends increases or decreases compared to the output current of the output MOS transistor at the center. As a result, the linearity of the gradation performance of the output may be deteriorated.

Also, as a countermeasure for process variations due to manufacturing processes, etc., the number of cell array-like output MOS transistors is increased, dummy transistors are provided around the cell array-like output MOS transistors, or dummy patterns are arranged around the cell array-like output MOS transistors. If it is provided, the area of the current output type source driver is increased, and the cost of the OELD display device is increased.
JP 2005-156966 A (page 48, FIG. 10)

  The present invention provides a current output type integrated circuit and a gradation data signal supply method that are formed in a plurality of cell arrays and that can suppress the number of transistors that generate a predetermined output current and can achieve high gradation accuracy.

  To achieve the above object, a current output type integrated circuit according to an aspect of the present invention includes a first output transistor that generates an output current based on a gradation data signal of bitm (m is a positive integer), A second output transistor disposed on both sides of the first output transistor, and generating an output current based on a gradation data signal lower than the bitm, wherein the output transistor is nbit (n is m (Where n is an integer greater than or equal to 2) used for gradation display, a transistor cell array part connected between gates, and a gate connected to the gate of the output transistor of the transistor cell array part to generate a reference current And a mirror transistor for use.

Furthermore, in order to achieve the above object, the gradation data signal supply method of one embodiment of the present invention is used for nbit (n is a positive integer of 2 or more) gradation display, and 2 ⁿ −1 in which the gates are connected. 1 or 2 ⁿ output transistors are arranged in parallel or in series, and bit information is divided into k (k is a positive integer greater than or ^equal to 1). a step of providing a bit gradation data signal, and a gradation data signal of bitm (m is n or less and m is a positive integer) applied to the third and fourth output transistors provided outside the both ends of the transistor cell array unit. Providing a gradation data signal higher than bitm to a fifth output transistor provided between the third and fourth output transistors; That it comprises a step of providing a sixth gradation data signal of the most significant bit in the output transistor of the provided serial k divided center of the transistor cell array section and it said.

  According to the present invention, there are provided a current output type integrated circuit and a gradation data signal supply method which are formed in a plurality of cell arrays and suppress the number of transistors which generate a predetermined output current and which can increase the gradation accuracy. be able to.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a current output type integrated circuit and a gradation data signal supply method according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a schematic block diagram showing a configuration of an organic EL display device, FIG. 2 is a circuit diagram showing an output unit of a current output type source driver, and FIG. 3 is a diagram showing an arrangement of output transistors in a transistor cell array unit. In this embodiment, a current mirror circuit is used to generate a reference current as a distribution current.

  As shown in FIG. 1, the organic EL display device 1 is provided with a display controller 2, a DC-DC converter 3, a display panel 4, a gate driver 5, and a source driver 6. The organic EL display device 1 is used for display of a small portable information terminal or the like. The source driver is also called a data driver, a data line driver, or a horizontal driver, and the gate driver is also called a scan driver, a scan driver, or a horizontal driver.

  The display controller 2 receives a synchronization signal such as a clock signal and display data information of red (R), green (G), and blue (B), and performs image data processing in order to perform an execution calculation of the organic EL display device 1. Signals such as control data are output to the gate driver 5 and the source driver 6 as parallel data. The DC-DC converter 3 generates various voltages necessary for displaying images on the display panel 4 from an external power source such as a battery, and functions as a power source for supplying these voltages to the gate driver 5 and the source driver 6. To do.

  The gate driver 5 inputs the signal output from the display controller 2 and the power supply voltage output from the DC-DC converter 3, and supplies a voltage for displaying an image on the scanning line having the MCH number of the display panel 4. .

  The source driver 6 is a current output type driver, and receives the signal output from the display controller 2 and the power supply voltage output from the DC-DC converter 3, and NCH × 3 (R, G, B) of the display panel 4. An output current lout for displaying an image is supplied to the data lines having the number. The output current Iout changes in current level corresponding to the gradation capability display.

  The display panel 4 is composed of an organic EL display (Organic Electroluminescence Display), and has MCH scanning lines (not shown) and NCH × 3 data lines, and a pixel portion is provided in an area surrounded by the scanning lines and the data lines. Each is provided. The display panel 4 is a display using an organic material having a property of emitting light when supplied with current, for example, diamines, and the luminance is determined according to the value of current flowing through the element.

  As shown in FIG. 2, the output unit 7 of the current output type source driver includes a reference current source 11, an output control circuit 12, a transistor cell array unit 13, switches SW1 to SW31, a distribution mirror transistor NTK, and an output terminal OUT. Is provided.

  The reference current source 11 has one end connected to the analog high potential side power source AVdd, the other end connected to the drain of the distribution mirror transistor NTK, and display data information of red (R), green (G), and blue (B). A reference current Istd necessary for outputting an output current used for the purpose is generated. Note that the value of the reference current Istd can be arbitrarily set in multiple stages using, for example, a ladder resistor, a ladder switch, a comparator, a transistor, and the like (not shown).

  The output control circuit 12 receives video signal data and precharge information signal data, and outputs gradation data signals D1 to D31 for performing on / off control of the output transistors NT1 to NT31 of the transistor cell array unit 13, respectively. Output to SW31. Here, illustration and description of voltage precharge information, current precharge information, and precharge pulse width information, which are precharge information, are omitted, and illustration and description regarding voltage precharge, current precharge, and precharge pulse width control are omitted. Is omitted. Note that the value of the precharge voltage PV can be arbitrarily set in multiple stages.

  The switch SW1 is composed of SPST (Single Pole Single Throw), one end is connected to the precharge voltage side and the output terminal OUT side, the other end is connected to the drain of the output transistor NT1 of the transistor cell array unit 13, and the output control circuit 12 Is turned on when the gradation data signal D1 output from is at “High” level, for example, to connect both ends.

  The switch SW2 is composed of SPST (Single Pole Single Throw), one end is connected to the precharge voltage side and the output terminal OUT side, the other end is connected to the drain of the output transistor NT2 of the transistor cell array unit 13, and the output control circuit 12 Is turned on when the gradation data signal D2 output from is “High” level, for example, to connect both ends.

  The switch SW3 is composed of SPST (Single Pole Single Throw), one end is connected to the precharge voltage side and the output terminal OUT side, the other end is connected to the drain of the output transistor NT3 of the transistor cell array unit 13, and the output control circuit 12 Is turned on when the gradation data signal D3 output from is at a “High” level, for example, to connect both ends. The switches SW4 to SW31 have the same arrangement and configuration as the switches SW1 to SW3, and the description thereof is omitted.

  Here, a Wilson constant current circuit may be used instead of the current mirror constant current circuit. Further, on / off control of the output transistor may be performed using a transfer gate and an inverter instead of the switch.

  The distribution mirror transistor NTK is composed of an Nch MOS transistor, the gate is connected to the drain, and the source is connected to the low potential side power source Vss. The distribution mirror transistor NTK forms a current mirror circuit with the output transistor of the transistor cell array unit 13, and when the output transistor of the transistor cell array unit 13 is on, the output transistor of the transistor cell array unit 13 has a mirror ratio × reference current Istd. Control the flow of current. The MOS transistor is also called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  The transistor cell array unit 13 is provided for gradation 5 bits (32 gradations), and 31 output transistors NT1 to NT31 formed of Nch MOS transistors are provided in an array in parallel.

  Here, in order to generate a predetermined output current, the output transistors NT1 to NT31 preferably have the same shape and the same threshold voltage, respectively, and preferably have gates arranged in parallel at equal intervals.

  The output transistor NT1 has a gate connected to the gate and drain of the distributing mirror transistor NTK, and a source connected to the low potential side power source Vss. The output transistor NT1 causes a current of mirror ratio × reference current Istd to flow to the low potential side power supply Vss side when the switch SW1 is turned on.

  The output transistor NT2 has a gate connected to the gate and drain of the distribution mirror transistor NTK, and a source connected to the low potential side power supply Vss. The output transistor NT2 allows a current of mirror ratio × reference current Istd to flow to the low potential side power supply Vss side when the switch SW2 is turned on.

  The output transistor NT3 has a gate connected to the gate and drain of the distribution mirror transistor NTK, and a source connected to the low potential power source Vss. The output transistor NT3 allows a current of mirror ratio × reference current Istd to flow to the low potential side power supply Vss side when the switch SW3 is turned on. The output transistors NT4 to NT31 have the same arrangement and configuration as the output transistors NT1 to NT3, and a description thereof is omitted.

  The output terminal OUT is a terminal that outputs an output current Iout necessary for the display panel 4 to perform light emission display. The output current Iout varies depending on the number of output transistors of the transistor cell array unit 13 that are turned on. For example, when all the output transistors are turned on, the output current Iout has a value of mirror ratio × reference current Istd × 31. Note that the number of gradations of the output current Iout can be increased from the number of gradations of 5 bits (32 gradations) by changing the number of stages of the reference current Istd and the number of stages of the precharge voltage PV.

As shown in FIG. 3, in the transistor array portion 13, the output transistors NT1 to NT31 are arranged in 31 rows × 1 columns in the vertical direction, with the output transistor NT1 being the uppermost stage. In the case of gradation 5 bits, bit 1 (the most significant bit) is one output transistor (2 ⁰ ), bit 2 is two output transistors (2 ¹ ), bit 3 is four output transistors (2 ² ), bit 4 (the least significant bit) is 8 output transistors (2 ³ ) and bit 5 are 16 output transistors (2 ⁴ ).

  Here, the cell address information is information of a gradation data signal for turning on / off the output transistor, and the cell address display (1 or 0 display) is set to bit 5 having information of “1” in the first digit. The first digit is “0”, the second digit is “4”, and the first and second digits are “0” and the third digit is “1”. Bit 3 is the first digit to the third digit “0”, the fourth digit “1” information is bit 4, and the first digit to the fourth digit “0” information is bit 5. Yes.

  In the gradation data signal supply method to the output transistors, first, the gradation data signal information of bit 5 is given to the uppermost output transistors NT1 to NT8 and the lowermost output transistors NT24 to NT31. Next, the information of the bit 4 gradation data signal is given to the output transistors NT9 to NT12 adjacent to the output transistor NT8 and the output transistors NT20 to NT23 adjacent to the output transistor NT24. Subsequently, the gradation data signal information of bit3 is given to the output transistor NT13 and the output transistor NT14 adjacent to the output transistor NT12, and to the output transistor NT18 and the output transistor NT19 adjacent to the output transistor NT20. Next, the bit 2 gradation data signal information is supplied to the output transistor NT15 adjacent to the output transistor NT14 and the output transistor NT17 adjacent to the output transistor NT18. Subsequently, the gradation data signal information of bit1 is given to the output transistor NT16 between the output transistors NT15 and NT17. Here, the bit information is arranged symmetrically about the output transistor NT16.

  Here, the first digit is displayed as bit5, the second digit is bit4, the third digit is bit3, the fourth digit is bit2, and bit1 is (0000). May be displayed as bit1, the second digit is bit2, the third digit is bit3, the fourth digit is bit4, and the fifth digit is bit5.

  Next, the gradation characteristics of the organic EL display device when the drive capability variation of the output transistor occurs will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram showing a linear function variation of the drive capability of the output transistor. FIG. 5 is a characteristic diagram showing the relationship between the gradation of the organic EL display device and the output current when the linear function variation of the drive capability of the output transistor occurs. Here, the linear function fluctuation of the drive capability of the output transistor means a linear change caused by a manufacturing variation (process fluctuation) generated in a manufacturing process of a current output type source driver composed of a semiconductor integrated circuit.

  As shown in FIG. 4, the drive capability, which is the current that flows when the output transistors NT1 to NT31 of the transistor cell array portion are turned on, has a minimum value in the output transistor NT1, increases linearly by 1%, and increases to a maximum value in the output transistor NT31. It becomes. Here, the value of the output transistor NT16 disposed in the central portion of the transistor cell array unit 13 is a set target value, and this value (1 μA) is arbitrarily changed by changing the transistor shape, threshold voltage, gate application condition, and the like. It may be changed.

  As shown in FIG. 5, even if the drive capability of the output transistor varies with a linear function (shown in FIG. 4), the output current of the output transistor increases linearly with respect to the gradation change, which is in good agreement with the ideal value curve. . For this reason, the fluctuation error (differential fluctuation error and integral fluctuation error) can be reduced (± 0.1 LSB or less), and high gradation accuracy can be achieved. Even when the drive capability of the output transistor NT1 is the maximum value and the output transistor NT31 is the minimum value, high gradation accuracy can be achieved similarly.

  As described above, in the current output type integrated circuit and the gradation data signal supply method of the present embodiment, 31 output transistors NT1 to NT31 formed of Nch MOS transistors are provided in parallel in the output section in an array form. . In the gradation data signal supply method to the output transistor, first, the gradation data signal information of bit 5 is given to the output transistors NT1 to NT8 and the output transistors NT24 to NT31. Next, the gradation data signal information of bit4 is given to the output transistors NT9 to NT12 and the output transistors NT20 to NT23. Subsequently, the gradation data signal information of bit3 is given to the output transistor NT13 and the output transistor NT14, and the output transistor NT18 and the output transistor NT19. Next, the gradation data signal information of bit2 is given to the output transistor NT15 and the output transistor NT17. Subsequently, the gradation data signal information of bit1 is given to the output transistor NT16.

  For this reason, even if the drive capability of the output transistor fluctuates by a linear function due to manufacturing variation (process fluctuation) that occurs in the manufacturing process, the output current of the output transistor increases linearly with respect to the change in gradation, and the ideal value curve is improved. Match. Therefore, the differential fluctuation error and the integral fluctuation error can be reduced, and high gradation accuracy can be achieved.

In this embodiment, a silicon oxide film is used as the gate insulating film of the MOS transistor. However, a SiNxOy film obtained by thermally nitriding a silicon oxide film, a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film laminated film, Alternatively, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a high dielectric film (High-K gate insulating film) or the like becomes a gate insulating film may be used.

  Next, a current output type integrated circuit and a gradation data signal supply method according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 6 is a diagram showing the arrangement of output transistors in the transistor cell array portion. In this embodiment, the method of supplying gradation data signal information for controlling on / off of the output transistors in the transistor cell array portion is changed.

  As shown in FIG. 6, in the transistor array section 13, the output transistor NT1 is arranged at the top in the vertical direction, the output transistors NT1 to NT31 are arranged in 31 rows × 1 column, and the bit information is vertically arranged around the output transistor NT16. It is divided into two (number of division stages is 2).

  The gradation data signal supply method to the output transistor is as follows. First, the output transistors NT1, NT3, NT5, NT7, NT9, NT11, NT13, NT15, NT17, NT19, NT21, NT23, NT25, NT27, NT29, and NT31 are set to bit5. Provides tone data signal information. Here, the output transistors NT1, NT3, NT5, NT7, NT9, NT11, NT13, and NT15 having bit5 information are arranged vertically symmetrically about the output transistor NT8, and the output transistors NT17, NT19, having bit5 information are arranged. NT21, NT23, NT25, NT27, NT29, and NT31 are arranged vertically symmetrically about the output transistor NT24.

  Next, the information of the bit 4 gradation data signal is given to the output transistors NT2, NT6, NT10, NT14, NT18, NT22, NT26, and NT30. Here, the output transistors NT2, NT6, NT10, and NT14 having information on bit4 are arranged vertically symmetrically about the output transistor NT8, and the output transistors NT18, NT22, NT26, and NT30 having information on bit4 are output. The transistors NT24 are arranged symmetrically with respect to the center.

  Subsequently, the gradation data signal information of bit3 is given to the output transistors NT4, NT12, NT20, and NT28. Here, the output transistors NT4 and NT12 having information on bit3 are arranged vertically symmetrically around the output transistor NT8, and the output transistors NT20 and NT28 having information on bit3 are arranged symmetrically up and down around the output transistor NT24. ing.

  Next, the bit2 information is given to the output transistors NT8 and NT24. Here, the output transistors NT8 and NT24 are arranged vertically symmetrically about the output transistor NT16. Subsequently, the bit1 information is given to the output transistor NT16.

  Next, the gradation characteristics of the organic EL display device when the drive capability variation of the output transistor occurs will be described with reference to FIGS. 7 to 9. FIG. 7 shows the drive capability variation of the output transistor when the quadratic function variation occurs. FIG. 8 is a characteristic diagram showing the relationship between gradation and output current of an organic EL display device, FIG. 8 (a) is a characteristic diagram when a linear function fluctuation occurs, and FIG. 8 (b) is a quadratic function fluctuation. FIG. 9 is a characteristic diagram of Example 1 showing the relationship between the gradation of the organic EL display device and the output current when a quadratic function variation occurs. Here, the quadratic function variation of the drive capability of the output transistor is a function that changes in a quadratic function due to manufacturing variation (process variation) that occurs in the manufacturing process of a current output type source driver composed of a semiconductor integrated circuit. To tell.

  As shown in FIG. 7, the drive capability, which is the current that flows when the output transistors NT1 to NT31 in the transistor cell array portion are turned on, exhibits a minimum value in the output transistor NT16 in the central portion and increases in a quadratic function toward both ends. As a result, the output transistors NT1 and NT31 at both ends have the maximum value.

  As a cause of the occurrence of the quadratic function variation, for example, the gate size (gate length) of the output transistor in the peripheral portion of the transistor cell array unit 13 generated by the loading effect when the gate is processed using the RIE (Reactive Ion Etching) method. ) Narrowing etc. When the gate dimension (gate length) is equal to or less than a predetermined width, the threshold voltage of the output transistor is lowered and the drive capability is increased.

  As shown in FIG. 8A, even if the drive capability of the output transistor varies with a linear function (shown in FIG. 4), the output current of the output transistor increases linearly with respect to the gradation change, and is well in line with the ideal value curve. I'm doing it. For this reason, fluctuation errors (differential fluctuation error and integral fluctuation error) can be reduced (± 0.1 LSB or less), and high gradation accuracy can be achieved.

  As shown in FIG. 8B, the output current of the output transistor increases linearly with respect to the change in gradation even if the drive capability of the output transistor fluctuates in a quadratic function (shown in FIG. 7). Match. Therefore, the differential fluctuation error can be reduced (within the range of −0.19 to +0.31 LSB), the integral fluctuation error can also be reduced (within the range of −0.28 to +0.12 LSB), and high gradation accuracy can be achieved. Can do.

  On the other hand, as shown in FIG. 9, in the first embodiment, when the drive capability of the output transistor fluctuates in a quadratic function (shown in FIG. 7), the output current of the output transistor changes discontinuously with the gradation change, and the ideal value It doesn't agree well with the curve. For this reason, the differential variation error is large (−0.02 to + 3.72LSB), the integral variation error is also large (−1.88 to + 1.84LSB), and the gradation accuracy cannot be maintained.

  As described above, in the current output type integrated circuit and the gradation data signal supply method of the present embodiment, 31 output transistors NT1 to NT31 formed of Nch MOS transistors are provided in parallel in the output section in an array form. . The gradation data signal supply method to the output transistor is as follows. First, the gradation data of bit 5 is output to the output transistors NT1, NT3, NT5, NT7, NT9, NT11, NT13, NT15, NT17, NT19, NT23, NT25, NT27, NT29, and NT31. Give signal information. Next, the information of the bit 4 gradation data signal is given to the output transistors NT2, NT6, NT10, NT14, NT18, NT22, NT26, and NT30. Subsequently, the gradation data signal information of bit3 is given to the output transistors NT4, NT12, NT20, and NT28. Next, the bit 2 gradation data signal information is supplied to the output transistors NT8 and NT24. Subsequently, the gradation data signal information of bit1 is given to the output transistor NT16. Here, the bit information is divided into two in the vertical direction with the output transistor as the center.

  For this reason, even if the drive capability of the output transistor fluctuates by a linear function due to manufacturing variation (process fluctuation) that occurs in the manufacturing process, the output current of the output transistor increases linearly with respect to the change in gradation, and the ideal value curve is improved. In addition, even if the drive capability of the output transistor varies by a quadratic function due to manufacturing variations (process variation) that occur in the manufacturing process, the output current of the output transistor increases linearly with respect to the gradation change, and the ideal value It almost coincides with the curve. Therefore, the differential fluctuation error and the integral fluctuation error can be reduced, and high gradation accuracy can be achieved.

  Next, a current output type integrated circuit and a gradation data signal supply method according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 10 is a diagram showing the arrangement of output transistors in the transistor cell array portion. In the present embodiment, dummy transistors are added to the transistor cell array portion so that the number of output transistors is 32. Note that the dummy transistor has the same shape as the output transistor, and is not supplied with a gradation data signal and does not generate an output current.

  As shown in FIG. 10, in the transistor array portion 13a, the output transistor NT1 is arranged at the top in the vertical direction, and the output transistors NT1 to NT32 are arranged in 32 rows × 1 column, and the bit information is divided into four (the number of divided stages is 4). A dummy transistor is arranged in NT24. Here, the cell address is displayed only in the first, second, and third digits.

  The gradation data signal supply method to the output transistor is as follows. First, output transistors NT1, NT3, NT5, NT7, NT10, NT12, NT14, NT16, NT17, NT19, NT21, NT23, NT26, NT28, NT30, and NT32 Provides tone data signal information. Here, the output transistors NT1, NT3, NT5, and NT7 having information on bit5 are arranged vertically symmetrically about the output transistor NT4, and the output transistors NT10, NT12, NT14, and NT16 having information on bit5 are output transistors NT13. The output transistors NT17, NT19, NT21, and NT23 having the bit5 information are arranged vertically symmetrically about the output transistor NT20, and the output transistors NT26, NT28, NT30 having the bit5 information are arranged. And NT32 are arranged symmetrically about the output transistor NT29.

  Next, the information of the bit 4 gradation data signal is given to the output transistors NT2, NT6, NT11, NT15, NT18, NT22, NT27, and NT31. Here, the output transistors NT2 and NT6 having the bit4 information are arranged vertically symmetrically with the output transistor NT4 as the center, and the output transistors NT11 and NT15 having the bit4 information are arranged symmetrically with the output transistor NT13 as the center. , Bit4 output transistors NT18 and NT22 are arranged vertically symmetrically about the output transistor NT20, and bit4 information output transistors NT27 and NT31 are arranged vertically symmetrically about the output transistor NT29. .

  Subsequently, the gradation data signal information of bit3 is given to the output transistors NT4, NT13, NT20, and NT29. Here, the output transistors NT4 and NT13 having information on bit3 are arranged symmetrically with respect to the center between the output transistors NT8 and NT9, and the output transistors NT20 and NT29 having information on bit3 are output transistors NT24 which are dummy transistors. And the output transistor NT25 are arranged symmetrically in the vertical direction.

  Next, the bit 2 gradation data signal information is supplied to the output transistors NT9 and NT25. Subsequently, the gradation data signal information of bit1 is given to the output transistor NT8.

  Next, the gradation characteristics of the organic EL display device when the drive capability variation of the output transistor occurs will be described with reference to FIG. 11. FIG. 11 shows the gradation and output current of the organic EL display device when the quadratic function variation occurs. It is a characteristic view which shows the relationship.

  As shown in FIG. 11, even if the drive capability of the output transistor fluctuates in the same quadratic function as shown in FIG. 7, the output current of the output transistor increases linearly with respect to the gradation change, and agrees well with the ideal value curve. ing. For this reason, the differential fluctuation error is small (within the range of −0.12 to + 0.10LSB), the integral fluctuation error is also small (within the range of −0.12 to + 0.12LSB), and is much higher tone than the second embodiment. Accuracy can be achieved. Note that even if the drive capability of the output transistor fluctuates in the same linear function as shown in FIG. 4, the output current of the output transistor increases linearly with respect to the gradation change, which is good as an ideal curve as in FIG. Match.

  As described above, in the current output type integrated circuit and the gradation data signal supply method according to the present embodiment, the output unit is composed of Nch MOS transistors, and 32 output transistors NT1 to NT32 including one dummy transistor are arrayed in parallel. It is provided in the shape. The gradation data signal supply method to the output transistor is as follows. First, output transistors NT1, NT3, NT5, NT7, NT10, NT12, NT14, NT16, NT17, NT19, NT21, NT23, NT26, NT28, NT30, and NT32 Provides tone data signal information. Next, the information of the bit 4 gradation data signal is given to the output transistors NT2, NT6, NT11, NT15, NT18, NT22, NT27, and NT31. Subsequently, the gradation data signal information of bit3 is given to the output transistors NT4, NT13, NT20, and NT29. Next, the bit 2 gradation data signal information is supplied to the output transistors NT9 and NT25. Subsequently, the gradation data signal information of bit1 is given to the output transistor NT8. Here, the bit information is divided into four.

  For this reason, even if the drive capability of the output transistor fluctuates by a linear function due to manufacturing variation (process fluctuation) that occurs in the manufacturing process, the output current of the output transistor increases linearly with respect to the change in gradation, and the ideal value curve is improved. The output current of the output transistor increases linearly with respect to the change in gradation even if the drive capability of the output transistor changes and the quadratic function fluctuates due to manufacturing variations (process fluctuation) generated in the manufacturing process. It matches the ideal value curve better than 2. Therefore, the differential fluctuation error and the integral fluctuation error can be made smaller than in the second embodiment, and high gradation accuracy can be achieved.

  In the present embodiment, one dummy transistor is provided in the transistor cell array portion 13a, but two or more dummy transistors may be provided.

  Next, a current output type integrated circuit and a gradation data signal supply method according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 12 is a diagram showing the arrangement of output transistors in the transistor cell array portion. In the present embodiment, the number and arrangement of output transistors in the transistor cell array portion are changed and dealt with.

As shown in FIG. 12, in the transistor cell array portion 13b, 32 output transistors are arranged in the vertical direction and a total of 256 are arranged in 32 rows × 6 columns of 8 in the horizontal direction, and the bit information is divided into 4 (divided stage number 4). ) Dummy transistors are arranged in 24 rows and E columns, and the cell address display is the first digit, the second digit, and the third digit from Bit 1 to Bit 5, and the first digit and the second digit from bit 6 to bit 8. Only eyes are displayed. In the case of gradation 8 bits (256 gradations), bit 1 is one output transistor (2 ⁰ ), bit 2 is two output transistors (2 ¹ ), bit 3 is four output transistors (2 ² ), and bit 4 is an output transistor 8. pieces ⁽² 3), bit5 output transistor 16 ⁽² 4), bit6 output transistor 32 ⁽² 5), bit7 output transistor 64 ⁽² 5), bit8 output transistor 128 and ^{(2 7)} Become.

  In the gradation data signal supply method to the output transistor, first, information on the gradation data signal of bit 8 is given to the output transistors in the A column, the C column, the F column, and the H column. Here, the output transistors of the A column and the C column and the output transistors of the F column and the H column having the information of bit 8 are arranged symmetrically with respect to the center between the D column and the E column.

  Next, bit 7 gradation data signal information is applied to the output transistors in the B and G columns. Here, the output transistors of the B column and the G column having the information of bit 7 are arranged symmetrically with respect to between the D column and the E column.

  Subsequently, the gradation data signal information of bit 6 is given to the output transistors in the 17th to 32th rows in the D column and the output transistors in the 1st to 16th rows in the E column. Here, the 17th to 32nd row output transistors in the D column having the bit6 information and the 1st row to 16th row output transistors in the E column are centered between the 16th row and the 17th row and between the D column and the E column. Are arranged symmetrically as a point.

  Next, the output transistors of the 1st row, 3rd row, 5th row, 7th row, 10th row, 12th row, 14th row and 16th row in the D column, 17th row, 19th row, 21st row, 23th row, 26th row in the E column The information of the bit 5 gradation data signal is given to the rows 28, 30, and 32. Here, the output transistors in the 1st, 3rd, 5th, and 7th rows of the D column having the bit5 information are arranged vertically symmetrically about the output transistors in the D column and the 4th row, and the D column having the bit5 information. The 10th, 12th, 14th, and 16th row output transistors are arranged symmetrically with respect to the D column 13th row output transistor, and the 17th row, the 19th row, the 21st row in the E column having bit 5 information, And the output transistors in rows 23 and 23 are arranged symmetrically with respect to the transistor in row E, column 20 and the output transistors in rows E, 26, 28, 30 and 32 having bit 5 information are arranged in row E, row 29. Are arranged symmetrically with respect to the output transistor.

  Subsequently, the gradation data signal information of bit 4 is given to the output transistors in the 2nd, 6th, 11th, and 15th rows in the D column, and the 18th, 22nd, 27th, and 31st rows in the E column. Here, the output transistors of the 2nd and 6th rows of the D column having the bit4 information are arranged vertically symmetrically with the output transistor of the 4th row of the D column as the center, and the 11th and 15th rows of the D column having the bit4 information are arranged. The output transistors are arranged vertically symmetrically about the output transistor of D column 13 rows, and the 18 and 22 row output transistors having bit 4 information are arranged vertically symmetrically about the transistor of E column 20 rows. The output transistors in the 27th and 31st rows of the E column having the information of bit4 are arranged symmetrically about the output transistor in the 29th row of the E column.

  Next, the bit 3 gradation data signal information is given to the output transistors in the 4th and 13th rows of the D column and the 20th and 29th rows of the E column. Subsequently, the gradation data signal information of bit 2 is given to the output transistors in the D column 9 rows and the E column 25 rows. Next, the gradation data signal information of bit1 is given to the output transistor in the D column and 8 rows.

  Next, the gradation characteristics of the organic EL display device when the drive capability variation of the output transistor occurs will be described with reference to FIGS. 13 and 14. FIG. 13 shows the gradation of the organic EL display device when the linear function variation occurs. FIG. 14 is a characteristic diagram showing the relationship between the gradation of the organic EL display device and the output current when a quadratic function variation occurs. Here, the linear function fluctuation of the drive capability of the output transistor means that the output transistor of the transistor cell array unit 13b changes as shown in FIG. 4 due to manufacturing variations (process fluctuations) in the row direction and the column direction. The quadratic function variation of the drive capability of the output transistor means that the output transistor of the transistor cell array portion 13b varies in a quadratic function as shown in FIG. 7 due to manufacturing variation (process variation) in the row direction and the column direction. To tell.

  As shown in FIG. 13, even if the drive capability of the output transistor fluctuates by a linear function, the output current of the output transistor increases linearly with respect to the gradation change, which is in good agreement with the ideal value curve. For this reason, the differential fluctuation error and the integral fluctuation error can be reduced (± 0.2 LSB or less), and high gradation accuracy can be achieved.

  As shown in FIG. 14, even if the drive capability of the output transistor fluctuates by a quadratic function, the output current of the output transistor increases linearly with respect to the change in gradation, and substantially matches the ideal value curve. Therefore, the differential fluctuation error can be reduced (within the range of −0.1 to +0.19 LSB), the integral fluctuation error can also be reduced (within the range of −0.19 to +0.15 LSB), and high gradation accuracy can be achieved. be able to.

  As described above, in the current output type integrated circuit and gradation data signal supply method of the present embodiment, the output unit is composed of Nch MOS transistors, and 32 output transistors including one dummy transistor are arranged in the vertical direction and in the horizontal direction. A total of 256 arrays of 8 32 rows × 8 columns are provided. In the gradation data signal supply method to the output transistor, first, information on the gradation data signal of bit 8 is given to the output transistors in the A column, the C column, the F column, and the H column. Next, bit 7 gradation data signal information is applied to the output transistors in the B and G columns. Subsequently, the gradation data signal information of bit 6 is given to the output transistors in the 17th to 32th rows in the D column and the output transistors in the 1st to 16th rows in the E column. Next, the output transistors of the 1st row, 3rd row, 5th row, 7th row, 10th row, 12th row, 14th row and 16th row in the D column, 17th row, 19th row, 21st row, 23th row, 26th row in the E column The information of the bit 5 gradation data signal is given to the rows 28, 30, and 32. Subsequently, the gradation data signal information of bit 4 is given to the output transistors in the 2nd, 6th, 11th, and 15th rows in the D column, and the 18th, 22nd, 27th, and 31st rows in the E column. Next, the bit 3 gradation data signal information is given to the output transistors in the 4th and 13th rows of the D column and the 20th and 29th rows of the E column. Subsequently, the gradation data signal information of bit 2 is given to the output transistors in the D column 9 rows and the E column 25 rows. Next, the gradation data signal information of bit1 is given to the output transistor in the D column and 8 rows. Here, the bit information is divided into four.

  For this reason, even if the drive capability of the output transistor fluctuates by a linear function due to manufacturing variation (process fluctuation) that occurs in the manufacturing process, the output current of the output transistor increases linearly with respect to the change in gradation, and the ideal value curve is improved. In addition, even if the drive capability of the output transistor varies by a quadratic function due to manufacturing variations (process variation) that occur in the manufacturing process, the output current of the output transistor increases linearly with respect to the gradation change, and the ideal value It almost coincides with the curve. Therefore, the differential fluctuation error and the integral fluctuation error can be reduced, and high gradation accuracy can be achieved.

  Next, a current output type integrated circuit and a gradation data signal supply method according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 15 is a diagram showing the arrangement of output transistors in the transistor cell array portion. In this embodiment, the number and arrangement of the output transistors in the transistor cell array portion of the fourth embodiment are the same, but the method of supplying information of the gradation data signal for controlling on / off of the output transistors is changed.

  As shown in FIG. 15, in the transistor cell array unit 13c, 32 output transistors are arranged in the vertical direction and 8 in the horizontal direction are arranged in a total of 256 in 32 rows × 6 columns, and the bit information is divided into four. . The dummy transistors are arranged and formed in 24 rows and E columns, and the cell array display shows the first row, the second row, and the third row.

  The gradation data signal supply method to the output transistor is as follows. First, the odd rows of the A column, the even rows of the B column, the odd rows of the 1st to 15th rows of the C column, the 17th to 32th rows of the C column, and the D column. Odd rows from 17 rows to 31 rows, even rows from 2 rows to 16 rows in E column, 1 rows to 16 rows in F column, even rows from 18 rows to 32 rows in F column, 17 rows in G column The 8-bit gradation data signal information is given to the output transistors in the first to sixteenth rows of the thirty-two rows and the H column.

  Next, bit 7 gradation data signal information is applied to the output transistors in the even rows of the A column, the odd rows of the B column, the 1st to 16th rows of the G column, and the 17th to 32th rows of the H column. Subsequently, the output transistors of the even rows of the 2nd to 16th rows of the C column, the odd rows of the 17th to 31st rows of the D column, the odd rows of the 1st to 15th rows of the E column, and the 17th to 31st rows of the F column. Is given the information of the gradation data signal of bit6. Since bit 5 and below are the same as those of the implementation spirit 4, description thereof is omitted.

  As described above, in the current output type integrated circuit and gradation data signal supply method of the present embodiment, the output unit is composed of Nch MOS transistors, and 32 output transistors including one dummy transistor are arranged in the vertical direction and in the horizontal direction. A total of 256 arrays of 8 32 rows × 8 columns are provided. The gradation data signal supply method to the output transistor is as follows. First, the odd rows of the A column, the even rows of the B column, the odd rows of the 1st to 15th rows of the C column, the 17th to 32th rows of the C column, and the D column. Odd rows from 17 rows to 31 rows, even rows from 2 rows to 16 rows in E column, 1 rows to 16 rows in F column, even rows from 18 rows to 32 rows in F column, 17 rows in G column The 8-bit gradation data signal information is given to the output transistors in the first to sixteenth rows of the thirty-two rows and the H column. Next, bit 7 gradation data signal information is applied to the output transistors in the even rows of the A column, the odd rows of the B column, the 1st to 16th rows of the G column, and the 17th to 32th rows of the H column. Subsequently, the output transistors of the even rows of the 2nd to 16th rows of the C column, the odd rows of the 17th to 31st rows of the D column, the odd rows of the 1st to 15th rows of the E column, and the 17th to 31st rows of the F column. Is given the information of the gradation data signal of bit6. Next, the output transistors of the 1st row, 3rd row, 5th row, 7th row, 10th row, 12th row, 14th row and 16th row in the D column, 17th row, 19th row, 21st row, 23th row, 26th row in the E column The information of the bit 5 gradation data signal is given to the rows 28, 30, and 32. Subsequently, the gradation data signal information of bit 4 is given to the output transistors in the 2nd, 6th, 11th, and 15th rows in the D column, and the 18th, 22nd, 27th, and 31st rows in the E column. Next, the bit 3 gradation data signal information is given to the output transistors in the 4th and 13th rows of the D column and the 20th and 29th rows of the E column. Subsequently, the gradation data signal information of bit 2 is given to the output transistors in the D column 9 rows and the E column 25 rows. Next, the gradation data signal information of bit1 is given to the output transistor in the D column and 8 rows. Here, the bit information is divided into four.

  For this reason, even if the drive capability of the output transistor fluctuates by a linear function due to manufacturing variation (process fluctuation) that occurs in the manufacturing process, the output current of the output transistor increases linearly with respect to the change in gradation, and the ideal value curve is improved. In addition, even if the drive capability of the output transistor varies by a quadratic function due to manufacturing variations (process variation) that occur in the manufacturing process, the output current of the output transistor increases linearly with respect to the gradation change, and the ideal value It almost coincides with the curve. Therefore, similarly to the fourth embodiment, the differential fluctuation error and the integral fluctuation error can be reduced, and high gradation accuracy can be achieved.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the present invention is applied to the current output type source driver of the organic EL display device, but the present invention can also be applied to a current output type LED driver. In addition, although the case of 5 bit gradation (32 gradations) in Examples 1 to 3 and the case of 8 bit gradation (256 gradations) in Examples 4 and 5 has been described, it can be applied to other bit gradations.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A first output transistor that generates an output current based on a gradation data signal of bitm (m is a positive integer), and a gradation that is arranged on both sides of the first output transistor and is lower than the bitm Second and third output transistors that generate an output current based on a data signal, and the output transistors are used for nbit (n is an integer greater than or equal to 2 and n is an integer greater than or equal to 2) gradation display. 2 ⁿ transistors connected between the gates, arranged in parallel or in series, a transistor cell array unit provided with one dummy transistor instead of the output transistor, and a gate connected to the gate of the output transistor of the transistor cell array unit A current output type integrated circuit comprising a distributing mirror transistor for generating a reference current.

(Supplementary Note 2) A first output transistor that generates an output current based on a gradation data signal of bitm (m is a positive integer), and a gradation that is arranged on both sides of the first output transistor and is lower than the bitm Second and third output transistors that generate an output current based on a data signal, and the output transistors are used for nbit (n is an integer greater than or equal to 2 and n is an integer greater than or equal to 2) gradation display. 2 ⁿ transistors connected between the gates, arranged in a multi-stage × multi-column configuration, in which one dummy transistor is provided instead of the output transistor, and a gate of the output transistor of the transistor cell array unit A current output type integrated circuit comprising a distribution mirror transistor connected to the gate and generating a reference current Road.

(Supplementary Note 3) nbit (n is a positive integer greater than or equal to 2) is used for gradation display, gates are connected, 2 ⁿ output transistors are arranged in a multi-stage × multi-column configuration, and bit information is divided into k ( k is a positive integer greater than or equal to 1) a step of providing a gradation data signal of the least significant bit to the first and second output transistors at both ends of the transistor cell array unit, and provided at other than the both ends of the transistor cell array unit Providing a gradation data signal of bitm (m is n or less and m is a positive integer) to the third and fourth output transistors, and a fifth provided between the third and fourth output transistors. And a sixth output transistor provided at the center of the k-divided transistor cell array portion. Providing a gradation data signal of the most significant bit to the register.

(Supplementary note 4) nbit (n is a positive integer of 2 or more) gradation display, 2 ⁿ output transistors connected between gates are arranged in parallel or in series, and bit information is divided into k (k is 1 A step of providing a gradation data signal of the least significant bit to the first and second output transistors at both ends of the transistor cell array unit in which one of the output transistors is replaced with a dummy transistor, and the transistor Providing a gradation data signal of bitm (m is n or less and m is a positive integer) to third and fourth output transistors provided at both ends of the cell array unit; and the third and fourth Providing a gradation data signal higher than bitm to a fifth output transistor provided between the output transistors; Gradation data comprising the steps of providing a gradation data signal of the most significant bit to a sixth output transistor provided at the center of the transistor cell array section, and providing the dummy transistor adjacent to the sixth output transistor. Signal supply method.

(Supplementary Note 5) nbit (n is a positive integer greater than or equal to 2) used for gradation display, 2 ⁿ output transistors connected between gates are arranged in a multi-stage × multi-column configuration, and bit information is divided into k ( k is a positive integer greater than or equal to 1, and one of the output transistors is replaced with a dummy transistor, and a gradation data signal of the least significant bit is provided to the first and second output transistors at both ends of the transistor cell array unit; Applying a gradation data signal of bitm (m is n or less and m is a positive integer) to third and fourth output transistors provided at both ends of the transistor cell array unit; Applying a gradation data signal higher than bitm to a fifth output transistor provided between the fourth output transistors; And a step of providing a gradation data signal of the most significant bit to a sixth output transistor provided at the center of the transistor cell array portion, and a step of providing the dummy transistor adjacent to the sixth output transistor. Data signal supply method.

(Supplementary note 6) The current output type integrated circuit according to any one of supplementary notes 1 and 2, wherein the output transistor is an Nch MOS transistor.

1 is a schematic block diagram showing a configuration of an organic EL display device according to Example 1 of the present invention. FIG. 3 is a circuit diagram illustrating an output unit of the current output type source driver according to the first embodiment of the invention. FIG. 3 is a diagram illustrating an arrangement of output transistors in a transistor cell array unit according to the first embodiment of the invention. The figure which shows the linear function fluctuation | variation of the drive capability of the output transistor which concerns on Example 1 of this invention. FIG. 5 is a characteristic diagram illustrating a relationship between gradation of the organic EL display device and output current when a linear function variation of the drive capability of the output transistor according to the first embodiment of the present invention occurs. FIG. 10 is a diagram illustrating an arrangement of output transistors in a transistor cell array unit according to the second embodiment of the invention. The figure which shows the quadratic function fluctuation | variation of the drive capability of the output transistor which concerns on Example 2 of this invention. FIG. 8A is a characteristic diagram showing the relationship between gradation and output current of an organic EL display device according to Example 2 of the present invention, FIG. 8A is a characteristic diagram when a linear function variation occurs, and FIG. 8B is a quadratic function. A characteristic diagram when fluctuation occurs. The characteristic view of Example 1 which shows the relationship between the gradation of an organic electroluminescence display at the time of quadratic function fluctuation | variation generation | occurrence | production of Example 2 of this invention, and output current. The figure which shows arrangement | positioning of the output transistor of the transistor cell array part which concerns on Example 3 of this invention. The characteristic view which shows the relationship between the gradation of an organic electroluminescence display which concerns on Example 3 of this invention, and output current. The figure which shows arrangement | positioning of the output transistor of the transistor cell array part which concerns on Example 4 of this invention. The characteristic view which shows the relationship between the gradation of an organic electroluminescence display at the time of linear function fluctuation | variation generation | occurrence | production of Example 4 of this invention, and output current. The characteristic view which shows the relationship between the gradation of an organic electroluminescence display at the time of quadratic function fluctuation | variation generation | occurrence | production of Example 4 of this invention, and output current. FIG. 10 is a diagram illustrating an arrangement of output transistors in a transistor cell array unit according to a fifth embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Organic EL display device 2 Display controller 3 DC-DC converter 4 Display panel (OELD)
5 Gate driver 6 Source driver 7 Output unit 11 Reference current source 12 Output control circuit 13, 13a, 13b, 13c Transistor cell array unit AVdd Analog high potential side power supply D1 to D31 Gradation data signal Istd Reference current Iout Output current NT1 to NT31 Output transistor NTK Distribution mirror transistor OUT Output terminal PV Precharge voltage SW1 to SW31 Switch Vss Low potential side power supply

Claims (5)

A first output transistor that generates an output current based on a tone data signal of bitm (m is a positive integer), and arranged on both sides of the first output transistor, and based on a tone data signal that is lower than the bitm Second and third output transistors that generate output current, and the output transistors are used for nbit (n is an integer greater than or equal to 2 and n is an integer greater than or equal to 2) gradation display, and the gates are connected. A transistor cell array section;
A distribution mirror transistor having a gate connected to a gate of the output transistor of the transistor cell array unit and generating a reference current;
A current output type integrated circuit comprising: A first output transistor that generates an output current based on a tone data signal of bitm (m is a positive integer), and arranged on both sides of the first output transistor, and based on a tone data signal that is lower than the bitm Second and third output transistors for generating an output current, and the output transistors are used for nbit (n is an integer greater than or equal to m and n is an integer greater than or equal to 2) gradation display, and the total number 2 ⁿ −1 A transistor cell array part which is arranged in parallel or in series, with gates connected to each other or 2 ⁿ
A distribution mirror transistor having a gate connected to a gate of the output transistor of the transistor cell array unit and generating a reference current;
A current output type integrated circuit comprising: A first output transistor that generates an output current based on a tone data signal of bitm (m is a positive integer), and arranged on both sides of the first output transistor, and based on a tone data signal that is lower than the bitm Second and third output transistors for generating an output current, and the output transistors are used for nbit (n is an integer greater than or equal to m and n is an integer greater than or equal to 2) gradation display, and the total number is 2 ⁿ A transistor cell array unit connected between the gates and arranged in a multi-stage × multi-column configuration;
A distribution mirror transistor having a gate connected to a gate of the output transistor of the transistor cell array unit and generating a reference current;
A current output type integrated circuit comprising: A first output transistor that generates an output current based on a tone data signal of bitm (m is a positive integer), and arranged on both sides of the first output transistor, and based on a tone data signal that is lower than the bitm Second and third output transistors for generating an output current and a fourth output transistor for generating an output current based on the gradation data signal of the most significant bit, and the output transistor is nbit (n is m In the above, and n is an integer of 2 or more) used for gradation display, the total number is ²ⁿ , bit information is divided into k (k is a positive integer of 1 or more), the gates are connected, and are connected in parallel or in series. The fourth transistor is arranged in the center of any one of the transistor cell array sections divided into k,
A distribution mirror transistor having a gate connected to a gate of the output transistor of the transistor cell array unit and generating a reference current;
A current output type integrated circuit comprising: nbit (n is a positive integer greater than or equal to 2) used for gradation display, 2 ⁿ −1 or 2 ⁿ output transistors connected between gates are arranged in parallel or in series, and bit information is divided into k (k Is a positive integer greater than or equal to 1), providing a gradation data signal of the least significant bit to the first and second output transistors at both ends of the transistor cell array unit;
Providing a gradation data signal of bitm (m is n or less and m is a positive integer) to the third and fourth output transistors provided at both ends of the transistor cell array unit;
Providing a gradation data signal higher than bitm to a fifth output transistor provided between the third and fourth output transistors;
Providing a gradation data signal of the most significant bit to a sixth output transistor provided in the center of the transistor cell array section divided into k;
A gradation data signal supply method comprising:

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