JP2007067781A - Cross connection apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the phase difference between paths by extracting the phase difference, and adjusting time by a cross connection apparatus. <P>SOLUTION: A lower-order cross connection section 20 is provided with a low-speed channel 201, a memory 202, a means 203 for writing the frame data of an inputted low-speed signal on the memory 202 in a predetermined order, and a means 204 for reading the written frame data of the low-speed signal from the memory 202 in the predetermined order and outputting the data from the low-speed channel 201. A higher-order cross connection section 10 is composed of a high-speed channel 101, a memory 102, a means 103 for writing the frame data of an inputted high-speed signal on the memory 102 in a predetermined order, a means 104 for reading the written frame data of the high-speed signal from the memory 102 in the predetermined order and outputting the data from the high-speed channel 101, and a means 106 for controlling the output timing of the frame data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a cross-connect device, and more particularly to a cross-connect device that eliminates a phase difference in a network by extracting a phase difference between paths and performing time adjustment.

Conventionally, SDH (Synchronous Digital Hierarchy) was internationally standardized in 1988 as a multiplexing system that can be efficiently applied to various communication services including not only telephones but also data and video.
The SDH network has many merits such as the ability to connect different vendors' transmission devices, the realization of advanced functions with a simple device configuration, and excellent operational maintenance. It contributes to the development of the network.
Various SDH apparatuses have been proposed in order to further bring out the effects of these merits (for example, Patent Documents 1 and 2).

Among the SDH apparatuses, there is a cross-connect apparatus that can improve network line efficiency and improve reliability by performing fine line setting.
The cross-connect device mainly performs line editing at each node (relay station and terminal station) constituting the SDH network. Specifically, the cross-connect device is connected to the exchange by exchanging time slots based on program control. It serves to collect lines according to purpose, such as lines, lines connected to dedicated transmission devices, and lines that pass through nodes and are transmitted to other nodes.
Then, new technologies relating to a cross-connect control system that is the basis of this cross-connect device have been proposed (see, for example, Patent Documents 3 and 4).

JP 03-208428 A (page 1-2, FIG. 1) Japanese Patent Laid-Open No. 06-177959 (page 1-3, FIG. 1) JP 2004-129111 A (page 1-2, FIG. 1) JP 09-247197 A (page 1-2, FIG. 1)

However, in the conventionally proposed cross-connect control method and the like as described above, a phase difference may occur between paths passing through nodes by combining a high-order cross-connect device and a low-order cross-connect device. .
For example, as shown in FIG. 7, one is a path (P1) that passes an input signal through a high-order cross-connect unit 10 without converting it into a low-speed signal, and the other is a specific low-speed signal. This is a path that passes through the low-order cross-connect unit 20 for separation or insertion. Specifically, the path passes from the high-order cross-connect unit 10 through the low-order cross-connect unit 20 and then back again from the high-order cross-connect unit 10. This is the output path (P2). The P1 and P2 paths are the same in that both are high-speed paths that pass through the same node (higher-order cross-connect unit 10), but the P2 path has a longer path length than the P1 path, and is transmitted. A delay occurs, resulting in a phase difference between P1 and P2.

When such a phase difference occurs, there is a problem in that data is lost because the main signal is momentarily interrupted when a path is switched or a setting is changed.
In addition, when a switch, router, or the like is connected to the client of the cross-connect device, it is necessary to relearn the routing information due to the momentary interruption of the packet, and during that time, flooding occurs and lower priority is given to unnecessary packets. There was also a risk that the packet would be discarded.

  The present invention has been proposed in order to solve such problems of the conventional technology, and a cross-connect device that eliminates a phase difference in a network by extracting a phase difference between paths and performing time adjustment. The purpose is to provide.

  In order to achieve the above object, a cross-connect device according to the present invention comprises a high-order cross-connect unit for setting up a high-speed signal line, and terminates an input signal for multiplexing and multiplexing as described in claim 1. A cross-connect device including a termination unit for separation and a low-order cross-connect unit for setting a low-speed signal line, wherein the low-order cross-connect unit inputs a low-speed channel for inputting and outputting a low-speed signal Memory for temporarily storing low-speed signal frame data, low-speed frame data writing means for writing input low-speed signal frame data to the memory in a predetermined order, and low-speed data written by the low-speed frame data writing means Low-speed frame data reading means for reading signal frame data from the memory in a predetermined order and outputting from any channel; The high-order cross-connect unit includes a high-speed channel for inputting / outputting high-speed signals, a memory for temporarily storing frame data of input high-speed signals, and frame data of input high-speed signals in the memory in a predetermined order. High-speed frame data writing means for writing, high-speed frame data reading means for reading frame data of the high-speed signal written by the high-speed frame data writing means from the memory in a predetermined order, and outputting from any high-speed channel; Phase control means for controlling the output timing of the frame data by the high-speed frame data reading means.

According to the cross-connect device of the present invention having such a configuration, the high-speed signal input to the high-order cross-connector section is temporarily written in the memory, and is generated between paths by adjusting the signal output timing. It is possible to eliminate the phase difference.
For example, in the case of a high-speed signal passing through the high-order cross-connect unit of the cross-connect device, a path that is simply input from one high-speed channel of the high-order cross-connect unit and directly output from the other high-speed channel, and one high-speed cross-connect unit After the high-speed signal input from the channel is converted to a low-speed signal at the termination part, it is folded back at the low-order cross-connect part, converted again to the high-speed signal via the termination part, and the same path as that output from other high-speed channels However, since the path lengths are different, a phase difference occurs between the paths.
Therefore, by outputting the output of one path with the phase difference delayed compared to the normal timing, the relative transmission delay of the other path can be absorbed, and as a result, the phases between the paths can be matched. It becomes.

As a result, in the present invention, when the path is switched or the setting is changed due to the phase difference between the paths, the main signal is not momentarily interrupted, and data loss due to the instantaneous interruption is prevented. Can do.
In addition, even when a switch, router, or the like is connected to the client of the cross-connect device, packets are not momentarily interrupted, and there is no need to relearn routing information. It is possible to effectively prevent a low-priority packet from being discarded due to an unnecessary packet due to flooding during learning.
Furthermore, by making it possible to separate the high-order cross-connect part and the low-order cross-connect part, it is only necessary to arrange the low-order cross-connect part as necessary, so that the cost can be reduced. A flexible network can be constructed.

  In the cross-connect device according to the present invention, as described in claim 2, the low-order cross-connect unit is configured such that one data in the frame data is written into the memory by the low-speed frame data writing unit. A low-speed path transit time extracting unit that extracts a time until reading is performed by the low-speed frame data reading unit; and the high-order cross-connect unit writes the one data into a memory by the high-speed frame data writing unit. A high-speed path passage time extracting means for extracting a time from when the high-speed frame data reading means performs reading, and a time extracted by the high-speed path passage time extracting means as A, and the low-speed path passage time When the time extracted by the extraction means is B, after adding a time difference of (A + B), A configuration equipped with phase control means to start reading the issue of frame data.

According to the cross-connect device of the present invention having such a configuration, the path differs for a path that is directly output from another channel without being converted into a low-speed signal from the high-speed signal input from the channel of the high-order cross-connect unit. Output is made with a time difference corresponding to the transmission delay occurring in other paths.
For this reason, it is possible to eliminate a phase difference from other paths that occurs in a path passing through the high-order cross-connect unit.
Thereby, in the present invention, it is possible to effectively prevent the occurrence of instantaneous interruption of the main signal and instantaneous interruption of the packet due to the phase difference between the paths.

  In the cross-connect device according to the present invention, the signal to be handled is the ITU-T Recommendation G. 707, a VC-3 (Virtual Container-3) path or a VC-4 (Virtual Container-4) path. TU-11 (Tributary Unit-11) path or TU-12 (Tributary Unit-12) path defined in 707.

  According to the cross-connect device of the present invention having such a configuration, the signal handled is ITU-T recommendation G.264. Since it conforms to the SDH system defined in 707, it has good compatibility with many currently used SDH devices and SDH networks, and can be a highly versatile device.

  In the cross-connect device according to the present invention, as described in claim 4, the high-speed signal is an STS-1 Synchronous Payload Envelope that is defined by ANSI (American National Standards Institute). ) Path or STS-3c SPE (STS-3c Synchronous Payload Envelope) path, and the low-speed signal is a VT1.5 (Virtual Tributary 1.5) path or VT2 (Virtual Tributary 2.0) path defined by ANSI. It is as.

  According to the cross-connect device of the present invention having such a configuration, the signal to be handled conforms to the SONET (Synchronous Optical Network) system defined by ANSI T1.105 or the like, so that the SONET device is not limited to the SDH device. It can also be used as a highly versatile device.

  According to another aspect of the phase adjustment method of the present invention, the step of writing the frame data of the input high-speed signal to the memory in a predetermined order and the frame data of the high-speed signal written to the memory are predetermined. Reading out in order, outputting from any high-speed channel, writing input low-speed signal frame data to memory in a predetermined order, and reading low-speed frame data written in memory in a predetermined order A step of outputting from an arbitrary low-speed channel, a step of extracting low-speed path passage time extraction means from the time one piece of data in the frame data is written to the memory until the reading is performed, and a high-speed path passage Time extraction means extracts the time from when the one data is written to the memory until it is read And when the time extracted by the high-speed path passage time extraction means is A and the time extracted by the low-speed path passage time extraction means is B, a time difference of (A + B) is added, And a step of starting reading out the frame data of the signal.

According to the phase adjustment method of the present invention having such a configuration, the high-speed signal input to the high-order cross connector portion is temporarily written in the memory, and the timing of signal output is adjusted to generate a difference in path length. It is possible to eliminate the phase difference.
Thus, according to the phase adjustment method of the present invention, when the path is switched or the setting is changed due to the phase difference between the paths, the main signal is not instantaneously interrupted. Missing or the like can be prevented.
In addition, even when a switch, router, or the like is connected to the client of the cross-connect device, packets are not momentarily interrupted, and there is no need to relearn routing information. It is also possible to prevent a low-priority packet from being discarded due to an unnecessary packet due to flooding during learning.

According to another aspect of the present invention, a phase adjustment program includes a high-order cross-connect unit that sets up a high-speed signal line, a termination unit that terminates an input signal, and multiplexes and demultiplexes. , A computer that constitutes a cross-connect device composed of a low-order cross-connect unit for setting a low-speed signal line,
Means for writing input high-speed signal frame data to memory in a predetermined order, means for reading high-speed signal frame data written to memory in a predetermined order, and outputting them from any high-speed channel, input low-speed signal frame Means for writing data to memory in a predetermined order, means for reading out frame data of low-speed signals written in memory in a predetermined order, and outputting them from any low-speed channel, and one data in frame data is written to memory A low-speed path passage time extraction unit that extracts a time until reading is performed, a high-speed path passage time extraction unit that extracts a time from when the one data is written to the memory until the reading is performed, The time extracted by the high-speed path passage time extraction means is A, and the low-speed path passage time extraction means When a B the extracted time Te, is a program for functioning as after adding the time difference (A + B), means for initiating the reading of the frame data of the high-speed signal.

Thus, the present invention can also be provided as a program.
Thus, the present invention can be realized by installing the program not only in the SONET / SDH apparatus but also in various transmission apparatuses, and can be provided as a phase adjustment program excellent in versatility and expandability.

As described above, according to the cross-connect device of the present invention, a high-order cross-connector portion and a low-order cross-connector portion are provided, and signals can be exchanged with each other by connecting a terminal portion between them. Even in the same path, the path length differs and transmission time may shift (phase difference), but the high-speed signal or low-speed signal input to the high-order cross connector or low-order cross connector is temporarily stored in memory. And the phase difference can be eliminated by adjusting the timing of signal output.
Thereby, in the present invention, it is possible to prevent the occurrence of instantaneous interruption of the main signal and instantaneous interruption of the packet due to the phase difference between the paths.
In addition, by making it possible to separate the high-order cross-connect part and the low-order cross-connect part, it is only necessary to arrange the low-order cross-connect part as necessary, so that the cost can be reduced and flexible. This makes it possible to construct a network with excellent versatility.

A preferred embodiment of the present invention will be described below with reference to FIGS.
Here, the cross-connect device of the present embodiment described below is realized by processing, means, and functions executed by a computer in accordance with a program (software) instruction. The program sends a command to each component of the computer to perform predetermined processing and functions as shown below. That is, each process / means in the cross-connect device of the present embodiment is realized by specific means in which a program and a computer cooperate.
Note that all or part of the program is provided by, for example, a magnetic disk, optical disk, semiconductor memory, or any other computer-readable recording medium, and the program read from the recording medium is installed in the computer and executed. The The program can also be loaded and executed directly on a computer through a communication line without using a recording medium.

FIG. 1 is a block diagram showing a schematic configuration of a cross-connect device according to an embodiment of the present invention.
The cross-connect device 1 of the present invention includes a high-order cross-connect unit 10, a low-order cross-connect unit 20, a termination unit 30, a high-speed interface 40 (40W, 40E), and a low-speed interface 50. Note that the low-order cross-connect unit 20, the termination unit 30, and the low-speed interface 50 can be separated from the apparatus as necessary.

The high-order cross-connect unit 10 performs high-speed signal line setting, and the low-order cross-connect unit 20 performs low-speed signal line setting.
The termination unit 30 is disposed between the high-order cross-connect unit and the low-order cross-connect unit, and separates and multiplexes high-speed signals into low-speed signals and multiplexes low-speed signals into high-speed signals.
The high-speed interfaces 40W and 40E normally input / output high-speed signals such as VC-3 and VC-4 to / from the high-order cross-connect unit 10.
The low-speed interface 50 normally inputs / outputs a low-speed signal from a lower-level device or the like with the low-order cross-connect unit 20.

The high-speed signal input through the high-speed interface 40W is subjected to line setting in units of VC-3 / VC-4 in the high-order cross-connect unit 10, and when the termination of the low-speed signal is not necessary, the high-speed interface 40E Is output. This path is referred to as a high speed path 60.
On the other hand, in order to separate a specific low-speed signal from a high-speed signal input via the high-speed interface 40W, it is terminated at the termination unit 30 and line setting is required at the low-order cross-connect unit 20.
At this time, a high-speed path output to the high-speed interface 40E through the high-order cross-connect unit 10, the terminal unit 30, and the low-order cross-connect unit 20 and again through the terminal unit 30 and the high-order cross-connect unit 10 is high-speed. The path 61 is used.

  Further, a low-speed path that transmits and receives to / from a lower-level device or the like via the low-speed interface 50 is a low-speed path 70. A low-speed path 71 that is output to the connection unit 10 is referred to as a low-speed path 71.

Next, an outline of the operation of the cross-connect device according to the embodiment of the present invention will be described with reference to FIG.
The signal input from the high-speed interface 40W is subjected to line setting in units of VC-3 / VC-4 in the high-order cross-connect unit 10, and when separation into low-speed signals and line setting are not required, the high-speed interface 40E is used as it is. Is output from.

When separation into a low-speed signal and line setting are necessary, the termination unit 30 terminates the high-speed signal (VC-3 / VC-4 path or the like), and a plurality of low-speed signals (TU-11 / TU-12). Etc.), and only the necessary TU-11 / TU-12 paths are routed to the low-speed interface 50 by the low-order cross-connect unit 20.
Further, when there is an input from the low speed interface 50, it is output from the high order cross connect unit 10 to the high speed interfaces 40W and 40E via the low order cross connect device 20 and the termination unit 30.
On the other hand, for the high-speed path 60 that passes through from the high-speed interface 40W to the high-speed interface 40E, the delay time of the high-speed path 61 that passes through the high-speed interface 40E via the termination unit 30, the low-order cross-connect unit 20, and the termination unit 30 again. Can be output from the high-speed interface 40E in the same phase by giving the read delay of the above to the read phase from the high-order cross-connect unit 10 in advance.

Next, main parts of the cross-connect device according to the embodiment of the present invention will be described with reference to FIGS.
[High-order cross-connect unit 10]
FIG. 2 is a block diagram showing a detailed configuration of a high-order cross-connect unit constituting the cross-connect device according to the embodiment of the present invention.
The high-order cross-connect unit 10 includes a high-speed channel 101, a memory 102, a high-speed frame data writing unit 103, a high-speed frame data reading unit 104, a high-speed path transit time extracting unit 105, and a phase control unit 106, as shown in FIG. ing.

The high-speed channel 101 inputs and outputs a high-speed signal with the high-speed interface 40 and the like. In addition, high-speed signals are input / output to / from the low-order cross-connect unit 20 via the termination unit 30.
The memory 102 temporarily stores frame data of a high-speed signal input from the high-speed channel 102. The frame data is configured as one bit string by time-dividing a plurality of input data and arranging them in a predetermined time slot.

The high-speed frame data writing unit 103 writes high-speed signal frame data input from the high-speed channel 102 into the memory 102.
The high-speed frame data reading unit 104 reads the frame data of the high-speed signal written by the high-speed frame data writing unit 103 from the memory 102 and outputs it from the other high-speed channel 101.
Here, a random access / sequential read method is employed in which the time slots of the frame data are written in the order in which they need to be replaced, and are read out in accordance with the order at the time of output.

The high-speed path transit time extraction unit 105 calculates the time required from the time when one data included in the frame data is written to the memory 102 by the high-speed frame data writing unit 103 until the high-speed frame data reading unit 104 reads the data. To extract.
The phase control means 106 controls the output timing of the frame data by the high-speed frame reading means 104. For example, by delaying the output timing by a predetermined time compared to the normal timing, the delay that has occurred with the other paths can be eliminated, and the phases can be matched.

[Low-order cross-connect unit 20]
FIG. 3 is a block diagram showing a detailed configuration of a low-order cross-connect unit constituting the cross-connect device according to the embodiment of the present invention.
As shown in FIG. 3, the low-order cross-connect unit 20 includes a low-speed channel 201, a memory 202, a low-speed frame data writing unit 203, a low-speed frame data reading unit 204, and a low-speed path passage time extracting unit 205.

The low-speed channel 201 inputs and outputs signals with a low-speed interface 50 (not shown). In addition, input / output to / from the high-order cross-connect unit 10 is performed via the termination unit 30. It is also possible to set so that the signal from the high-order cross-connect unit 10 is not output to the low-speed interface 50 but is returned as it is and is output to the high-order cross-connect unit 10 again via the termination unit 30.
Since other functions 202 to 205 are substantially the same as the functions 102 to 105 described above, a detailed description thereof will be omitted.

Next, the operation of the cross-connect device according to one embodiment of the present invention will be described with reference to FIGS. 4, 5, and 6.
FIG. 4 is a phase relationship diagram showing the relationship between writing and reading to the memory used in the high-order cross-connect unit and the low-order cross-connect unit constituting the cross-connect device according to the embodiment of the present invention.
Each of the cross-connect units 10 and 20 is generally composed of a space switch or a time switch. In the present embodiment, the implementation using the time switch will be described. The time switch replaces the time slots by controlling the order of writing to and reading from the memory. In this embodiment, a random write / sequential read method is employed.

(1) When there is no cross-connect to a low-speed path When there is no cross-connect to a low-speed path such as TU-11 / TU-12, the order in which time slots need to be replaced in the memory 102 of the high-order cross-connect unit 10 The function as a cross-connect device is realized by writing to and reading sequentially.
(2) When there is a cross-connect to the low-speed path When there is a cross-connect to the low-speed path, first, the input signal from the high-speed interface 40W is VC-3 / VC-4 units at the high-order cross-connect unit 10. When there is a low-speed signal that needs to be terminated, the corresponding VC-3 / VC-4 path is terminated at the termination unit 30 and output to the low-speed interface 50 via the low-order cross-connect unit 20.

In the memory 202 of the low-order cross-connect unit 20, as in the high-order cross-connect unit 10, writing to the memory 202 is performed sequentially according to the required time slot replacement order according to the multiplexing order of TU-11 / TU-12. read out.
On the other hand, a signal input via the low-speed interface 50 is cross-connected through the low-order cross-connect unit 20 and the termination unit 30, and another VC-3 / VC-4 is transmitted in the high-order cross-connect unit 10. It is multiplexed with the path and output from the high speed interface 40W or 40E.
Similarly, in the memory 102 of the high-order cross-connect unit 10, data is written in the order in which the time slots need to be replaced, and read sequentially.
FIG. 5 is a diagram showing a flow of internal data in each memory built in the high-order cross-connect unit and the low-order cross-connect unit that constitute the cross-connect device according to the embodiment of the present invention.

(1) When there is no cross-connect to the low-speed path When there is no cross-connect to the low-speed path, the data written from the position of “A” bit in the figure is the memory 102 of the high-order cross-connect unit 10 after t1 time. Read from.
(2) When there is a cross-connect to the low-speed path When there is a cross-connect to the low-speed path, the data written from the position of “A” bit in the figure is the memory 102 of the high-order cross-connect unit 10 after t2 hours. And is written into the memory 202 of the low-order cross-connect unit 20 on the same time axis. Data is read from the memory 202 of the low-order cross-connect unit 20 after t3 time, and a read delay of t1 is given so that t1 = t2 + t3.
As a result, it is possible to relatively eliminate the signal transmission delay that occurs between the paths (1) and (2).

Next, a memory control system of the cross-connect device according to the present embodiment will be described with reference to FIG.
FIG. 6 is a diagram showing an overall operation flow of the memory control method of the cross-connect device according to the embodiment of the present invention. Specifically, this represents an operation of extracting an arbitrary VC-3 path from the STM-N, and further inserting and separating a TU-11 path therefrom. The STM-N frame has a bit rate that is an integral multiple of the STM-1 frame (155.52 Mbit / s), and 1, 4, and 64 are standardized as the value of N.
In the STM-N, the VC-3 # 1 path (high-speed path 60) is through and is output as it is without being cross-connected by the low-order cross-connect unit 20.
On the other hand, after the VC-3 # 2 path (high-speed path 61) is written and read in the internal memory-2 of the high-order cross-connect unit, the pointer unit processing of the VC-3 / VC-4 path is performed in the termination unit 30. Done.

After that, the data is written in the internal memory of the low-order cross-connect unit, inserted, separated, and cross-connected in units of TU-11 / TU-12, and written / read out in the internal memory-3 of the high-order cross-connect unit. Done.
At that time, the internal memory-1 of the high-order cross-connect unit 1 has a delay amount t1 (= t2 + t3) corresponding to the memory write / read phase difference between the low-order cross-connect unit internal memory and the high-order cross-connect internal memory-3. By delaying the readout phase, the same phase as that of the VC-3 # 2 path can be obtained when multiplexing to the STM-N again.

  As described above, according to the cross-connect device 1 of the present embodiment, the high-speed path 60 that passes through and outputs a high-speed signal such as VC-3 / VC-4 separated from the STM-N signal, and the VC- After the 3 / VC-4 path is converted into a low-speed signal such as TU-11 / TU-12, the transmission delay that occurs between the high-speed paths 61 that are multiplexed again with the high-speed signal and output can be eliminated. The phases between the paths can be matched.

Thereby, in this embodiment, when the path is switched or the setting is changed due to the phase difference between the paths, the main signal is not momentarily interrupted, and data loss due to the instantaneous interruption is prevented. be able to.
In addition, even when a switch, router, or the like is connected to the client of the cross-connect device, packets are not momentarily interrupted, and there is no need to relearn routing information. It is possible to effectively prevent problems such as occurrence of flooding during learning and discarding low priority packets due to unnecessary packets.

Furthermore, by making the high-order cross-connect part 10 and the low-order cross-connect part 20 separable, a low-order cross-connect part can be arranged as necessary.
For this reason, cost can be reduced, and a flexible and highly versatile network can be constructed.

The cross-connect device according to the present invention has been described with reference to the preferred embodiment. However, the cross-connect device according to the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. It goes without saying that implementation is possible.
For example, the cross-connect device of the present invention may be another transmission device provided with a memory, and the network is not limited to a SONET / SDH network but may be a network according to another standard.

  The present invention can be suitably used for a cross-connect device provided with phase control means.

1 is a block diagram illustrating a schematic configuration of a cross-connect device according to an embodiment of the present invention. It is a block diagram which shows the detailed structure of the high order cross-connect part which comprises the cross-connect apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows the detailed structure of the low order cross-connect part which comprises the cross-connect apparatus which concerns on one Embodiment of this invention. FIG. 4 is a phase relationship diagram illustrating a relationship between writing and reading to a memory used in a high-order cross-connect unit and a low-order cross-connect unit that constitute a cross-connect device according to an embodiment of the present invention. It is the figure which showed the flow of the internal data of each memory incorporated in the high-order cross-connect part which comprises the cross-connect apparatus based on one Embodiment of this invention, and a low-order cross-connect part. It is the figure which showed the flow of the whole operation | movement about the memory control system of the cross-connect apparatus which concerns on one Embodiment of this invention. It is the figure which showed operation | movement of the conventional cross-connect control system etc.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Cross-connect apparatus 10 High-order cross-connect part 101 High-speed channel 102 Memory 103 High-speed frame data writing means 104 High-speed frame data reading means 105 High-speed path passage time extraction means 106 Phase control means 20 Low-order cross-connect part 201 Low-speed channel 202 Memory 203 Low-speed frame data writing means 204 Low-speed frame data reading means 205 Low-speed path passage time extracting means 206 Phase control means 30 Terminating section 40 High-speed interface 50 Low-speed interface

Claims (6)

A high-order cross-connect unit that sets up a high-speed signal line, a termination unit that terminates an input signal, performs multiplexing and demultiplexing, and a low-order cross-connect unit that sets up a low-speed signal line A connecting device,
The low-order cross-connect unit is
A low-speed channel that inputs and outputs low-speed signals;
A memory for temporarily storing the frame data of the input low-speed signal;
Low-speed frame data writing means for writing input low-speed frame data into the memory in a predetermined order;
Low-speed frame data reading means for reading the frame data of the low-speed signal written by the low-speed frame data writing means from the memory in a predetermined order and outputting from any low-speed channel,
The high-order cross-connect unit is
A high-speed channel that inputs and outputs high-speed signals;
A memory for temporarily storing frame data of the input high-speed signal;
High-speed frame data writing means for writing the input high-speed signal frame data into the memory in a predetermined order;
High-speed frame data reading means for reading the frame data of the high-speed signal written by the high-speed frame data writing means from the memory in a predetermined order and outputting from any high-speed channel;
And a phase control means for controlling the output timing of frame data by the high-speed frame data reading means. The low-order cross-connect unit is
Comprising low-speed path passage time extraction means for extracting the time from when one data in the frame data is written to the memory by the low-speed frame data writing means until reading is performed by the low-speed frame data reading means;
The high-order cross-connect unit is
A high-speed path passage time extracting unit that extracts a time from when the one data is written to the memory by the high-speed frame data writing unit until the high-speed frame data reading unit reads the data;
When the time extracted by the high-speed path passage time extraction means is A and the time extracted by the low-speed path passage time extraction means is B, after adding the time difference of (A + B), the frame data of the high-speed signal The cross-connect device according to claim 1, further comprising: a phase control unit that starts reading data.   The high-speed signal is an ITU-T G. The low-speed signal is a VC-3 path or a VC-4 path specified in 707. The cross-connect device according to claim 1, wherein the cross-connect device is a TU-11 path or a TU-12 path defined in 707.   The high-speed signal is an STS-1 SPE path or STS-3c SPE path specified by ANSI, and the low-speed signal is a VT1.5 path or VT2 path specified by ANSI. The cross-connect device according to 1 or 2. Writing the frame data of the input high-speed signal into the memory in a predetermined order;
Reading out the frame data of the high-speed signal written in the memory in a predetermined order and outputting it from an arbitrary high-speed channel;
Writing the frame data of the input low-speed signal into the memory in a predetermined order;
Reading out the frame data of the low-speed signal written in the memory in a predetermined order and outputting from any low-speed channel;
A step of extracting a low-speed path passage time extraction unit from a time when one piece of data in the frame data is written to the memory until a reading is performed;
A step of extracting a time from when the one piece of data is written in the memory until the reading is performed;
When the time extracted by the high-speed path passage time extraction means is A and the time extracted by the low-speed path passage time extraction means is B, after adding the time difference of (A + B), the frame data of the high-speed signal A phase adjustment method using a cross-connect device. A cross-connect device comprising a high-order cross-connect unit for setting a high-speed signal line, a termination unit for terminating and multiplexing and demultiplexing an input signal, and a low-order cross-connect unit for setting a low-speed signal line The computers that make up the
Means for writing the frame data of the input high-speed signal into the memory in a predetermined order;
Means for reading frame data of a high-speed signal written in a memory in a predetermined order and outputting it from an arbitrary high-speed channel;
Means for writing the frame data of the input low-speed signal into the memory in a predetermined order;
Means for reading out frame data of a low-speed signal written in a memory in a predetermined order and outputting it from an arbitrary low-speed channel;
A low-speed path passage time extracting means for extracting a time from when one data in the frame data is written to the memory until the reading is performed;
High-speed path passage time extraction means for extracting the time from when the one data is written to the memory until the reading is performed;
When the time extracted by the high-speed path passage time extraction means is A and the time extracted by the low-speed path passage time extraction means is B, after adding the time difference of (A + B), the frame data of the high-speed signal Means to start reading
Phase adjustment program to function as

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