JP2007066102A5

JP2007066102A5 -

Info

Publication number: JP2007066102A5
Application number: JP2005252620A
Authority: JP
Filing date: 2005-08-31
Publication date: 2008-09-04
Anticipated expiration: 2025-08-31

Claims

A memory controller for writing data to a nonvolatile memory and reading data from the nonvolatile memory,
A front-end unit that communicates with the outside,
A core controller that controls the operation of each part of the memory controller;
A back-end unit that performs read / write control on the nonvolatile memory;
A mode detection unit that determines whether the memory controller functions independently or in parallel based on an identification signal input to the first port;
An MS detection unit that determines whether to use the memory controller as a master or a slave controller based on the identification signal input to the second port;
The core control unit
When the mode detection unit determines that the memory controller functions in parallel, and the MS detection unit determines to use as a master controller, the data received from the outside by the front end unit is stored in the nonvolatile memory. based on the ID code recorded in the sexual memory, for each predetermined size, to transfers distributed to the third port for transferring the back end unit and the data,
When the mode detection unit determines that a plurality of memory controllers are allowed to function in parallel and the MS detection unit determines to use as a slave controller, the data input from the third port is used as the back end. Forward to the department
The memory controller, wherein when the mode detection unit decides to make the memory controller function independently, the data received from the outside by the front end unit is not distributed to the third port and transferred .

2. The memory according to claim 1, wherein the predetermined size to which the core control unit distributes data is a page size which is a unit of writing or a page size × N (N is a multi number in a multi-page program function). controller.

3. The memory controller according to claim 1, wherein the identification signal input to the first port and the second port has a voltage level that changes according to a power supply voltage supplied to the memory controller.

The identification signal input to the first port is a voltage level that changes according to the power supply voltage supplied to the memory controller, and the identification signal input to the second port is a signal supplied from an external device. The memory controller according to claim 1, wherein the memory controller is provided.

Comprising at least two memory modules including a non-volatile memory and a memory controller, each of the memory controllers comprising:
A front-end unit that communicates with the outside,
A core control unit for controlling the operation of each unit of the memory controller;
A back-end unit that controls writing of data to the nonvolatile memory and reading of data from the nonvolatile memory;
A mode detection unit that determines whether the memory controller functions independently or in parallel based on an identification signal input to the first port;
An MS detection unit that determines whether the memory controller is used as a master or a slave controller based on an identification signal input to the second port, and a mode detection unit and an MS detection of each of the memory controllers By determining the part, one of the memory controllers is used as a master controller, the other is used as a slave controller,
The core control unit of the memory module including a memory controller used as a master controller, the data received from the outside by the front end unit, based on an ID code recorded in the nonvolatile memory, for each predetermined size. Transfer to the end part and the third port that transfers data,
The core controller of the memory module including a memory controller to be used as a slave controller, the nonvolatile memory device, characterized by transferring the data inputted from the third port to the back end unit.

6. The nonvolatile memory device according to claim 5, wherein the predetermined size to which the core control unit distributes data is a page size that is a unit of data writing to the nonvolatile memory.

7. The identification signal input to the first port and the second port of each memory controller has a voltage level that changes according to a power supply voltage supplied to each memory controller. The non-volatile storage device described.

The identification signal used in the memory module including the memory controller used as a master controller is a voltage level that changes according to the power supply voltage supplied to the memory controller,
7. The nonvolatile memory device according to claim 5, wherein an identification signal used in the memory module including a memory controller used as a slave controller is a signal supplied from an external device.

Nonvolatile memory system comprising a nonvolatile memory device according to any one of claims 5-8, and a access device for performing access control of said nonvolatile memory device.