JP2007066039A - Shared memory apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shared memory apparatus capable of simplifying wiring up to a memory, preventing the reduction of performance due to the increase of areas and long-distance wiring and improving expansion in the scalability of a system. <P>SOLUTION: Each of memory systems 11-1 to 11-n includes a memory macro 12 such as a DRAM for storing data and a processor 13 for performing prescribed data processing by accessing the memory macro 12. The memory macro 12 having at least one memory interface 15 capable of transferring data is constituted so that areas including at least memory cells and memory interfaces are arranged in parallel in an aligned state of two-dimensional heights, and memory interfaces of memory macros aligned in the two-dimensional heights in respectively different memory systems are mutually connected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a shared memory device in which a plurality of memory systems including a processing device such as a processor are mixedly mounted and the memory of each system is shared.

If an architecture emphasizing parallel processing is employed in a system in which a plurality of memory systems are mixed, for example, a configuration as shown in FIG. 1 is obtained.
In the configuration of FIG. 1, the logic circuits (processors) 1-1 to 1-4 and the memory macros 2-1 to 2-4 have a one-to-one connection because priority is given to parallel processing.
In the configuration of FIG. 1, the logic circuit 1 and the memory macro 2 are connected in a one-to-one relationship in order to prioritize parallel processing. It is necessary to use a path.

  Therefore, a configuration in which the connection from the logic circuit 1 directly to the adjacent memory is generally performed by a crossbar (Xbar) 3 as shown in FIG.

  In the configuration of FIG. 1, as described above, the logic circuit 1 and the memory macro 2 are connected in a one-to-one relationship because priority is given to parallel processing, but the logic circuit 1 refers to the data of the adjacent logic circuit 1. In order to do this, it is necessary to use a path through a host device, and it is difficult to realize actual access.

In the configuration of FIG. 2, the logic circuit 1 can refer to the data of the adjacent logic circuit 1 without going through the host device, but the wiring from the logic circuit 1 to the memory 2 is very difficult. However, there is a disadvantage that the area is increased and the performance is lowered due to the long distance wiring.
Further, in the configuration using the crossbar 3 in FIG. 2, it is difficult to increase the scalability of the system scalability.

  An object of the present invention is to provide a shared memory device capable of simplifying wiring to a memory, preventing an increase in area and performance degradation due to long-distance wiring, and improving scalability of a system. .

  To achieve the above object, a shared memory device according to a first aspect of the present invention includes a plurality of memory systems including a processing device and at least one memory macro accessible by the processing device. The memory macro of the system has at least one memory interface capable of transferring data, and at least a region including the memory cell and the memory interface is arranged in parallel with a two-dimensional height, so that two-dimensional of different memory systems Memory macro memory interfaces having the same height are connected to each other.

  Preferably, at least one of the plurality of memory interfaces of different memory systems connected to each other has a latch in the data transfer wiring.

  Preferably, at least one of the plurality of memory interfaces of different memory systems connected to each other has a repeater capable of re-driving data transferred to the data transfer wiring.

  Preferably, a plurality of memory macros arranged in parallel in each of the memory systems are arranged with the same two-dimensional height for the entire area.

  Preferably, at least one of the plurality of memory macros arranged in parallel in each of the memory systems includes a second area other than the first area having a two-dimensional height including the memory cells and the memory interface. .

  Preferably, in each of the memory systems, a plurality of memory macros are arranged in a row, a plurality of memory macros of each memory system are arranged in a matrix, and the memory macros arranged in the matrix form have the same row. A macro group is formed by a plurality of memory macros arranged at the same time, and in each of the macro groups, an area including at least a memory cell and a memory interface is arranged in parallel with a two-dimensional height, and different memory systems Memory interfaces of memory macros having a two-dimensional height are connected to each other.

  Preferably, in each of the memory systems described above, the plurality of memory macros are connected to the processing device by individual wires.

  Preferably, in each of the above memory systems, the plurality of memory macros are connected to the processing device by a shared wiring.

  Preferably, in at least one of the macro groups, a plurality of memory macros are arranged with a two-dimensional height for the entire region.

  Preferably, in at least one of the macro groups, at least one of the plurality of memory macros includes a second region other than the first region having a two-dimensional height and including a memory cell and a memory interface. .

  A shared memory device according to a second aspect of the present invention includes a plurality of memory systems including a processing device, at least one memory macro accessible by the processing device, and a memory control unit that controls access to the memory macro. The memory control unit of each memory system exchanges information between the processor and the memory macro and also exchanges information with the memory control unit of a different memory system. The memory macro of each memory system performs data transfer. A memory having at least one memory interface capable of performing at least one memory, and having at least two memory cells and an area including the memory interface arranged in parallel with two-dimensional heights, and having two-dimensional heights of different memory systems Macro memory interfaces It is.

According to the present invention, data is transferred between memory macros through a memory interface capable of transferring data to the memory macro of each memory system.
Further, for example, when data to be accessed is written in a memory macro of one or more different memory systems, a write broadcast is performed through a data line between the memory macros.

According to the present invention, wiring to the memory can be simplified, an increase in area and performance degradation due to long-distance wiring can be prevented, and the scalability of the system scalability can be improved.
Further, according to the present invention, the processor can access data to the nearest local macro, and as a result, useless data transfer can be reduced and the load on the system bus can be reduced. There is an advantage that the processing capability can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 3 is a system configuration diagram of the shared memory device according to the first embodiment of the present invention.

  The shared memory device 10 includes a plurality of memory systems 11-1 to 11-n, which can be accessed between the memory systems 11-1 to 11-n, and has a multiprocessor architecture that emphasizes parallel processing. Adopted.

Each of the memory systems 11-1 to 11-n basically performs predetermined data processing by accessing a memory macro (MM) 12, such as a DRAM or SRAM, for storing data, or the memory macro 12. A processor (Processor: PRC) 13 as a processing device, and information (data and commands and addresses) between the processor 13 of the own stage and the memory macro 11, and a memory control unit of a different memory system This includes a memory control unit (MCU) 14 that exchanges information (only commands and addresses).
The memory macro 12 in the present embodiment includes a memory interface (MIF) 15 capable of transferring data, and the memory macro memory interface of a different memory system (an adjacent memory system in the present embodiment). They are connected to each other.
FIG. 1 is a conceptual diagram, and the arrangement position of the memory interface 15 in the memory macro 12 may be different from that in FIG.

Specifically, the memory system 11-1 includes a memory macro 12-1, a processor 13-1, and a memory control unit 14-1.
The memory system 11-2 includes a memory macro 12-2, a processor 13-2, and a memory control unit 14-2.
Similarly, the memory system 11-n includes a memory macro 12-n, a processor 13-n, and a memory control unit 14-n.

In the present embodiment, the memory systems 11-1 to 11-n are arranged in the Y direction (vertical direction) of the two-dimensional orthogonal coordinate system set in FIG. n), the memory control units 14 (-1 to -n), and the memory macros 12 (-1 to -n) are sequentially arranged in a form in which the widths are substantially aligned.
The memory systems 11-1 to 11-n having such an arrangement structure are arranged in parallel in the X direction of the orthogonal coordinate system.
For example, the memory macros 12-1 to 12-n of the memory systems 11-1 to 11-n are arranged with the height h1 in the Y direction from the reference line indicated by the reference sign BSL in FIG. . That is, the memory macros 12-1 to 12-n of the memory systems 11-1 to 11-n are arranged in parallel in the X direction (horizontal direction) with a two-dimensional height aligned.
Furthermore, in the present embodiment, the memory interfaces 15-1 to 15-n of the memory macros 12-1 to 12-n have heights h2 and h3 at two edges (sides) in the Y direction from the reference line BSL. Are arranged in parallel. That is, the memory interfaces 15-1 to 15-n of the memory macros 12-1 to 12-n have the same height (width) h4 in the Y direction and the same arrangement position in the Y direction, They are arranged in parallel in a straight line (a straight line in the horizontal direction).

The memory interface 15-1 of the memory macro 12-1 of the memory system 11-1 is connected to the memory interface 15-2 of the memory macro 12-2 of the adjacent memory system 11-2.
The memory interface 15-2 of the memory macro 12-2 of the memory system 11-2 is connected to the memory interface (15-3) of the memory macro (12-3) of the adjacent memory system (11-3) (not shown). Yes.
Similarly, the memory interface 15-n of the memory system 11-n is connected to the memory interface (15-n-1) of the memory macro (12-n-1) of the adjacent memory system (11-n-1) (not shown). It is connected to the.

  3 exemplifies a configuration in which a space is provided between the memory macros. However, a space is provided, a space is not provided, or a logic circuit is provided in a connection line of the memory interface 15. Various embodiments are possible.

As described above, in the shared memory device 10 according to the first embodiment, a memory interface capable of transferring data is provided in the memory macro of each memory system so that data can be transferred between the memory macros.
In the shared memory device 10 according to the first embodiment, the memory interfaces 15-1 to 15-n of the memory macros 12-1 to 12-n have the same height (width) h4 in the Y direction. Aligned in the Y direction and arranged in parallel in the X direction (straight line in the horizontal direction) eliminates unnecessary routing of the wiring connecting the memory macros, and wiring at the shortest distance Can be laid out.
Further, in the first embodiment, when data to be accessed is written to a memory macro of one or a plurality of different memory systems, write broadcast is performed through a data line between the memory macros.

  Hereinafter, specific configurations and functions of the memory control units 14 (-1 to -n) and the memory interfaces 15 (-1 to -n) of the memory macros 12 (-1 to -n) will be described.

  First, the memory control unit 14 of each memory system will be described. The memory control unit of each memory system has the same configuration.

  FIG. 4 is a block diagram showing an example of a memory control unit according to the present invention.

  4 includes a command FIFO (Command First In First Out: CMD FIFO) 141, a write latency counter (WLC) 142, a memory access management unit (MAMU) 143, Latches 144 to 146 and an AND gate 147 are included.

The command FIFO 141 stores a command and address issued by the processor 13 of the own memory system 11 and latches the command and address (C / A or CMD / ADDR) stored in response to the FIFO read signal FIFO-RD from the MAMU 143. Output to.
Further, the command FIFO 141 outputs a FIFO ready signal FIFO-RDY to the processor 13 in a ready state, and outputs a FIFO state signal FIFO-ST indicating the current state to the MAMU 143.

The write latency counter 142 receives a write enable signal WR-ENBL from the MAMU 143 when a write command for the memory macro 12 of the own memory system 11 is issued, and takes a predetermined number in consideration of the write latency. Counting is performed, and a data in ready signal DI-RDY indicating that the data input is ready is output to the processor 13.
The processor 13 that has received this data in ready signal DI-RDY issues write data, and this write data (Data In: DT IN) is once latched in the latch 146 and supplied to the memory macro 12. The

When the MAMU 143 receives a command and address (CMD / ADDR) and its valid signal (valid signal) LD (which may be expressed as ldi) for the memory macro 12 of its own memory system 11, the MAMU 143 decodes the input command, In response to the access to the memory macro 12 according to the write, read operation, etc., an access timing at which no collision occurs is generated, and the FIFO read signal FIFO-RD is transmitted so that the command and address are transferred to the memory macro 12 at this timing. The data is output to the command FIFO 141 and the latch 145.
If the command determined to be valid is a write command, the MAMU 143 outputs a write enable signal WR-ENBL to the write latency counter 142.

FIG. 5 is a diagram showing a configuration example of a MAMU (memory access management unit) in the memory control unit according to the present invention.
FIG. 6 is a diagram illustrating a configuration example of the ready check block in FIG.

  As shown in FIG. 5, the MAMU 143 basically has Ready Check Blocks (RCBs) 1431-0 to 1431-3 and selectors 1432 corresponding to the number n of memory systems (n = 4 in FIG. 5). A down counter (DCNT) 1433, and a MAMU state machine (SMCN) 1434.

As shown in FIGS. 5 and 6, each RCB 1431 (−0 to −3) determines the number of commands and addresses (CMD / ADDR) that are accessing the memory macro 12 of its own memory system 11 (FIGS. 5 and 6). In the example, units UNT0 to UNT3 corresponding to 4), a decoder 14311, and an AND gate 14312 are included.
The RCB 1431 (-0 to -3) is provided corresponding to the memory macros 12-1 to 12-n (n = 4 in this embodiment) of the memory systems 11-1 to 11-n. , Corresponding macro data (unit number (Unit-No) and address and command (ADDR / CMD)) Mac? Di (= 3, 2, 1, 0), macro effective signal Mac? ldi, the ready signal RDYi, and the command iCMD being executed are supplied.

The decoder 14311 receives the macro data Mac? In response to Di, the unit number is decoded and, for example, high level unit enable signals UE0 to UE3 are output to the corresponding unit UNT according to the decoding result.

The AND gate 14312 receives the macro valid signal Mac? The logical product of ldi and ready signal RDYi is obtained, and when both input signals are at high level, high level signal S14312 is output to each unit UNT0 to UNT3.

  Each unit UNT0-3 has a similar configuration, and includes an AND gate 14313, a command register (CMDreg) 14314, a step counter (STEPcount) 14315, a reference table (Reference Table) 14316, and a subtracter (Sub) 14317, respectively. It consists of

  The AND gate 14313 takes the logical product of the output signal S14312 of the AND gate 14312 and the unit enable signal UE (0-3) from the decoder 14311. When both signals are high, the high level enable signal SEN is output to the command register 14314 and the step. Output to the counter 14315.

The command register 14314 is enabled when the enable terminal EN receives the high level enable signal SEN from the AND gate 14313, and is supplied to the data terminal Data. The address and command information (ADDR / CMD) of Di are fetched and held, and the held data is output to the reference table 14316.

The step register 14315 is enabled by receiving a high level enable signal SEN from the AND gate 14313 at the load terminal LD, and is supplied with the macro data Mac? Di is captured and held, the number of steps of the command is counted, and the result is output to the subtracter 14317.

  The reference table 14316 receives the data held in the command register 14314 and the command iCMD being executed, and there is a clock difference between the next issued command and the command currently being executed. Scheduling whether to issue to the eye, and outputting the issue timing as a result to the subtracter 14316.

  The subtractor 14317 inputs the issue timing and the command iCMD according to the reference table 14316, takes the difference between the issue timing and the execution time of the command (and address) being executed, and outputs the result to the selector 1432 in FIG. To do.

  The selector 1432 of FIG. 5 selects the maximum value from the output values of the subtracters 14317 of the plurality (4 in this embodiment) of each RCB 1431 (−0 to −3) and outputs the selected value to the down counter 1433. .

  The down counter 1433 is controlled to the enable state by the state machine 1434. The output of the selector 1432 is loaded by the load signal to the load terminal ld, down-counts until it becomes zero, and when it becomes zero, the state S1433 is notified as such. 1434.

The state machine 1434 manages the state of the MAMU 143. When the state machine 1434 receives the signal S143 from the down counter 1433, the state machine 1434 receives the ready signal RDY of its own memory system 11. i (in the example of FIG. 5, the ready signal RDY of the memory system 11-1 0) and the FIFO read signal FIFO-RD is output to the command FIFO 141.

In the example of FIG. 5, the MAMU of the memory system 11-1 is assumed. In this case, the macro data Mac0 is read from the RCB1431-0. D, Macro valid signal Mac0 ld0 is output.

Here, an outline of operations in the MAMU 143 and RCB 1431 having the above-described configuration will be described with reference to FIGS. 7 and 8.
FIG. 7 is a flowchart for explaining the operation of the MAMU in this embodiment. FIG. 8 is a flowchart for explaining the operation of the RCB in this embodiment.

First, the MAMU 143 determines whether or not to input a command / address (iC / A) issued by the processor 13 (ST1).
In step ST, when the command / address (iC / A) issued by the processor 13 is input, the process proceeds to RCB 1431 (ST2).

In RCB 1431, first, in step ST21, it is determined whether or not there is a command / address (C / A) refresh.
If it is determined in step ST21 that there is a refresh, the command / address (C / A) is refreshed (ST22), the step counter 14315 is reset (ST23), and the process proceeds to step ST24.
If it is determined in step ST21 that there is no refresh, the process directly proceeds to step ST24 without performing steps ST22 and ST23.
In step ST24, the command / address (iC / A) issued by the processor 13 and the command / address being executed (refC / A) are loaded into the reference table 14316.
Then, the command / address (C / A) issuance timing is detected from the reference table 14316 (ST25).
Next, the subtractor 14317 takes the difference between the issue timing and the execution time of the command / address (refC / A) being executed (ST26). This process is a process for obtaining the access time of the memory macro 12. This access time is input to the selector 1432 (ST27).

The selector 1432 of the MAMU 143 selects the maximum counting time from the output of the RCB 1431 (ST3).
Then, the selected maximum access time is set in the down counter 1433 (ST4).
The down counter 1433 counts down until the count value becomes zero (0). When the count value becomes zero (ST5), the ready signal RDY of the own memory system 11 is displayed in the state machine 1434. The memory macro 12 is accessed by outputting i and outputting the FIFO read signal FIFO-RD to the command FIFO 141 (ST6).

  Next, a specific configuration and function of the memory interface 15 (-1 to -n) of the memory macro 12 (-1 to -n) will be described.

  FIG. 9 is a diagram showing a configuration example of a memory interface according to the present invention.

  9 includes a command / address selector (C / A SEL) 151, a data path timing generator (Data Path Timing Generator: DPTG) 152, a memory timing generator (Memory Timing Generator: MTG) 153, and a data path selector. (Data Path Selector: DPS) 154 is included.

  As shown in FIG. 9, the command / address selector 151 includes a command / address path selector (CAPS) 1511 and a command / address decoder (CAD) 1512.

  Based on the enable signal from the command address decoder 1512, the command / address path selector 1511 selects the memory interface 15 of the memory macro 12 of the memory system arranged adjacent to the processor 13, the right side, and / or the left side of the own memory system 11. It is determined in which direction the command and address transferred from is output and transferred to the memory interface 15 of the memory system arranged on the right or left side in the Y direction.

  The command / address decoder 1512 receives the command and address transferred from the memory interface 15 of the memory macro 12 of the memory system arranged adjacent to the processor 13 of the own memory system 11, the right side, and / or the left side. It is determined whether or not there is a path corresponding to the command and address in its own memory system 11, and the result is notified to the data path timing generator 152 and the memory timing generator 153.

  When the command / address decoder 1512 informs that there is a path corresponding to the input command and address, the data path timing generator 152 is arranged adjacent to the processor 13 of the own memory system 11 on the right or / and the left side. The data transferred from the memory interface 15 of the memory macro 12 of the selected memory system is transferred to the memory macro 12 of the own memory system, the processor 13, or the memory interface 15 of the memory macro 12 of the memory system 11 arranged on the left or right side. A path to be transferred to is selected, a signal S152 for controlling the timing of passing is generated, and the signal S152 is output to the data path selector 154.

  When the command / address decoder 1512 informs that there is a path corresponding to the input command and address, the memory timing generator 153 generates a signal S153 for controlling the timing of accessing the memory macro 12 of the own memory system 11 And supplied to the memory macro 12.

  The data path selector 154 receives the signal S152 from the data path timing generator 152 and transfers it from the processor 13 of the own memory system 11 and the memory interface 15 of the memory macro 12 of the memory system arranged adjacent to the right or the left side. The transferred data is selectively transferred to the memory macro 12 of the own memory system, the processor 13, or the memory interface 15 of the memory macro 12 of the memory system 11 arranged on the left or right side.

  FIG. 10 is a circuit diagram showing a specific configuration example of the data path selector in the present embodiment.

The data path selector 154 of FIG. 10 includes a first latch (LTC1) 1541, a second latch (LTC2) 1542, a third latch (LTC3) 1543, a fourth latch (LTC4) 1544, a first selector (SEL1) 1545, 2 selector (SEL2) 1546, third selector (SEL3) 1547, fourth selector (SEL4) 1548, write redundancy circuit 1549, write buffer (WR) 1550, read amplifier (Read Amplifier: RA) 1551, and A read redundancy circuit 1552 is provided.
The data path selector 154 shown in FIG. 10 is a 1-bit circuit. For example, 256 circuits are provided in the case of 256 bits.
In FIG. 10, the memory portion of the memory macro 12 is assumed to be a DRAM, and SA0 to SAm indicate sense amplifiers. BL indicates a bit line.

  In the data path selector 154, data and paths to be selected by the first to fourth selectors 1545 to 1548 are controlled by a control signal S 152 from the data path timing generator 152.

The first selector 1545 is issued by the processor 13 of the own memory system 11, and the global write data GWD via the memory control unit 14, the data LDTI transferred from the memory interface of the memory macro of the left memory system, and the right memory The data RDTI transferred from the memory interface of the memory macro of the system is supplied, and data according to the instruction of the control signal S152 is selected and output to the first latch 1541.
The write data latched in the first latch 1541 is supplied to the write buffer 1550 via the redundant circuit 1549, transferred to the sense amplifiers SA0 to SAm, and the data is written to the addressed memory cell.

The second selector 1546 is supplied with the data LDTI transferred from the memory macro memory interface of the left memory system and the data RDTI transferred from the memory macro memory interface of the right memory system. Any one of the data is selected and output to the second latch 1542.
The data LTDI or RTDI latched in the second latch 1542 is supplied to the third selector 1547 and the fourth selector 1548.

The third latch 1543 latches read data read from the memory unit of the memory macro 12 of the own memory system 11 and via the read amplifier 1551 and the redundant circuit 1552. The data latched by the third latch 1543 is supplied to the third selector 1547 and the fourth selector 1548.
The fourth latch 1544 is issued by the processor 13 of the own memory system 11 and latches the global write data GWD via the memory control unit 14. The data latched by the fourth latch 1544 is supplied to the third selector 1547.

  The third selector 1547 is the global write data GWD issued by the own memory system 11, the read data read from the memory unit of the own memory system, the data LDTI transferred from the memory interface of the memory macro of the left memory system, or the right side Select one of the data RDTI transferred from the memory macro memory interface of the memory system of the left memory system, the data LTDO to the memory macro memory interface of the left memory system, or the memory macro memory interface of the right memory system The data RTDO is selected and transferred to the left memory interface or the right memory interface.

  The fourth selector 1548 includes global read data GRD from a lower bank, which will be described later, read data read from the memory unit of its own memory system, data LDTI transferred from the memory interface of the memory macro of the left memory system, or One of the data RDTI transferred from the memory interface of the memory macro of the right memory system is selected and transferred to the processor 13 through the memory control unit 14 of the own memory system 11.

FIG. 11 is a diagram illustrating a connection example between memory macros including the memory interface 15 having the above configuration.
In the example of FIG. 11, the case where the memory timing generator 153 is arranged in the memory unit of the memory macro 12 is shown. Therefore, the memory interfaces 15-i and 15-i + 1 in FIG. 11 are not shown.

As described above, in this embodiment, the third selector 1547 is once latched by the third latch 1543 and the global write data GWD issued by the own memory system 11 once latched by the fourth latch 1544. Read data read from the memory unit of the own memory system, and data LDTI transferred from the memory interface of the memory macro of the left memory system once latched by the second latch 1542, or memory of the memory macro of the right memory system Select any of the data RDTI transferred from the interface, select as data LTDO to the memory interface of the memory macro of the left memory system, or data RTDO to the memory interface of the memory macro of the right memory system, Transferred to the side memory interface or the right memory interface, the.
The fourth selector 1548 also reads the read data read from the memory unit of the own memory system once latched by the third latch 1543 and the memory macro memory interface of the left memory system once latched by the second latch 1542. Data LDTI transferred from the memory interface or the data RDTI transferred from the memory interface of the memory macro of the right memory system is selected and transferred to the processor 13 through the memory control unit 14 of the own memory system 11.

  That is, in the data path selector 154 of the present embodiment, a latch (or also referred to as a register) is provided in the data transfer wiring. In FIG. 11, it is described as LTC160.

As described above, by providing a latch in the data transfer wiring, the following effects can be obtained.
For example, in the memory interface 15-i of the memory macro 12-i, the data LDTI transferred from the memory interface 15-i-1 of the left memory macro 12-i-1 is transferred to the memory interface of the right memory macro 12-i + 1. When the data RDTO is transferred to 15-i + 1, the latch 160 (second latch 1542 in the specific configuration of FIG. 10) holds the input data LDTI at the first clock, and the third selector at the second clock. The data is output as data RDTO through 1547.
That is, while outputting the data RDTO at the second clock, another operation such as holding the next data LDTI at the same second clock can be executed, thereby improving the throughput of data transfer. Can be planned.

As shown in FIG. 12, for example, a memory macro 12-i + 1 can be configured as a memory interface that does not use a signal without using a latch (register) 160.
According to this configuration, an unnecessary circuit can be deleted to reduce the circuit area.

As shown in FIG. 13, a repeater (RPT) 170 as a buffer for re-driving input data (supply data) can be provided instead of providing a latch 160 in the data transfer wiring of each memory interface. It is.
For example, in the memory interface 15-i of the memory macro 12-i, the data LDTI transferred from the memory interface 15-i-1 of the left memory macro 12-i-1 is transferred to the memory interface of the right memory macro 12-i + 1. When data is transferred to 15-i + 1 as data RDTO, the input data LDTI is redriven in the repeater 170, and the waveform is shaped. The data RDTO can be output as data RDTO having a sharp rise and fall slope.
Thus, by providing a repeater in the data transfer wiring, there is an advantage that a transfer band can be secured.

Further, as shown in FIG. 14, for example, a memory macro 12-i + 1 can be configured as a memory interface that does not use a repeater 170 and does not use a signal.
According to this configuration, an unnecessary circuit can be deleted to reduce the circuit area.

  Next, the operation of the shared memory device 10 having the configuration of FIG. 1 will be described.

  First, for example, a case where the processor 13-1 of the memory system 11-1 accesses a memory cell at a desired address of the memory macro 12-1 of the own system will be described.

In this case, the processor 13-1 issues a write or read command and an address to be accessed and outputs it to the memory control unit 14-1.
In the memory control unit 14-1, the command and address (CMD / ADR) for the memory macro 12-1 of the own memory system 11-1 issued by the processor 13-1 and its valid signal (valid signal) LD are issued. The input command is decoded, and an access timing at which no collision occurs is generated in the access to the memory macro 12 according to the write, read operation, etc. according to the command. Then, the command and address are controlled to be transferred to the memory macro 12-1 at the timing generated from the memory control unit 14-1, and the command and address are output to the memory interface 15-1 of the memory macro 12-1. .
In the memory control unit 14-1, even if the command is write or read, the write data issued by the processor 13-1, the memory macro 12-1, or the memory macro 12-1 is read. The passed read data is propagated to the memory macro 12-1 or the processor 13-1 in a form that basically passes.

In the memory interface 15-1, based on the command and address transferred from the memory control unit 14-1, it is determined whether or not the own memory system 11-1 has a path corresponding to the input command and address. . In this case, it is determined that there is a path in the own memory system 11-1.
In the memory interface 15-1, the write data issued by the processor 13-1 of the own memory system 11-1 is transferred to the memory unit of the memory macro 12-1 based on the determination result, and the desired address is stored. Data is written to the memory cell.
Alternatively, read data read from the memory macro 12-1 of the own memory system 11-1 is transferred to the processor 13-1 via the memory control unit 14-1.

  Next, for example, a case where the processor 13-1 of the memory system 11-1 accesses a memory cell at a desired address of the memory macro 12-2 of the memory system 11-2 adjacent on the right side will be described.

In this case, the processor 13-1 issues a write or read command and an address to be accessed and outputs it to the memory control unit 14-1.
Since the memory control unit 14-1 is not a command and an address for the memory macro 12-1 of its own memory system 11-1, the command and address issued by the processor 13-1 are the same as those of the adjacent memory system 11-2. It is transferred to the memory control unit 14-2.

  In the memory control unit 14-2, based on the command and address (CMD / ADR) and its valid signal (valid signal) LD for the memory macro 12-2 of the own memory system 11-2 issued by the processor 13-1. The input command is decoded, and an access timing at which no collision occurs is generated in the access to the memory macro 12 according to the write, read operation, etc. according to the command. Then, the command and address are controlled to be transferred to the memory macro 12-2 with the timing generated from the memory control unit 14-2, and the command and address are output to the memory interface 15-2 of the memory macro 12-2. .

  In the memory control unit 14-1, even if the command is write or read, the write data issued by the processor 13-1 or read from the memory macro 12-2 and passed through the memory macro 12-1. The read data is propagated to the memory macro 12-1 or the processor 13-1 in a form that basically passes.

In the memory interface 15-1, whether or not the own memory system 11-1 has a path corresponding to the input command and address is determined based on the command and address transferred from the memory control unit 14-1. . In this case, it is determined that there is no path in the own memory system 11-1.
As a result, in the memory interface 15-1, the write data issued by the processor 13-1 of the own memory system 11-1 is stored in the memory macro 12-2 of the right memory system 11-2 based on the determination result. It is transferred to the interface 15-2.
Alternatively, the read data read from the memory macro 12-2 of the adjacent memory system 11-2 and transferred from the memory interface 15-2 is transferred to the processor 13-1 via the memory control unit 14-1. .

In the memory interface 15-2, based on the command and address transferred from the memory control unit 14-2, it is determined whether or not a path corresponding to the input command and address exists in the own memory system 11-2. . In this case, it is determined that the own memory system 11-2 has a path.
In the memory interface 15-2, the write data issued by the processor 13-1 of the adjacent memory system 11-1 and input to the memory interface 15-2 through the memory interface 15-1 based on the determination result. Is transferred to the memory portion of the memory macro 12-2, and data is written to the memory cell at a desired address.
Alternatively, the read data read from the memory macro 12-2 of the memory system 11-2 is transferred to the memory interface 15-1 of the adjacent memory system 11-1 via the memory interface 15-2, and the memory control unit 14- 1 to the processor 13-1.

  As described above, according to the first embodiment, each of the memory systems 11-1 to 11-n accesses the memory macro 12, such as DRAM or SRAM, which stores data, and the memory macro 12. Information (data and commands and addresses) between the processor 13 that performs predetermined data processing and the processor 12 of the own stage and the memory macro 11 and information with a memory control unit of a different memory system ( The memory macro 12 includes a memory interface 15 capable of transferring data, and includes memories of different memory systems (adjacent memory systems in the present embodiment). Macro memory interfaces are connected to each other Since it was, wiring to the memory can be simplified, it is possible to prevent performance degradation due to area increase and long-distance wires can improve the extensibility of scalability of the system.

  Further, in the multiprocessor system as in the first embodiment, in order to ensure expandability, a memory system optimized for the processor is incorporated in a pair so that the application needs. The optimum number of processors for processing capacity can be installed. Alternatively, as the number of processors that can be mounted increases due to the evolution of semiconductor processes, it becomes possible to expect an improvement in processing capability without changing the architecture. At this time, it is desirable to adopt a memory system hierarchical structure in order to reduce the time for accessing the memory system.

Further, according to the first embodiment, when data to be accessed is written to the memory macros of one or a plurality of different memory systems, write broadcasting is performed through the data lines between the memory macros, thereby obtaining the following effects. Is also possible.
That is, in a multi-processor system, when data in a general memory system is referred to by a plurality of processors, the same data must be accessed many times using the system bus.
On the other hand, in the first embodiment, the memory system can copy data to a plurality of memory macros by write broadcast through the data lines between the memory macros. This allows the processor to access data to the nearest local macro. As a result, useless data transfer can be reduced, the load on the system bus can be reduced, and the processing performance is improved.

  In the shared memory device 10 according to the first embodiment, the memory interfaces 15-1 to 15-n of the memory macros 12-1 to 12-n have the same height (width) h4 in the Y direction. Aligned in the Y direction and arranged in parallel in the X direction (straight line in the horizontal direction) eliminates unnecessary routing of the wiring connecting the memory macros, and wiring at the shortest distance Can be laid out.

In the first embodiment, the memory macros 12-1 to 12-n of the memory systems 11-1 to 11-n are arranged with the height h1 in the Y direction from the reference line BSL aligned, that is, The memory macros 12-1 to 12-n of the memory systems 11-1 to 11-n employ a configuration in which two-dimensional heights are aligned and arranged in parallel in the X direction (horizontal direction). For example, a configuration as shown in FIG. 15 can also be adopted.
Specifically, in each of the memory macros 12-1 to 12-n (n = 4 in the example of FIG. 15), the first area AR1 including the memory cell array and the memory interface related to the connection wiring is the reference line as described above. Arranged so that the two-dimensional heights in the Y direction (vertical direction) from the BSL are aligned, and has a special processing area AR2 such as sorting as in the memory macros 12-3 and 12-4 in FIG. The second area AR2 excluding the area AR1 can be configured to be different between the memory macros.

  In the example of FIG. 15, the memory cell arrays of the memory macros 12-1 and 12-2 and the memory macros 12-3 and 12-4 share a row decoder. Therefore, the memory cell array of the memory macro sharing the row decoder is arranged with a two-dimensional height in the Y direction.

  In this case, the area AR1 including the memory cell array and the memory interface related to the connection wiring is arranged so that the two-dimensional height in the Y direction (vertical direction) from the reference line BSL is aligned as described above. Further, it is possible to lay out the wiring at the shortest distance by eliminating unnecessary routing of the wiring connecting the memory macros.

  In this case, as shown in FIG. 16, the structure is illustrated as having a space between each memory macro, but a space is provided, no space is provided, or a logic is provided on a connection line of the memory interface 15. Various modes such as providing a circuit are possible.

Second Embodiment
FIG. 17 is a system configuration diagram of the shared memory device according to the second embodiment of the present invention.
FIG. 18 is a diagram showing a connection example between memory macros provided with the memory interface according to the present invention in the second embodiment.

  The second embodiment is different from the first embodiment described above in that each of the memory macros 12A-1 to 12A-n includes a plurality of ports PT that can transfer data with different memory macros.

  In this case, the memory interface 15 is arranged corresponding to each port, and its basic configuration is the same as the configuration described in association with FIG. 9 and FIG. Therefore, the detailed description is abbreviate | omitted.

  In the second embodiment, the case where the memory timing generator 153 is arranged in the memory unit of the memory macro 12A is shown. Therefore, it is not shown in each memory interface 15 of FIG.

Also in the shared memory device 10A according to the second embodiment, the memory interfaces 15-11 to 15-n1 and 15-1m to 15-nm of the memory macros 12-1 to 12-n have the height in the Y direction ( Width) and the arrangement positions in the Y direction are aligned and arranged in parallel in a straight line in the X direction (straight line in the horizontal direction).
Accordingly, it is possible to eliminate the unnecessary routing of the wirings connecting the memory macros and to layout the wirings with the shortest distance.

  Other configurations are the same as those of the first embodiment, and according to the second embodiment, the same effects as those of the first embodiment described above can be obtained.

<Third Embodiment>
FIG. 19 is a system configuration diagram of a shared memory device according to the third embodiment of the present invention.
FIG. 20 is a diagram showing a connection example between memory macros provided with the memory interface according to the present invention in the third embodiment.

  The third embodiment is different from the first embodiment described above in that each of the memory macros 12A-1 to 12A-n has a plurality of banks BNK1 to BNKm, and data transfer with corresponding banks of different memory macros is performed. It is possible to configure.

  In this case, the memory interface 15 is arranged for each of the banks BNK1 to BNKm, and the basic configuration is the same as the configuration described in association with FIGS. Therefore, the detailed description is abbreviate | omitted.

  In the third embodiment, a data path timing generator 152 and a memory timing generator 153 are arranged for each memory interface of each bank.

Also in the shared memory device 10b of the third embodiment, the banks BNK1 to BNKm including the memory interface portions of the memory macros 12-1 to 12-n have the same height (width) in the Y direction. , The arrangement positions in the Y direction are aligned and arranged in parallel in a straight line in the X direction (a straight line in the horizontal direction).
Accordingly, it is possible to eliminate the unnecessary routing of the wirings connecting the memory macros and to layout the wirings with the shortest distance.

  Other configurations are the same as those of the first embodiment, and according to the third embodiment, the same effects as those of the first embodiment described above can be obtained.

<Fourth embodiment>
FIG. 21 is a system configuration diagram of a shared memory device according to the fourth embodiment of the present invention.

  The fourth embodiment differs from the first embodiment described above in that the port of the memory interface that was not used by the memory macro, specifically, the memory macro of the memory system 11-1 in the first embodiment. The left input / output unit (port) of the memory interface 15-1 arranged in 12-1, and the right input / output unit of the memory interface 15-n arranged in the memory macro 12-n of the memory system 11-n (Port) is used as an interface with the external memories 20 and 21.

Other configurations are the same as those of the first embodiment, and according to the fourth embodiment, the following effects can be obtained as well as the same effects as the effects of the first embodiment described above can be obtained. Can do.
Generally, since the system bus is used for data transfer of the external memory, the peak performance is likely to become a bus neck.
On the other hand, according to the fourth embodiment, it is possible to reduce the load on the system bus, and as a result, there is an advantage that the processing capability increases.

<Fifth Embodiment>
FIG. 22 is a system configuration diagram of the shared memory device according to the fifth embodiment of the present invention.

  The fifth embodiment is different from the second embodiment described above in that the memory interface port not used by the memory macro, specifically, the memory macro of the memory system 11-1 in the second embodiment. The input / output unit (port) on the left side of the memory interface 15 arranged in each port of 12A-1 and the input on the right side of the memory interface 15 arranged in each port of the memory macro 12A-n of the memory system 11-n The output unit (port) is used as an interface with the external memories 20A and 21A.

Other configurations are the same as those of the second embodiment. According to the fifth embodiment, the following effects can be obtained as well as the same effects as those of the first and second embodiments described above. Obtainable.
Generally, since the system bus is used for data transfer of the external memory, the peak performance is likely to become a bus neck.
On the other hand, according to the fifth embodiment, it is possible to reduce the load on the system bus, and as a result, there is an advantage that the processing capability increases.

<Sixth Embodiment>
FIG. 23 is a system configuration diagram of the shared memory device according to the sixth embodiment of the present invention.

  The sixth embodiment differs from the third embodiment described above in that the port of the memory interface that was not used by the memory macro, specifically, the memory macro of the memory system 11-1 in the third embodiment. The left input / output unit (port) of the memory interface 15 arranged in each of the banks BNK1 to BNLm of 12A-1 and the banks BNK1 to BNLm of the memory macro 12A-n of the memory system 11-n. The right input / output unit (port) of the memory interface 15 is used as an interface with the external memories 20B and 21B.

Other configurations are the same as those of the third embodiment. According to the sixth embodiment, the following effects can be obtained as well as the same effects as those of the first and third embodiments described above can be obtained. Obtainable.
Generally, since the system bus is used for data transfer of the external memory, the peak performance is likely to become a bus neck.
On the other hand, according to the sixth embodiment, it is possible to reduce the load on the system bus, and as a result, there is an advantage that the processing capability increases.

<Seventh embodiment>
FIG. 24 is a system configuration diagram of the shared memory device according to the seventh embodiment of the present invention.

  In the first to sixth embodiments described above, one memory macro is arranged in each memory system. However, in the shared memory device 10F of the seventh embodiment, In each memory system 11F-1 to 11F-n (n = 4 in the example of FIG. 24), a memory macro having a similar configuration is m in the Y direction in the two-dimensional orthogonal coordinate system set in FIG. In this case, m = 4) are arranged in order with the same width.

Specifically, in the memory system 11F-1, memory macros (MM) 12-11, 12-12, 12-13, and 12-14 are arranged in a line.
In the memory system 11F-2, memory macros (MM) 12-21, 12-22, 12-23, and 12-24 are arranged in a line.
In the memory system 11F-3, memory macros (MM) 12-31, 12-32, 12-33, and 12-34 are arranged in a line.
In the memory system 11F-4, memory macros (MM) 12-41, 12-42, 12-43, and 12-44 are arranged in a line.
Therefore, in the shared memory device 10F of the seventh embodiment, memory macros are arranged in a matrix of m × n (4 × 4 in the example of FIG. 24).

In the matrix arrangement of memory macros, a first macro group MGRP1 is formed by the memory macros 12-11, 12-21, 12-31, and 12-41 arranged in the first row.
Similarly, the second macro group MGRP2 is formed by the memory macros 12-12, 12-22, 12-32, and 12-42 arranged in the second row.
A third macro group MGRP3 is formed by the memory macros 12-13, 12-23, 12-33, and 12-43 arranged in the third row.
A fourth macro group MGRP4 is formed by the memory macros 12-14, 12-24, 12-34, and 12-44 arranged in the fourth row.

In the shared memory device 10F according to the seventh embodiment, in each of the first to fourth macro groups MGRP1 to MGRP4, the memory macros 12-11 to 12-41 of the memory systems 11F-1 to 11F-4. , 12-12 to 12-42, 12-13 to 12-43, 12-14 to 12-44 are arranged with the same height h1 in the Y direction from the reference line BSL, that is, each memory system 11F-1 The memory macros of ˜11F-n are arranged in parallel in the X direction (horizontal direction) with the same two-dimensional height.
More preferably, in each of the first to fourth macro groups MGRP1 to MGRP4, the memory interfaces (15) of the memory macros have the same height (width) in the Y direction and the same arrangement position in the Y direction. Are arranged in parallel in a straight line in the X direction (a straight line in the horizontal direction).
Therefore, in each macro group, it is possible to eliminate the unnecessary routing of the wirings connecting the memory macros and to layout the wirings with the shortest distance.

In this case, in each of the macro groups MGRP1 to MGRP4, a configuration is illustrated in which a space is provided between the memory macros. However, a space is provided, a space is not provided, or logic is connected to the connection line of the memory interface Various modes such as providing a circuit are possible.
In addition, although a configuration in which a space is provided between each of the macro groups MGRP1 to MGRP4 is illustrated, various modes such as providing a space, not providing a space, or providing a logic circuit are possible.

  In each of the memory systems 11F-1 to 11F-4 (n), the memory interface of each memory macro, the upper memory control unit 14F (-1 to -4), and the processor 13F (-1 to 1) as a processing unit. -4) can be connected, for example, as shown in FIG.

In the connection example of FIG. 25, in each of the memory systems 11F-1 to 11F-4, individual connection wirings CNL11 to CNL14, CNL21 to CNL24, CNL31 to CNL34, and CNL41 to CNL44 are formed for each memory macro.
If this connection example is adopted, each memory macro and the upper processor 13 can be freely accessed.

In the connection example of FIG. 26, in each of the memory systems 11F-1 to 11F-4, the wiring between the upper side and each memory macro is formed as a shared wiring CML. By adopting this connection example, the number of wirings can be reduced. The surface area of the wiring area can be reduced.

  Other configurations are the same as those of the first embodiment, and according to the seventh embodiment, the same effects as those of the first embodiment described above can be obtained.

<Eighth Embodiment>
FIG. 27 is a system configuration diagram of the shared memory device according to the eighth embodiment of the present invention.

  The shared memory device 10G of the eighth embodiment is different from the shared memory device 10F of the seventh embodiment in that the following configurations are adopted in the second to fourth macro groups MGRP2G to MGRP4G.

In the seventh embodiment described above, in each macro group MGRP1 to MGP4, the heights of the memory macros in the Y direction are aligned, that is, the memory macros of each macro group MGRP1 to MGP4 have a two-dimensional height. Are arranged in parallel in the X direction (horizontal direction).
On the other hand, in the eighth embodiment, the first area AR1 including the memory cell array and the memory interface related to the connection wiring of each memory macro of the second to fourth macro groups MGRP2G to MGRP4G is in the Y direction. The second area AR2 excluding the area AR1 is arranged so as to be different between the memory macros, for example, having a special processing area AR2 such as sorting, etc. Yes.

  In this case, the area AR1 including the memory cell array and the memory interface related to the connection wiring is arranged so that two-dimensional heights in the Y direction (vertical direction) are aligned. Therefore, the wiring can be laid out with the shortest distance.

In this case, in each of the macro groups MGRP1G to MGRP4G, the configuration is illustrated in which a space is provided between the memory macros. However, a space is provided, no space is provided, or logic is connected to the connection line of the memory interface. Various modes such as providing a circuit are possible.
In addition, although a configuration is illustrated in which a space is provided between the macro groups MGRP1G to MGRP4G, various modes are possible such as providing a space, no space, or providing a logic circuit.

  Other configurations are the same as those of the seventh embodiment, and according to the eighth embodiment, the same effects as those of the first and seventh embodiments described above can be obtained.

  In each of the above embodiments, the example in which the memory control unit is arranged between the processor and the memory macro has been described. However, a mode in which the function of the memory control unit is provided in the memory interface of each memory macro is also possible.

1 is a diagram illustrating a general architecture of a multiprocessor. It is a figure which shows the architecture using a crossbar. 1 is a system configuration diagram of a shared memory device according to a first embodiment of the present invention. It is a block diagram which shows an example of the memory control unit which concerns on this embodiment. It is a figure which shows the structural example of the memory access management unit (MAMU) in the memory control unit which concerns on this embodiment. It is a figure which shows the structural example of the ready check block (RCB) in FIG. It is a flowchart for demonstrating operation | movement of MAMU in this embodiment. It is a flowchart for demonstrating operation | movement of RCB in this embodiment. It is a figure which shows the structural example of the memory interface which concerns on this invention. It is a circuit diagram which shows the specific structural example of the data path selector in this embodiment. 6 is a diagram illustrating an example of connection between memory macros including a memory interface including a latch in a data selector in the first embodiment. FIG. FIG. 5 is a diagram illustrating a connection example between memory macros including a memory interface including a data path selector provided with a latch and a data path selector provided with no latch. FIG. 3 is a diagram illustrating an example of connection between memory macros including a memory interface including a repeater in a data selector in the first embodiment. It is a figure which shows the example of a connection between the memory macros provided with the memory interface including the data path selector which provided the repeater, and the data path selector which did not provide the repeater. 2 is a diagram showing an example of a memory macro array in which a region including a memory interface and a memory cell array has a two-dimensional height and other regions have different heights, and an arrangement example between memory macros will be described. FIG. It is a figure which shows the example of the memory macroarray from which the area | region containing a memory interface and a memory cell array has equal two-dimensional height, and other areas differ in height. FIG. 5 is a system configuration diagram of a shared memory device according to a second embodiment of the present invention. FIG. 10 is a diagram illustrating a connection example between memory macros including a memory interface in the second embodiment. FIG. 6 is a system configuration diagram of a shared memory device according to a third embodiment of the present invention. FIG. 10 is a diagram illustrating an example of connection between memory macros including a memory interface in the third embodiment. FIG. 9 is a system configuration diagram of a shared memory device according to a fourth embodiment of the present invention. FIG. 9 is a system configuration diagram of a shared memory device according to a fifth embodiment of the present invention. FIG. 10 is a system configuration diagram of a shared memory device according to a sixth embodiment of the present invention. FIG. 10 is a system configuration diagram of a shared memory device according to a seventh embodiment of the present invention. It is a figure which shows the 1st example of the connection wiring of a high-order apparatus and each memory macro at the time of providing a several memory macro in each memory system. It is a figure which shows the 2nd example of the connection wiring of a high-order apparatus and each memory macro at the time of providing a several memory macro in each memory system. FIG. 10 is a system configuration diagram of a shared memory device according to an eighth embodiment of the present invention.

Explanation of symbols

  10, 10A to 10G ... shared memory devices, 11-1 to 11-n, 11A-1 to 11A-n, 11B-1 to 11B-n, 11F-1 to 11F-n, 11G-1 to 11G-n ... Memory system, 12-1 to 12-n, 12A-1 to 12A-n, 12B-1 to 12B-n, 12-11 to 12-14, 12-21 to 12-24, 12-31 to 12-34 , 12-41 to 12-44 ... memory macro, 13-1 to 13-n ... processor, 14-1 to 14-n ... memory control unit, 15-1 to 15-n ... memory interface, 20, 20A, 20B ... external memory.

Claims (16)

A plurality of memory systems including a processing device and at least one memory macro accessible by at least the processing device;
The memory macro of each memory system has at least one memory interface capable of transferring data, and at least a region including the memory cell and the memory interface is arranged in parallel with a two-dimensional height,
A shared memory device in which memory interfaces of memory macros with different two-dimensional heights of different memory systems are connected. The shared memory device according to claim 1, wherein at least one of a plurality of memory interfaces of different memory systems that are connected has a latch in a data transfer wiring. The shared memory device according to claim 1, wherein at least one of a plurality of memory interfaces of different memory systems having a connection relationship includes a repeater capable of re-driving data transferred to the data transfer wiring. The shared memory device according to claim 1, wherein the plurality of memory macros arranged in parallel in each of the memory systems are arranged with the same two-dimensional height for all regions. The at least one of the plurality of memory macros arranged in parallel in each of the memory systems includes a second area other than the first area having a two-dimensional height including a memory cell and a memory interface. Shared memory device. In each of the above memory systems, a plurality of memory macros are arranged in a row, and a plurality of memory macros of each memory system are arranged in a matrix,
Among the memory macros arranged in a matrix, a macro group is formed by a plurality of memory macros arranged in the same row,
In each of the macro groups, at least a region including the memory cell and the memory interface is arranged in parallel with a two-dimensional height,
The shared memory device according to claim 1, wherein memory interfaces of memory macros having different two-dimensional heights are connected to each other. The shared memory device according to claim 6, wherein in each of the memory systems, the plurality of memory macros are connected to the processing device by individual wirings. The shared memory device according to claim 6, wherein in each of the memory systems, the plurality of memory macros are connected to the processing device by a shared wiring. The shared memory device according to claim 6, wherein in at least one of the macro groups, a plurality of memory macros are arranged with a two-dimensional height aligned for all regions. 7. In at least one of the macro groups, at least one of the plurality of memory macros includes a second region other than the first region having a two-dimensional height and including a memory cell and a memory interface. Shared memory device. A plurality of memory systems including a processing device, at least one memory macro accessible by the processing device, and a memory control unit that controls access to the memory macro;
The memory control unit of each of the above memory systems exchanges information between the processor and the memory macro, and also exchanges information with the memory control unit of a different memory system,
The memory macro of each memory system has at least one memory interface capable of transferring data, and at least a region including the memory cell and the memory interface is arranged in parallel with a two-dimensional height,
A shared memory device in which memory interfaces of memory macros with different two-dimensional heights of different memory systems are connected. The shared memory device according to claim 11, wherein at least one of a plurality of memory interfaces of different memory systems having a connection relationship has a latch in a data transfer wiring. The shared memory device according to claim 11, wherein at least one of the plurality of memory interfaces of different memory systems that are connected has a repeater that can redrive the data transferred to the data transfer wiring. In each of the above memory systems, a plurality of memory macros are arranged in a row, and a plurality of memory macros of each memory system are arranged in a matrix,
Among the memory macros arranged in a matrix, a macro group is formed by a plurality of memory macros arranged in the same row,
In each of the macro groups, at least a region including the memory cell and the memory interface is arranged in parallel with a two-dimensional height,
The shared memory device according to claim 11, wherein memory interfaces of memory macros having different two-dimensional heights of different memory systems are connected to each other. The shared memory device according to claim 14, wherein in each of the memory systems, the plurality of memory macros are connected to the processing device by individual wires. The shared memory device according to claim 14, wherein in each of the memory systems, the plurality of memory macros are connected to the processing device by a shared wiring.

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