JP2007052856A - Semiconductor device and its sense amplifier operating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sense amplifier operating method as to a semiconductor device equipped with the sense amplifier, which forms a different amplification voltage level by specially changing over a power source voltage to be supplied to the sense amplifier, and to provide the semiconductor device equipped with such sense amplifier. <P>SOLUTION: A power source voltage changeover circuit for changing over the power supply voltage supplied to the sense amplifier is provided to supply a first voltage level for amplifying the information of a memory cell as the power source voltage of the sense amplifier and a second voltage level which has a voltage amplitude larger than that of the first voltage level, becoming a writing voltage to the memory cell before a precharge operation. Deterioration of a device performance due to a high voltage can be prevented since occurrence of noise at the amplification is reduced by supplying the power source voltage in two steps and also an impressed period at the second voltage level becomes short. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a sense amplifier, and more particularly to a method of operating a sense amplifier having different amplification voltage levels by switching a power supply voltage supplied to the sense amplifier, and a semiconductor device including the sense amplifier.

  Recent semiconductor devices are increasingly required to have higher integration and higher speed. For this reason, the semiconductor process is miniaturized and the operating voltage of these semiconductor devices is also lowered. Even in a dynamic random memory (hereinafter referred to as DRAM), the operating voltage has been reduced with the miniaturization of the process.

  A decrease in the operating voltage in the DRAM, particularly a decrease in the operating voltage of the sense amplifier circuit, decreases the amount of charge written into the memory cell, making it difficult to ensure the refresh characteristics and the operating margin of the memory cell. A conventional sense amplifier circuit is shown in FIG. FIG. 5 shows a bit line pair, a sense amplifier circuit, and a precharge circuit.

  The sense amplifier circuit includes a flip-flop circuit composed of a first inverter circuit composed of transistors Q1 and Q3, a second inverter circuit composed of transistors Q2 and Q4, a transistor Q14 for supplying a high voltage VH to the flip-flop circuit, and The transistor Q15 supplies the low voltage VL. The first inverter circuit inputs the bit line BLB and outputs the bit line BLT. The second inverter circuit inputs the bit line BLT and outputs the bit line BLB. A high voltage VH and a low voltage VL are supplied to the flip-flop circuit by a sense amplifier activation signal (SA is high level and SAB is low level). A minute signal of the memory cell of the bit line pair (BLT, BLB) is amplified to the high voltage VH and low voltage VL levels.

  The precharge circuit includes transistors Q5, Q6 and Q7. The precharge signal PRE turns on the transistor 5 to balance the bit line pairs at the same potential. Further, the transistors Q6 and Q7 are turned on to balance the bit line pair with the reference voltage VREF.

  In such a conventional sense amplifier circuit operation shown in FIG. 5, there is a problem that noise due to abrupt voltage amplification occurs when the sense amplifier amplification level is increased. Furthermore, it has been found that with the recent miniaturization of semiconductor processes, a high voltage is applied during the sense amplifier active time, which causes a new problem of causing deterioration of MOS device characteristics. The inventor of the present application has found the problem that the characteristics of the miniaturized device deteriorate due to the long application time of the high voltage, and has reached the present invention.

  There are the following prior documents for the problem that noise is generated due to abrupt voltage amplification in the operation of the sense amplifier circuit of the conventional system. In Patent Document 1 (Japanese Patent Laid-Open No. 10-334681), in a nonvolatile semiconductor memory device, a sense amplifier is activated by a two-stage method in which the sense amplifier is activated with a low current driving capability at an early stage of activation and then with a high current driving capability. In this way, noise generation due to rapid voltage amplification of the sense amplifier is prevented. Patent Document 2 (Japanese Patent Laid-Open No. 2001-126484) discloses a technique for controlling overdrive by amplifying at a high voltage at the initial stage of activation of the sense amplifier and operating at a low voltage before the completion of amplification of the sense amplifier. Yes.

  In these documents, generation of noise and excessive overdrive voltage are prevented by controlling the amplification capability when the sense amplifier amplifies the information in the memory cell. However, since a high voltage is applied during the active period of the sense amplifier, there is no recognition of new problems that cause deterioration of MOS device characteristics, and these problems are not described.

Japanese Patent Laid-Open No. 10-334682 JP 2001-126484 A

  As described above, since the operating voltage of the semiconductor device is lowered and the amount of charge stored in the memory cell is reduced, the voltage level written to the memory cell is preferably as high as possible. However, when the voltage level written in the memory cell is set to a high voltage, the high voltage is applied during the sense amplifier activation time, which causes a problem of deteriorating the device characteristics of the MOS.

  In view of the above problems, an object of the present invention is to provide a highly reliable sense amplifier operation method and a semiconductor device including the sense amplifier. In the operation method of the sense amplifier of the present application, the power supply voltage for driving the sense amplifier has two stages. A first voltage level for amplifying the information in the memory cell as a power supply voltage for the sense amplifier and a second voltage level to be a write voltage to the memory cell before the precharge operation are supplied. Since the period during which the second voltage level, which is a high voltage, is applied is shortened, deterioration of device characteristics due to the high voltage can be prevented. With this configuration, a highly reliable sense amplifier operation method and a semiconductor device including the sense amplifier can be provided.

  In order to solve the above-described problems, the present invention basically employs the techniques described below. Needless to say, application techniques that can be variously changed without departing from the technical scope of the present invention are also included in the present application.

  In the sense amplifier operating method of the present invention, the voltage level to be amplified by the sense amplifier is set to two stages, the data is first read from the memory cell by amplification of the first voltage level, and then the voltage amplitude is higher than that of the first voltage level. Writing to the memory cell is performed by amplification of a large second voltage level.

  In the sense amplifier operation method of the present invention, the amplification of the first voltage level is performed by a sense amplifier activation signal.

  The amplification of the second voltage level in the sense amplifier operation method of the present invention is performed before a precharge operation by input of a precharge signal.

  A semiconductor device of the present invention includes a flip-flop that is connected between a high potential node and a low potential node and amplifies data of a bit line pair, and a high voltage power supply switching control circuit that is connected to the high potential node. The sense amplifier has two voltage levels to be amplified, first reads data from the memory cell by amplification of the first voltage level, and then by amplification of the second voltage level having a larger voltage amplitude than the first voltage level. Writing to the memory cell is performed.

  The amplification of the first voltage level in the semiconductor device of the present invention is performed by a sense amplifier activation signal.

  The amplification of the second voltage level in the semiconductor device of the present invention is performed before a precharge operation by inputting a precharge signal.

  The sense amplifier in the semiconductor device of the present invention further includes a low voltage power supply switching control circuit connected to the low potential node.

  A semiconductor device of the present invention includes a flip-flop that is connected between a high potential node and a low potential node and amplifies data of a bit line pair, and a low voltage power supply switching control circuit that is connected to the low potential node. The sense amplifier has two voltage levels to be amplified, first reads data from the memory cell by amplification of the first voltage level, and then by amplification of the second voltage level having a larger voltage amplitude than the first voltage level. Writing to the memory cell is performed.

  The amplification of the first voltage level in the semiconductor device of the present invention is performed by a sense amplifier activation signal.

  The amplification of the second voltage level in the semiconductor device of the present invention is performed before a precharge operation by inputting a precharge signal.

  In the operation method of the sense amplifier of the present application, the power supply voltage for driving the sense amplifier has two stages. A first voltage level for amplifying the information in the memory cell as a power supply voltage for the sense amplifier and a second voltage level to be a write voltage to the memory cell before the precharge operation are supplied. Since the period during which the second voltage level having a larger voltage amplitude than the first voltage level is applied is shortened, an effect of preventing deterioration of device characteristics due to a high voltage can be obtained.

  A semiconductor device of the present invention will be described with reference to the drawings.

  A first embodiment will be described with reference to FIGS. FIG. 1 is a circuit diagram of the sense amplifier section, and FIG. 2 is a timing chart thereof. The sense amplifier circuit shown in FIG. 1 includes a bit line pair, a sense amplifier circuit, and a precharge circuit. The sense amplifier circuit includes a flip-flop unit, a high voltage power supply unit, and a low voltage power supply unit.

  The flip-flop unit includes a first inverter circuit composed of transistors Q1 and Q3 and a second inverter circuit composed of transistors Q2 and Q4 between a high potential node VP and a low potential node VN. The first inverter circuit inputs the bit line BLB and outputs the bit line BLT. The second inverter circuit inputs the bit line BLT and outputs the bit line BLB.

  The high voltage power supply unit includes transistors Q8 / Q9 for supplying high voltage VH1 / VH2 to the high potential node VP of the flip-flop and the high voltage power supply switching circuit 1. The high voltage power supply switching circuit 1 receives the sense amplifier activation signal SA and the zero precharge signal PRE0, and connects the first high voltage switching signal SAP1 and the high voltage VH2 that connect the high voltage VH1 to the high potential node VP. The second high voltage switching signal SAP2 is output. When the first high voltage switching signal SAP1 is activated, the transistor Q8 is turned on, and the high voltage VH1 is supplied to the high potential node VP. When the second high voltage switching signal SAP2 is activated, the transistor Q9 is turned on, and the high voltage VH2 is supplied to the high potential node VP. Here, the high voltage VH2 is higher than the high voltage VH1.

  The low voltage power supply unit includes transistors Q10 / Q11 for supplying the low voltage VL1 / VL2 to the low potential node VN of the flip-flop, and the low voltage power supply switching circuit 2. The low voltage power supply switching circuit 2 receives the sense amplifier activation signal SA and the zero precharge signal PRE0, and connects the first low voltage switching signal SAN1 and the low voltage VL2 that connect the low voltage VL1 to the low potential node VN. The second low voltage switching signal SAN2 is output. When the first low voltage switching signal SAN1 is activated, the transistor Q10 is turned on, and the low voltage VL1 is supplied to the low potential node VN. When the second low voltage switching signal SAN2 is activated, the transistor Q11 is turned on, and the low voltage VL2 is supplied to the low potential node VN. Here, the low voltage VL2 is a voltage lower than the low voltage VL1.

  The precharge circuit includes transistors Q5, Q6, Q7 and a precharge control circuit 3. The precharge control circuit 3 receives the precharge signal PRE and outputs a first precharge signal PRE1 and a zero precharge signal PRE0. The zero precharge signal PRE0 is input to the high voltage power supply switching circuit 1 and the low voltage power supply switching circuit 2 to control power supply to the flip-flop. The first precharge signal PRE1 is output to the gates of the transistors Q5, Q6, Q7 that precharge the bit line.

  The transistor Q5 is connected between the bit line pair (BLT, BLB), and the first precharge signal PRE1 is input to the gate thereof. The transistor Q6 is connected between the bit line BLT and the reference voltage VREF, and the first precharge signal PRE1 is input to its gate. The transistor Q7 is connected between the bit line BLB and the reference voltage VREF, and the first precharge signal PRE1 is input to its gate. The first precharge signal PRE1 turns on the transistor Q5 to balance the bit line pair (BLT, BLB) at the same potential, and further turns on the transistors Q6, Q7 to charge the bit line pair to the reference voltage VREF. Balance.

  Next, the operation of the sense amplifier unit will be described with reference to the timing chart of FIG. A word line of a selected memory cell (not shown) is activated, and a sense amplifier activation signal SA for activating the sense amplifier is activated at time T0. In response to the sense amplifier activation signal SA, the high voltage power supply switching control circuit 1 outputs the first high voltage switching signal SAP1, and the low voltage power supply switching control circuit 2 outputs the first low voltage switching signal SAN1. The transistor Q8 is turned on by the first high voltage switching signal SAP1, and the high voltage VH1 is supplied to the high potential node VP of the flip-flop. The transistor Q10 is turned on by the first low voltage switching signal SAN1, and the low voltage VL1 is supplied to the low potential node VN of the flip-flop. As a result, the bit line pair (BLT, BLB) is amplified to the first voltage level of VH1 and VL1. Thus, the first amplification by the sense amplifier is performed by the sense amplifier activation signal SA. The information in the memory cell is amplified to this first voltage level and output to the data amplifier circuit.

  When the precharge signal PRE that activates the precharge is activated at time T1, the zero precharge signal PRE0 from the precharge control circuit 3 is output. By this signal, the first high voltage switching signal SAP1 and the first low voltage switching signal SAN1 are deactivated, and the second high voltage switching signal SAP2 and the second low voltage switching signal SAN2 are activated. A high voltage VH2 is supplied to the high potential node VP of the flip-flop, and a low voltage VL2 is supplied to the low potential node VN of the flip-flop. The bit line pair (BLT, BLB) is amplified in two stages from a first voltage level of VH1 and VL1 to a second voltage level of VH2 and VL2. At this time, since the selected word line (not shown) of the memory cell array is activated, the second voltage level of VH2 or VL2 is written into the memory cell. The timing of switching the power supply from the first voltage level to the second voltage level is controlled by a precharge control circuit.

  Here, the high voltage VH2 at the second voltage level is higher than the high voltage VH1 at the first voltage level, and the low voltage VL2 at the second voltage level is the low voltage VL1 at the first voltage level. Is a lower voltage. Therefore, the sense amplifier first performs an amplification operation with the voltage amplitudes of the high voltage VH1 and the low voltage VL1, and reads the data in the memory cell. Thereafter, the precharge signal PRE performs an amplifying operation with the high voltage VH2 and the low voltage VL2 having a large voltage amplitude, and writing into the memory cell with a voltage having a large voltage amplitude. Here, the high voltages VH1 and VH2 are power supply voltages supplied to the high potential node VP of the sense amplifier, and the low voltages VL1 and VL2 are power supply voltages supplied to the low potential node VN of the sense amplifier. Therefore, the high voltage and the low voltage are high and low voltages for performing the amplification operation of the sense amplifier, and the voltages are not absolute voltages but mean relative voltages.

  After the word line of the memory cell is deactivated, the precharge control circuit deactivates the zero precharge signal PRE0 and activates the first precharge signal PRE1 at time T2. The second high voltage switching signal SAP2 and the second low voltage switching signal SAN2 are deactivated by deactivation of the zero precharge signal PRE0, and the high voltage VH2 to the high potential node VP and the low potential node VN of the flip-flop are deactivated. The supply of the low voltage VL2 is stopped. The transistors Q5, Q6, and Q7 are turned on by the activation of the first precharge signal PRE1, so that the bit line pair (BLT, BLB) is precharged to the reference voltage VREF. Thus, the precharge timing is controlled by the precharge control circuit.

  The operation method of the sense amplifier according to the present embodiment is amplified in two stages from the first voltage level of the first VH1 and VL1 to the second voltage level of VH2 and VL2. The amplification of the sense amplifier can be performed in two stages, and the voltage level for securing the amount of charge necessary for data retention in the DRAM can be set with the minimum voltage stress application time. By using this operation method, there is no rapid voltage amplification, and noise during amplification of the sense amplifier can be reduced. Also, by applying the second voltage level only for a short period, the write voltage to the memory cell can be increased, and the charge amount of the memory cell can be ensured, and the characteristics of the MOS device can be degraded by minimizing the high voltage stress application time. Can be prevented. It is possible to obtain a sense amplifier operation method capable of ensuring the charge amount of the memory cell and preventing deterioration of device characteristics, and a highly reliable semiconductor device including these sense amplifiers.

  A second embodiment of the present invention will be described with reference to FIG. FIG. 3 shows a circuit diagram of the sense amplifier section according to the second embodiment. In the first embodiment, the two-stage switching of the power source to the flip-flop of the sense amplifier is performed on both the high potential side and the low potential side, but in this embodiment, the two-stage switching is performed only on the high potential side. It is an operation method. Compared with the sense amplifier unit circuit of the first embodiment, only the low-voltage power supply unit is different, and the other constituent elements have the same configuration and operation as those of the first embodiment.

  The sense amplifier circuit shown in FIG. 3 includes a bit line pair, a sense amplifier circuit, and a precharge circuit. The sense amplifier circuit includes a flip-flop unit, a high voltage power supply unit, and a low voltage power supply unit. The low voltage power supply unit of the present embodiment does not have a low voltage power supply control circuit, but includes a transistor Q12 that supplies a low voltage VL to the low potential node VN. The transistor Q12 has a drain connected to the low potential node VN of the flip-flop, a source connected to the low voltage VL, and a gate connected to the sense amplifier activation signal SA. Here, the low voltage VL may be a low voltage at which the flip-flop operates. The low voltage VL may be the same voltage as the low voltages VL1 and VL2 of the first embodiment, or may be a different voltage.

  Next, the operation of the sense amplifier unit will be described with reference to the timing chart of FIG. A word line (not shown) of the selected memory cell is activated. A sense amplifier activation signal SA for activating the sense amplifier is activated at time T0. In response to the sense amplifier activation signal SA, the high voltage power supply switching control circuit 1 outputs the first high voltage switching signal SAP1. The transistor Q8 is turned on by the first high voltage switching signal SAP1, and the high voltage VH1 is supplied to the high potential node VP of the flip-flop. In the low voltage power supply unit, the sense amplifier activation signal SA is directly input to the gate of the transistor Q12, and the transistor Q12 is turned on. A low voltage VL is supplied to the low potential node VN of the flip-flop. As a result, the bit line pair (BLT, BLB) is amplified to the third voltage level of the high voltage VH1 and the low voltage VL. Thus, the first amplification by the sense amplifier is performed by the sense amplifier activation signal SA.

  When the precharge signal PRE that activates the precharge is activated at time T1, the zero precharge signal PRE0 from the precharge control circuit 3 is output. By this signal, the first high voltage switching signal SAP1 is deactivated and the second high voltage switching signal SAP2 is activated. The voltage supplied to the high potential node VP of the flip-flop is switched from the high voltage VH1 to the high voltage VH2. Here, the high voltage VH2 is higher than the high voltage VH1. As described above, the timing of power supply switching is controlled by the precharge control circuit.

  Since the low voltage power supply unit is controlled by the sense amplifier activation signal SA, the low potential VL is supplied to the low potential node VN as it is, and the low voltage VL is supplied as it is. The bit line pair (BLT, BLB) is amplified in two stages from the third voltage level of the high voltage VH1 and the low voltage VL to the fourth voltage level of the high voltage VH2 and the low voltage VL. Since the selected word line (not shown) of the memory cell array is activated at this time, the fourth voltage levels of the high voltage VH2 and the low voltage VL are written into the memory cell. In the timing chart of FIG. 2, voltage switching on the low potential side from time T1 to time T2 is not performed.

  The word line of the memory cell is deactivated. Thereafter, the sense amplifier activation signal SA is deactivated, and the precharge control circuit deactivates the zero precharge signal PRE0 and activates the first precharge signal PRE1 at time T2. The second high voltage switching signal SAP2 is deactivated by deactivation of the zero precharge signal PRE0, and the supply of the high voltage VH2 to the high potential node VP of the flip-flop is stopped. Further, the inactivation of the sense amplifier activation signal SA stops the supply of the low voltage VL to the low potential node VN of the flip-flop. The transistors Q5, Q6, and Q7 are turned on by the activation of the first precharge signal PRE1, so that the bit line pair (BLT, BLB) is precharged to the reference voltage VREF. Thus, the precharge timing is controlled by the precharge control circuit.

  The operation method of the sense amplifier of the present embodiment is amplified in two steps from the first voltage level of the high voltage VH1 and the low voltage VL to the fourth voltage level of the high voltage VH2 and the low voltage VL. The amplification of the sense amplifier can be performed in two stages, and the voltage level for securing the amount of charge necessary for data retention in the DRAM can be set with the minimum voltage stress application time. By adopting this operation method, since abrupt voltage amplification is not performed, noise during amplification of the sense amplifier can be reduced. Also, by applying the voltage level of the high voltage VH2 only for a short period of time, the write voltage to the memory cell can be increased, and the charge amount of the memory cell is ensured, and the high voltage stress application time is minimized to minimize the characteristics of the MOS device. Deterioration can be prevented. It is possible to obtain a sense amplifier operation method capable of ensuring the charge amount of the memory cell and preventing deterioration of device characteristics, and a highly reliable semiconductor device including these sense amplifiers.

  A third embodiment of the present invention will be described with reference to FIG. FIG. 4 shows a circuit diagram of a sense amplifier section according to the third embodiment. In the first embodiment, the two-stage switching of the power supply to the flip-flop of the sense amplifier is performed on both the high potential side and the low potential side. However, in this embodiment, the two-stage switching is performed only on the low potential side. It is an operation method. Compared with the sense amplifier unit circuit of the first embodiment, only the high-voltage power supply unit is different, and the other components are the same in configuration and operation as those in the first embodiment.

  The sense amplifier circuit shown in FIG. 4 includes a bit line pair, a sense amplifier circuit, and a precharge circuit. The sense amplifier circuit includes a flip-flop, a high voltage power supply unit, and a low voltage power supply unit. The high voltage power supply unit of the present embodiment does not include the high voltage power supply control circuit 1 but includes a transistor Q13 that supplies the high voltage VH to the high potential node VP. The transistor Q13 has a drain connected to the high potential node VP of the flip-flop, a source connected to the high voltage VH, and a gate connected to the inverted sense amplifier activation signal SAB. Here, the high voltage VH only needs to be a high voltage at which the flip-flop operates. The high voltage VH may be the same voltage as the high voltage VH1 or VH2 of the first embodiment, or may be a different voltage.

  Further, the operation of the sense amplifier unit will be described with reference to the timing chart of FIG. A word line (not shown) of the selected memory cell is activated. A sense amplifier activation signal SA for activating the sense amplifier is activated at time T0. A first low voltage switching signal SAN1 is output from the low voltage power supply switching control circuit 2 in response to the sense amplifier activation signal SA. The transistor Q10 is turned on by the first low voltage switching signal SAN1, and the low voltage VL1 is supplied to the low potential node VN of the flip-flop. In the high voltage power supply unit, the inverted sense amplifier activation signal SAB is directly input to the gate of the transistor Q13, and the transistor Q13 is turned on. A high voltage VH is supplied to the high potential node VP of the flip-flop. As a result, the bit line pair (BLT, BLB) is amplified to the fifth voltage level of the high voltage VH and the low voltage VL1. Thus, the first amplification by the sense amplifier is performed by the sense amplifier activation signal SA.

  When the precharge signal PRE that activates the precharge is activated at time T1, the zero precharge signal PRE0 from the precharge control circuit 3 is output. By this signal, the first low voltage switching signal SAN1 is deactivated and the second low voltage switching signal SAN2 is activated. The voltage supplied to the low potential node VN of the flip-flop is switched from the low voltage VL1 to the low voltage VL2. As described above, the timing of power supply switching is controlled by the precharge control circuit.

  Since the high voltage power supply unit is controlled by the inverted sense amplifier activation signal SAB, the high potential VH is supplied to the high potential node VP as it is. The bit line pair (BLT, BLB) is amplified in two stages from the fifth voltage level of the high voltage VH and the low voltage VL1 to the sixth voltage level of the high voltage VH and the low voltage VL2. At this time, since the selected word line (not shown) of the memory cell array is activated, the sixth voltage levels of the high voltage VH and the low voltage VL2 are written into the memory cells. In the timing chart of FIG. 2, voltage switching on the high potential side from time T1 to time T2 is not performed.

  The word line of the memory cell is deactivated. Thereafter, the sense amplifier activation signal SA is deactivated, and the precharge control circuit deactivates the zero precharge signal PRE0 and activates the first precharge signal PRE1 at time T2. The deactivation of the zero precharge signal PRE0 deactivates the second low voltage switching signal SAN2, and the supply of the low voltage VL2 to the low potential node VN of the flip-flop is stopped. Further, the inactivation of the inverted sense amplifier activation signal SAB stops the supply of the high voltage VH to the high potential node VP of the flip-flop. The transistors Q5, Q6, and Q7 are turned on by the activation of the first precharge signal PRE1, so that the bit line pair (BLT, BLB) is precharged to the reference voltage VREF. Thus, the precharge timing is controlled by the precharge control circuit.

  The operation method of the sense amplifier of this embodiment is amplified in two stages from the first voltage level of the high voltage VH and the low voltage VL1 to the sixth voltage level of the high voltage VH and the low voltage VL2. It is possible to set the voltage level for securing the amount of charge necessary for data retention in the DRAM with a minimum voltage stress application time by making the amplification of the sense amplifier into two stages. By adopting this operation method, since abrupt voltage amplification is not performed, noise during amplification of the sense amplifier can be reduced. In addition, by applying a voltage level having a large voltage amplitude (VH, VL2) only for a short period, the write voltage to the memory cell can be increased, and the charge amount of the memory cell is ensured, and the high voltage stress application time is minimized. Therefore, it is possible to prevent the characteristic deterioration of the MOS device. It is possible to obtain a sense amplifier operation method capable of ensuring the charge amount of the memory cell and preventing deterioration of device characteristics, and a highly reliable semiconductor device including these sense amplifiers.

  As mentioned above, although it explained in full detail about the Example, this application is not limited to the said Example. As the operation of the sense amplifier in the embodiment, the data read from the memory cell has been described, but it goes without saying that the same operation is performed at the time of writing. It is needless to say that various modifications can be made without departing from the concept of the present invention, and these are included in the present application.

FIG. 3 is a circuit diagram of a sense amplifier unit according to the first embodiment. It is a timing chart in FIG. 6 is a circuit diagram of a sense amplifier section according to Embodiment 2. FIG. 6 is a circuit diagram of a sense amplifier section according to Embodiment 3. FIG. It is a sense amplifier part circuit diagram concerning a conventional example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High voltage power supply switching control circuit 2 Low voltage power supply switching control circuit 3 Precharge control circuit Q1-Q15 Transistor BLT, BLB Bit line SAP1, SAP2 High voltage switching signal SAN1, SAN2 Low voltage switching signal SA Sense amplifier activation signal SAB Inversion Sense amplifier activation signal PRE Precharge signal VN Low potential node VP High potential node VH, VH1, VH2 High voltage VL, VL1, VL2 Low voltage VREF Reference voltage

Claims (10)

  In the sense amplifier operating method, the voltage level amplified by the sense amplifier is set to two stages, first the data from the memory cell is read by amplification of the first voltage level, and then the second voltage having a voltage amplitude larger than the first voltage level. A method of operating a sense amplifier, wherein writing to a memory cell is performed by amplification of a voltage level.   2. The sense amplifier operating method according to claim 1, wherein the amplification of the first voltage level is performed by a sense amplifier activation signal.   3. The sense amplifier operation method according to claim 1, wherein the amplification of the second voltage level is performed before a precharge operation by inputting a precharge signal.   In a semiconductor device, a sense amplifier including a flip-flop connected between a high potential node and a low potential node and amplifying data of a bit line pair, and a high voltage power supply switching control circuit connected to the high potential node The voltage level to be amplified is divided into two stages. First, data is read from the memory cell by amplification of the first voltage level, and then to the memory cell by amplification of the second voltage level having a voltage amplitude larger than the first voltage level. A semiconductor device characterized in that writing is performed.   5. The semiconductor device according to claim 4, wherein the amplification of the first voltage level is performed by a sense amplifier activation signal.   6. The semiconductor device according to claim 4, wherein the amplification of the second voltage level is performed before a precharge operation by inputting a precharge signal.   5. The semiconductor device according to claim 4, wherein the sense amplifier further includes a low voltage power supply switching control circuit connected to the low potential node.   In a semiconductor device, a sense amplifier including a flip-flop connected between a high potential node and a low potential node and amplifying data of a bit line pair, and a low voltage power supply switching control circuit connected to the low potential node is provided. The voltage level to be amplified is divided into two stages. First, data is read from the memory cell by amplification of the first voltage level, and then to the memory cell by amplification of the second voltage level having a voltage amplitude larger than the first voltage level. A semiconductor device characterized in that writing is performed.   9. The semiconductor device according to claim 8, wherein the amplification of the first voltage level is performed by a sense amplifier activation signal. 10. The semiconductor device according to claim 8, wherein the amplification of the second voltage level is performed before a precharge operation by inputting a precharge signal.

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