JP2007048621A - Plasma treatment apparatus - Google Patents

Plasma treatment apparatus Download PDF

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JP2007048621A
JP2007048621A JP2005232306A JP2005232306A JP2007048621A JP 2007048621 A JP2007048621 A JP 2007048621A JP 2005232306 A JP2005232306 A JP 2005232306A JP 2005232306 A JP2005232306 A JP 2005232306A JP 2007048621 A JP2007048621 A JP 2007048621A
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electrode
sample
impedance
electric field
counter electrode
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JP4643387B2 (en
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Yusuke Ehata
裕介 江畑
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Sharp Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma treatment apparatus with a high treatment rate without damages of a sample surface by plasma. <P>SOLUTION: In this plasma treatment apparatus provided with an electrode unit provided with an applicator to which power generated from a power supply is applied and a counter electrode facing the applicator through an insulator, and an impedance component inserted between the counter electrode and ground potential, the electrode unit faces a sample with a gap, reactive gas is locally supplied to the space formed between the electrode unit and the sample, and plasma is generated between the applicator and the counter electrode with the power applied to the applicator to treat the sample using the reactive gas. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、プラズマを用いて表面処理を行うプラズマ処理装置に関する。   The present invention relates to a plasma processing apparatus that performs surface treatment using plasma.

現在、半導体や液晶表示装置などの各種デバイスの多層構造におけるエッチング、成膜、アッシング、表面親水化などの表面処理を行う装置としてはプラズマを用いた表面処理装置が広く使用されている。その中でも近年、高速処理、装置の低価格化、装置占有面積の低減などを目的として大気圧近傍の圧力でプラズマを発生させ、試料に対する処理を行なう大気圧プラズマ処理装置が開発されている。   At present, a surface treatment apparatus using plasma is widely used as an apparatus for performing surface treatment such as etching, film formation, ashing, and surface hydrophilization in a multilayer structure of various devices such as semiconductors and liquid crystal display devices. Among them, in recent years, an atmospheric pressure plasma processing apparatus that generates plasma at a pressure near atmospheric pressure and processes a sample has been developed for the purpose of high-speed processing, cost reduction of the apparatus, reduction of the area occupied by the apparatus, and the like.

上記大気圧プラズマ処理装置の1つとして、電源を有し、該電源からの電力が印加される印加電極と前記印加電極と絶縁体を介して対向した接地電極をまとめて電極ユニットとし、前記電極ユニットを試料に対向させ、更に前記電極ユニットと試料の間に大気圧を含む高圧力の反応ガス領域を形成し、前記印加電極と接地電極間のうち試料に近接した領域のみで該反応ガスに基づく高圧プラズマを発生させ、前記高圧プラズマ中で生じた活性種により試料の処理を行なう装置が知られている(例えば、特許文献1参照)。   As one of the above atmospheric pressure plasma processing apparatuses, an electrode unit having an electric power source and an application electrode to which electric power from the electric power source is applied and a ground electrode opposed to the application electrode through an insulator are collectively provided as the electrode unit. The unit is opposed to the sample, and a high-pressure reaction gas region including atmospheric pressure is formed between the electrode unit and the sample, and only the region close to the sample between the application electrode and the ground electrode is exposed to the reaction gas. There is known an apparatus for generating a high-pressure plasma based thereon and processing a sample with active species generated in the high-pressure plasma (see, for example, Patent Document 1).

以下に特許文献1に記載された高圧プラズマ装置を図13を用いて説明する。
図13は、電極浮上型高圧浮上電極の断面図であり、特許文献1に記載される装置の構成を示す概略図である。
図13中、H1は電極浮上型高圧浮上電極、101は高圧反応ガス供給口、102は反応ガス排気口、103は内側電極、104は外側電極、105は絶縁体、106は電力伝達線路開放端、107は試料台、108は試料、109は高圧プラズマ、110は反応ガス流、Dは前記電極H1と試料108との間隔である。
Hereinafter, the high-pressure plasma apparatus described in Patent Document 1 will be described with reference to FIG.
FIG. 13 is a cross-sectional view of an electrode levitation type high-voltage levitation electrode, and is a schematic diagram illustrating a configuration of an apparatus described in Patent Document 1.
In FIG. 13, H1 is an electrode floating type high pressure floating electrode, 101 is a high pressure reaction gas supply port, 102 is a reaction gas exhaust port, 103 is an inner electrode, 104 is an outer electrode, 105 is an insulator, and 106 is an open end of a power transmission line 107 is a sample stage, 108 is a sample, 109 is high-pressure plasma, 110 is a reactive gas flow, and D is the distance between the electrode H1 and the sample 108.

内側電極103と外側電極104、及び絶縁体105で前記電極浮上型高圧浮上電極H1を形成しており、電極H1と試料108は所定の気体雰囲気内に対向して配置されている。この時、高圧反応ガス供給口101より高圧反応ガスを供給すると、高圧反応ガス供給口101から、反応ガス排気口102若しくは周囲の気体雰囲気に向う反応ガス流110が形成され、供給された高圧反応ガスと周囲気体雰囲気との差圧によって電極H1は間隔Dだけ浮上し、間隔Dが狭いことから電極H1と試料108に挟まれる部分に、高圧反応ガス供給口101から反応ガス排気口102にむかう反応ガス流路、また高圧反応ガス供給口101から電極H1周囲の気体雰囲気にむかう反応ガス流路が低コンダクタンスな気体流路となり、電極H1と試料108に挟まれる部分に高圧反応ガス領域を形成する。ここで前記高圧反応ガス領域の圧力は大気圧であってよい。   The electrode floating type high voltage floating electrode H1 is formed by the inner electrode 103, the outer electrode 104, and the insulator 105, and the electrode H1 and the sample 108 are arranged to face each other in a predetermined gas atmosphere. At this time, when a high-pressure reaction gas is supplied from the high-pressure reaction gas supply port 101, a reaction gas flow 110 is formed from the high-pressure reaction gas supply port 101 toward the reaction gas exhaust port 102 or the surrounding gas atmosphere, and the supplied high-pressure reaction is performed. Due to the differential pressure between the gas and the ambient gas atmosphere, the electrode H1 floats by a distance D. Since the distance D is narrow, the electrode H1 and the sample 108 are moved from the high-pressure reaction gas supply port 101 to the reaction gas exhaust port 102. The reaction gas flow path and the reaction gas flow path from the high pressure reaction gas supply port 101 to the gas atmosphere around the electrode H1 become a low conductance gas flow path, and a high pressure reaction gas region is formed in a portion sandwiched between the electrode H1 and the sample 108. To do. Here, the pressure in the high-pressure reaction gas region may be atmospheric pressure.

この時、電極H1を試料108に対して浮上させず、電極H1と試料108との間隔Dを近接させ配置することによっても、同様に高圧反応ガス供給口101から反応ガス排気口102にむかう反応ガス流路、また高圧反応ガス供給口101から前記電極周囲にむかう反応ガス流路は低コンダクタンスな気体流路となり、前記電極と試料108に挟まれる部分に高圧反応ガス領域を形成することができる。   At this time, the reaction from the high-pressure reaction gas supply port 101 to the reaction gas exhaust port 102 can be similarly performed by placing the electrode H1 so as not to float with respect to the sample 108 and disposing the electrode H1 and the sample 108 close to each other. The gas flow path and the reaction gas flow path from the high pressure reaction gas supply port 101 to the periphery of the electrode become a low conductance gas flow path, and a high pressure reaction gas region can be formed in a portion sandwiched between the electrode and the sample 108. .

更に内側電極103は図示されない電源に接続され、同時に外側電極104は接地されており、内側電極103と外側電極104に挟まれる絶縁体105部分に電力伝達線路を形成する。電源より発生した電力は内側電極103に印加され、内側電極103と外側電極104の間で形成される電力伝達線路を通じて電力伝達線路開放端106に達し、電極H1と試料108の間に形成された高圧反応ガス領域のうち、高圧反応ガス供給口101より離れた位置に局所的な高圧プラズマ109が発生し、高圧プラズマ109で発生した活性種により試料108の成膜、加工、表面処理を行なう。また試料108と電極H1を相対移動させることによって試料108全体の処理を行なう。   Further, the inner electrode 103 is connected to a power source (not shown), and at the same time, the outer electrode 104 is grounded, and a power transmission line is formed in an insulator 105 portion sandwiched between the inner electrode 103 and the outer electrode 104. The power generated from the power source is applied to the inner electrode 103, reaches the power transmission line open end 106 through the power transmission line formed between the inner electrode 103 and the outer electrode 104, and is formed between the electrode H 1 and the sample 108. In the high-pressure reaction gas region, a local high-pressure plasma 109 is generated at a position away from the high-pressure reaction gas supply port 101, and the film 108 is formed, processed, and surface-treated by the active species generated by the high-pressure plasma 109. Further, the entire sample 108 is processed by relatively moving the sample 108 and the electrode H1.

この時、本装置は、電力が印加された内側電極103と試料108間にプラズマを発生させるわけではなく、電力が印加された内側電極103と接地された外側電極104との間に高圧プラズマ109を発生させ、プラズマ中で発生した活性種を試料108の表面に拡散させ成膜、加工、表面処理を行なうため、試料108に直接プラズマが接触せず試料108を損傷しない。
特開2000−306848号公報
At this time, the apparatus does not generate plasma between the inner electrode 103 to which electric power is applied and the sample 108, but the high-pressure plasma 109 between the inner electrode 103 to which electric power is applied and the outer electrode 104 that is grounded. Since the active species generated in the plasma are diffused on the surface of the sample 108 to perform film formation, processing, and surface treatment, the sample 108 is not in direct contact with the plasma and the sample 108 is not damaged.
JP 2000-306848 A

ここで内側電極103、外側電極104は紙面に垂直な方向に長手方向を持つ長尺状の電極であり、内側電極103と外側電極104が対向する電力伝達線路開放端106部分に紙面に垂直な方向に長いライン状の大気圧プラズマを発生させる場合について考える。
内側電極103に振幅1.0[kV]、周波数13.56[MHz]の高周波電圧を印加し、外側電極104を接地させた時の電界強度分布計算結果を図14に示す。
Here, the inner electrode 103 and the outer electrode 104 are long electrodes having a longitudinal direction in a direction perpendicular to the paper surface, and are perpendicular to the paper surface at the power transmission line open end portion 106 where the inner electrode 103 and the outer electrode 104 face each other. Consider the case of generating a line-shaped atmospheric pressure plasma that is long in the direction.
FIG. 14 shows the electric field intensity distribution calculation result when a high frequency voltage having an amplitude of 1.0 [kV] and a frequency of 13.56 [MHz] is applied to the inner electrode 103 and the outer electrode 104 is grounded.

試料108の表面をY=0[mm]とし、前記内側電極103の中央をX=0、Z=0[mm]とし、基板と電極ユニットH1下面の距離をD=4.0[mm]としている。また内側電極103と外側電極104との距離を3.0[mm]とし、内側電極103と外側電極104の間に設置された絶縁体105はアルミナ(比誘電率εr=9.4)とし、内側電極103と外側電極104の間の部分に高さ3.0mm、底辺7.0mmの窪みを有するものとして計算を行なった。また試料108は厚さ5.0mm、比誘電率5.5のガラスとし、更に試料108の下側は空気とする。   The surface of the sample 108 is Y = 0 [mm], the center of the inner electrode 103 is X = 0 and Z = 0 [mm], and the distance between the substrate and the lower surface of the electrode unit H1 is D = 4.0 [mm]. Yes. The distance between the inner electrode 103 and the outer electrode 104 is 3.0 [mm], and the insulator 105 disposed between the inner electrode 103 and the outer electrode 104 is alumina (relative dielectric constant εr = 9.4). The calculation was performed assuming that the portion between the inner electrode 103 and the outer electrode 104 has a recess with a height of 3.0 mm and a base of 7.0 mm. The sample 108 is made of glass having a thickness of 5.0 mm and a dielectric constant of 5.5, and the lower side of the sample 108 is made of air.

また、内側電極103の直下(X=0[mm]、Z=0[mm]、領域A)の電界強度分布、及び内側電極103と外側電極104の間隔の中央部分(X=5.5[mm]、Z=0[mm]、領域B)、また外側電極104の直下(X=11.0[mm]、Z=0[mm]、領域C)の電界強度分布を図15に示す。   In addition, the electric field intensity distribution immediately below the inner electrode 103 (X = 0 [mm], Z = 0 [mm], region A) and the central portion (X = 5.5 [X] of the distance between the inner electrode 103 and the outer electrode 104). mm], Z = 0 [mm], region B), and the electric field intensity distribution immediately below the outer electrode 104 (X = 11.0 [mm], Z = 0 [mm], region C) is shown in FIG.

図14、図15に示すように、内側電極103と外側電極104の間の絶縁体105の窪み部分には最も大きな7.78E5[V/m]の電界強度が発生していることがわか
る。この時、同時に、内側電極103の直下の試料表面近傍にも1.35E5[V/m]
の電界強度が、外側電極104の直下の試料表面近傍には0.3[V/m]の電界強度が
発生している。
As shown in FIGS. 14 and 15, it can be seen that the largest electric field strength of 7.78E5 [V / m] is generated in the recessed portion of the insulator 105 between the inner electrode 103 and the outer electrode 104. At this time, 1.35E5 [V / m] is also applied to the vicinity of the sample surface immediately below the inner electrode 103.
An electric field strength of 0.3 [V / m] is generated in the vicinity of the sample surface immediately below the outer electrode 104.

この時、内側電極103に対する印加電圧を大きくしてゆくと最も大きな電界強度が発生している内側電極103と外側電極104の間の絶縁体105の窪み部分に反応ガスに応じた大気圧プラズマが発生し、大気圧プラズマ中で発生した活性種により試料106の表面に対し成膜、加工、表面処理を行なうのであるが、更に処理速度を増加させるため内側電極103に対する投入電力、即ち印加電圧を増加させると、内側電極103と外側電極104の間に発生した大気圧プラズマの分解が促進されると同時に、内側電極103の直下の試料108表面近傍の電界強度も増加し、最終的には前記試料108の表面にも大気圧プラズマが発生し、試料表面に直接大気圧プラズマが接触することで試料表面に損傷を与えるという課題を有する。逆に、試料108の表面に大気圧プラズマが発生しない程度しか内側電極103には電力、電圧を印加できないことになり、投入電力の上限が規定され、高い処理速度を達成することができないという課題を有するのである。   At this time, when the applied voltage to the inner electrode 103 is increased, atmospheric pressure plasma corresponding to the reaction gas is generated in the hollow portion of the insulator 105 between the inner electrode 103 and the outer electrode 104 where the greatest electric field strength is generated. The film is formed, processed, and surface-treated on the surface of the sample 106 by the active species generated in the atmospheric pressure plasma. In order to further increase the processing speed, the input power to the inner electrode 103, that is, the applied voltage is set. Increasing the pressure promotes the decomposition of the atmospheric pressure plasma generated between the inner electrode 103 and the outer electrode 104, and at the same time increases the electric field strength near the surface of the sample 108 immediately below the inner electrode 103. Atmospheric pressure plasma is also generated on the surface of the sample 108, and there is a problem that the sample surface is damaged by direct contact of the atmospheric pressure plasma with the sample surface. Conversely, power and voltage can be applied to the inner electrode 103 only to the extent that atmospheric pressure plasma is not generated on the surface of the sample 108, and the upper limit of input power is defined, and a high processing speed cannot be achieved. It has.

この時、図14、図15の計算結果から、内側電極103の近傍で最も高い電界強度をEp、試料108の表面上で最も高い電界強度をEsとすると、Ep/Es=7.78E5/1.35E5=5.8倍となる。これは内側電極103への印加電圧を増大させ、内側電極103と外側電極104の間の最も高い電界強度Epの部分で大気圧プラズマが発生した時の印加電圧の5.8倍の印加電圧を内側電極103に印加すると、試料108の表面の表面上で最も高い電界強度Esの部分もプラズマ発生電界強度に達し、試料表面上に大気圧プラズマが発生し試料108の表面を損傷することを示している。   At this time, from the calculation results of FIGS. 14 and 15, assuming that the highest electric field strength in the vicinity of the inner electrode 103 is Ep and the highest electric field strength on the surface of the sample 108 is Es, Ep / Es = 7.78E5 / 1 .35E5 = 5.8 times. This increases the applied voltage to the inner electrode 103, and the applied voltage is 5.8 times the applied voltage when atmospheric pressure plasma is generated in the portion of the highest electric field strength Ep between the inner electrode 103 and the outer electrode 104. When applied to the inner electrode 103, the portion of the highest electric field strength Es on the surface of the sample 108 also reaches the plasma generation electric field strength, indicating that atmospheric pressure plasma is generated on the sample surface and damages the surface of the sample 108. ing.

この発明は、電源から発生した電力が印加される印加電極と、前記印加電極に対し絶縁体を挟んで対向する対向電極とを備えた電極ユニット、および前記対向電極と接地電位間に挿入されたインピーダンス素子を備え、前記電極ユニットが試料にギャップを置いて対向し、更に前記電極ユニットと試料の間に形成される空間に局所的に反応ガスを供給し、前記印加電極に印加された電力によって前記印加電極と対向電極間にプラズマを発生させ、反応ガスに基く試料の処理を行なうプラズマ処理装置を提供するものである。   According to the present invention, an electrode unit including an application electrode to which power generated from a power source is applied, a counter electrode facing the application electrode with an insulator interposed therebetween, and the counter electrode and the ground potential are inserted An impedance element is provided, the electrode unit is opposed to the sample with a gap, and a reactive gas is locally supplied to a space formed between the electrode unit and the sample, and the power applied to the applied electrode The present invention provides a plasma processing apparatus for generating a plasma between the application electrode and the counter electrode and processing a sample based on a reaction gas.

この発明において、前記印加電極と対向電極間がその間にインピーダンスZcを有し、前記インピーダンス素子のインピーダンスZはZ=Zc(A・Exp[jθ]−1)、但し、θは任意の実数、Aは0≦A<1、且つ0.5≦A・cosθを満たす実数であってもよい。
また、前記印加電極と対向電極がその間にインピーダンスZcを有し、前記インピーダンス素子のインピーダンスZは、Z=−Zc/2であってもよい。
さらに、前記印加電極と対向電極がその間にインピーダンスZcを有し、前記インピーダンス素子のインピーダンスZは、Z=j・ Im[Zc(A・Exp[jθ]−1)]但し、θは任意の実数、Aは0≦A<1、且つ0.5≦A・cosθを満たす実数であってもよい。
前記インピーダンス素子は、インダクタンス素子と可変容量素子との直列回路で形成されてもよい。
In the present invention, the applied electrode and the counter electrode have an impedance Zc therebetween, and the impedance Z of the impedance element is Z = Zc (A · Exp [jθ] −1), where θ is an arbitrary real number, A May be a real number satisfying 0 ≦ A <1 and 0.5 ≦ A · cos θ.
The application electrode and the counter electrode may have an impedance Zc between them, and the impedance Z of the impedance element may be Z = −Zc / 2.
Furthermore, the applied electrode and the counter electrode have an impedance Zc between them, and the impedance Z of the impedance element is Z = j · Im [Zc (A · Exp [jθ] −1)], where θ is an arbitrary real number , A may be a real number satisfying 0 ≦ A <1 and 0.5 ≦ A · cos θ.
The impedance element may be formed of a series circuit of an inductance element and a variable capacitance element.

本発明によれば、試料表面に損傷を与えること無しに電極近傍により大きな電界強度を発生させ、強いては高い分解率、活性種密度を有する大気圧プラズマを発生させ、より高い処理速度を有するプラズマ処理装置を実現できる。   According to the present invention, a plasma having a higher processing speed is generated by generating a large electric field strength near the electrode without damaging the sample surface, and generating an atmospheric pressure plasma having a high decomposition rate and active species density. A processing device can be realized.

本発明の第1の実施形態について図1から図11を用いて説明する。
図1は本発明の第1の実施形態を示す概略図、図2は電極ユニット内部の等価回路図、図3はZとZcの関係1の、図4はZとZcの関係2の、図5はZとZcの関係3の各説明図である。
また、図6、図7はインピーダンスZを挿入した場合の試料近傍の電界強度分布計算結果、及び試料近傍の電界強度分布計算グラフである。
また、図8、図9はインピーダンスZを挿入しない場合の試料近傍の電界強度分布計算結果、及び試料近傍の電界強度分布計算グラフである。
また、図10は電圧比Vc/V、Vz/Vの変化を示すグラフ、図11は電界強度比E
p1/Es1の変化を示すグラフである。
A first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a schematic diagram showing a first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram inside the electrode unit, FIG. 3 is a diagram showing a relationship 1 between Z and Zc, and FIG. 4 is a diagram showing a relationship 2 between Z and Zc. 5 is an explanatory diagram of the relationship 3 between Z and Zc.
6 and 7 are a calculation result of the electric field intensity distribution near the sample when the impedance Z is inserted, and an electric field intensity distribution calculation graph near the sample.
8 and 9 are a calculation result of the electric field intensity distribution near the sample when the impedance Z is not inserted, and an electric field intensity distribution calculation graph near the sample.
FIG. 10 is a graph showing changes in the voltage ratios Vc / V and Vz / V, and FIG.
It is a graph which shows the change of p1 / Es1.

図1中、1は印加電極、2は対向電極、3は絶縁体、4は接地金属筐体、5は電極ユニット、6は電力伝達線路、7はインピーダンス回路素子Z、8は電源、9はマッチングボックス、10は試料、11は反応ガス供給口、12は反応ガス排気口、13は反応ガス流、14は大気圧プラズマである。   In FIG. 1, 1 is an applied electrode, 2 is a counter electrode, 3 is an insulator, 4 is a ground metal housing, 5 is an electrode unit, 6 is a power transmission line, 7 is an impedance circuit element Z, 8 is a power source, 9 is Matching box 10 is a sample, 11 is a reactive gas supply port, 12 is a reactive gas exhaust port, 13 is a reactive gas flow, and 14 is an atmospheric pressure plasma.

3つの印加電極1、4つの対向電極2は紙面に垂直な方向に延びる長尺状の電極であり、印加電極1、対向電極2は絶縁体3を介して互いに対向して配置され、印加電極1、対向電極2、絶縁体3、接地金属筐体4で電極ユニット5を形成し、電極ユニット5と試料10は所定の気体雰囲気内に配置されている。更に電極ユニット5は試料10に対して、間隔がGとなるように互いに相対移動が可能なように配置されており、反応ガス供給口11より所望の反応ガスを供給し、また反応ガス排気口12より排気を行なうと、試料10と電極ユニット5との間に形成される反応ガス流路に反応ガス流13が流れることとなる。   The three application electrodes 1 and the four counter electrodes 2 are elongated electrodes extending in a direction perpendicular to the paper surface. The application electrode 1 and the counter electrode 2 are arranged to face each other with an insulator 3 interposed between them. 1, the counter electrode 2, the insulator 3, and the ground metal casing 4 form an electrode unit 5, and the electrode unit 5 and the sample 10 are arranged in a predetermined gas atmosphere. Further, the electrode unit 5 is arranged so as to be relatively movable with respect to the sample 10 so that the interval is G, and a desired reaction gas is supplied from the reaction gas supply port 11, and a reaction gas exhaust port is provided. When the gas is exhausted from 12, the reaction gas flow 13 flows through the reaction gas flow path formed between the sample 10 and the electrode unit 5.

電源8は一対の出力端子を有し、3つの印加電極1は、電力伝達線路6、マッチングボックス9を通じて電源8の一方の出力端子に接続され、電源8の他方の出力端子は接地される。4つの対向電極2は、図1のインピーダンス素子7(インピーダンスZ)を介して接地されている。また、接地金属筐体4は直接接地されている。また、印加電極1と対向電極2間に形成される容量をC、また、その間のインピーダンスをZcとする。従って、印加電極1と対向電極2間にプラズマが発生していない場合は、インピーダンスZcは容量Cを用いて以下の式(1)で表される。
Zc=1/(2πf・C・j) ……(1)
また、印加電極1と対向電極2間にプラズマが発生している場合はZcは実部と虚部からなる複素数で表される。
The power supply 8 has a pair of output terminals, and the three application electrodes 1 are connected to one output terminal of the power supply 8 through the power transmission line 6 and the matching box 9, and the other output terminal of the power supply 8 is grounded. The four counter electrodes 2 are grounded via the impedance element 7 (impedance Z) of FIG. The ground metal casing 4 is directly grounded. Further, a capacitance formed between the application electrode 1 and the counter electrode 2 is C, and an impedance therebetween is Zc. Therefore, when plasma is not generated between the application electrode 1 and the counter electrode 2, the impedance Zc is expressed by the following formula (1) using the capacitance C.
Zc = 1 / (2πf · C · j) (1)
Further, when plasma is generated between the application electrode 1 and the counter electrode 2, Zc is represented by a complex number composed of a real part and an imaginary part.

ここで、電源8は周波数f[Hz]の電力(低周波電力、高周波電力、VHF電力、マイクロ電力等)を発振しており、発振する電圧波形は略正弦波形とする。
電源8から発生した電力は、電力伝達線路6を通じて印加電極1に印加され、印加電極1の電位をV、対向電極2の電位をVz、印加電極1と対向電極2の電位差をVc、また印加電極1への入力インピーダンスをZin、電流をIとすると電極ユニット5の等価回路は図2のように表されるため、以下の式が成り立つ。
V=Vc+Vz=I・Zin ……(2)
Zin=Zc+Z ……(3)
Vz=I・Z ……(4)
Vc=I・Zc ……(5)
ここで式(2)〜式(5)を用いてVc、VzとVの関係は以下の式(6)、式(7)のようになる。
Here, the power supply 8 oscillates power of frequency f [Hz] (low frequency power, high frequency power, VHF power, micro power, etc.), and the oscillating voltage waveform is a substantially sine waveform.
The power generated from the power source 8 is applied to the application electrode 1 through the power transmission line 6, the potential of the application electrode 1 is V, the potential of the counter electrode 2 is Vz, the potential difference between the application electrode 1 and the counter electrode 2 is Vc, and is applied. If the input impedance to the electrode 1 is Zin and the current is I, the equivalent circuit of the electrode unit 5 is represented as shown in FIG.
V = Vc + Vz = I · Zin (2)
Zin = Zc + Z (3)
Vz = I · Z (4)
Vc = I · Zc (5)
Here, using the formulas (2) to (5), the relationship between Vc, Vz and V is as shown in the following formulas (6) and (7).

式(6)、式(7)で印加電極1の電位Vに対して印加電圧1と対向電極2との間の電圧Vcを大きく、同時に印加電極1の電位Vに対して対向電極2の電位Vzが等しいか、又は小さくする場合(以下の式(8)、式(9)で表される不等式)のZcとZの関係を考える。
|Vc|>|V| ……(8)
|Vz|≦|V| ……(9)
In the expressions (6) and (7), the voltage Vc between the applied voltage 1 and the counter electrode 2 is increased with respect to the potential V of the applied electrode 1, and at the same time, the potential of the counter electrode 2 with respect to the potential V of the applied electrode 1 Consider the relationship between Zc and Z when Vz is equal or smaller (inequality represented by the following equations (8) and (9)).
| Vc | > | V | …… (8)
| Vz | ≦ | V | ...... (9)

式(6)及び式(8)から、式(8)で表されるVcとVの関係を満たすZ、Zcの関係は、式(6)中の分母(1+Z/Zc)が、図3に示されるような複素平面上において半径1の円内(但し、線上を含まない)にあればよいことになる為、前記式(6)の分母(1+Z/Zc)は以下の式(10)で表すことができる。
1+Z/Zc=A・Exp[j・θ] ……(10)
但し、Aは0≦A<1の実数、θは任意の実数
From Equation (6) and Equation (8), the relationship between Z and Zc satisfying the relationship between Vc and V expressed by Equation (8) is as follows. The denominator (1 + Z / Zc) in Equation (6) is as shown in FIG. The denominator (1 + Z / Zc) of the equation (6) is given by the following equation (10) because it suffices to be within a circle of radius 1 (not including the line) on the complex plane as shown. Can be represented.
1 + Z / Zc = A · Exp [j · θ] (10)
Where A is a real number of 0 ≦ A <1 and θ is any real number

また式(7)及び式(9)から、式(9)で表されるVzとVの関係を満たすZ、Zcの関係は、式(7)中の分母(1+Zc/Z)が、図4に示されるような複素平面上において半径1の円外(但し、線上を含む)にあればよいことになる為、前記式(7)の分母(1+Zc/Z)は以下の式(11)で表すことができる。
1+Zc/Z=B・Exp[j・φ] ……(11)
但し、BはB≧1の実数、φは任意の実数
従って、式(10)、式(11)からZは以下のように表すことができる。
Z=Zc・(A・Exp[j・θ]−1) ……(12)
Further, from the equations (7) and (9), the relationship between Z and Zc satisfying the relationship between Vz and V represented by the equation (9) is the denominator (1 + Zc / Z) in the equation (7). Therefore, the denominator (1 + Zc / Z) of the equation (7) is expressed by the following equation (11) because it is only necessary to be outside the circle of radius 1 (including the line) on the complex plane as shown in FIG. Can be represented.
1 + Zc / Z = B · Exp [j · φ] (11)
However, B is a real number of B ≧ 1, and φ is an arbitrary real number. Therefore, Z can be expressed as follows from the equations (10) and (11).
Z = Zc · (A · Exp [j · θ] -1) (12)

式(12)および式(13)が満たされなければならないことから、以下の式(14)が成立しなければならない。   Since Expression (12) and Expression (13) must be satisfied, the following Expression (14) must be satisfied.

上記式(14)をB・Exp[j・φ]について解くと式(15)のようになる。 When the above equation (14) is solved for B · Exp [j · φ], equation (15) is obtained.

ここで、BはB≧1で無ければならないことから以下の式(16)が成り立つ。
|A・Exp[j・θ]|≧|A・Exp[j・θ]−1| ……(16)
従って、式(16)を変形させてゆくと、以下の式(17−1)〜式(17−4)
のようになる。
|A・Exp[j・θ]|2≧|A・Exp[j・θ]−1|2 ……(17−1)
A2・Exp[j・θ]・Exp[−j・θ]≧(A・Exp[j・θ]−1)・
(A・Exp[−j・θ]−1) ……(17−2)
A・Exp[j・θ]+A・Exp[−j・θ]≧1 ……(17−3)
A・(cosθ+j・sinθ)+A・(cosθ−j・sinθ)≧1…(17−4)
従って、以下の式(18)が成立しなければならないことになる。
A・cosθ≧1/2 ……(18)
但しAは0≦A<1の実数、θは任意の実数。
Here, since B must be B ≧ 1, the following equation (16) holds.
| A · Exp [j · θ] | ≧ | A · Exp [j · θ] -1 | (16)
Therefore, when the equation (16) is changed, the following equations (17-1) to (17-4)
become that way.
| A · Exp [j · θ] | 2 ≧ | A · Exp [j · θ] -1 | 2 (17-1)
A 2 · Exp [j · θ] · Exp [−j · θ] ≧ (A · Exp [j · θ] −1)
(A • Exp [−j • θ] −1) (17-2)
A · Exp [j · θ] + A · Exp [−j · θ] ≧ 1 (17-3)
A · (cos θ + j · sin θ) + A · (cos θ−j · sin θ) ≧ 1 (17-4)
Therefore, the following formula (18) must be established.
A ・ cos θ ≧ 1/2 …… (18)
However, A is a real number of 0 ≦ A <1, and θ is an arbitrary real number.

逆に、前記印加電極1と対向電極2との間に形成されるインピーダンスZcに対して、式(18)、式(12)で表される値にZを設定する時、式(8)、式(9)を実現することができる。
従って、印加電極1と接地電位との電位差Vに対して印加電極1と対向電極2との間の電圧Vcを大きくすることができ、また同時に印加電極1と接地電位との電位差Vに対して対向電極2と接地電位との電位差Vzの大きさを小さくすることができることになる。
ここで、この時の印荷電極1、対向電極2近傍の電界強度分布について計算した結果について以下に示す。
Conversely, when Z is set to the value represented by the equations (18) and (12) with respect to the impedance Zc formed between the application electrode 1 and the counter electrode 2, the equation (8), Equation (9) can be realized.
Therefore, the voltage Vc between the application electrode 1 and the counter electrode 2 can be increased with respect to the potential difference V between the application electrode 1 and the ground potential, and at the same time with respect to the potential difference V between the application electrode 1 and the ground potential. The magnitude of the potential difference Vz between the counter electrode 2 and the ground potential can be reduced.
Here, the calculation result of the electric field intensity distribution in the vicinity of the imprint electrode 1 and the counter electrode 2 at this time is shown below.

印加電極1、対向電極2を共に完全導体とし印加電極1と対向電極間の距離を3[mm]とし、電極ユニット5の下面と試料10との距離をG=4.0[mm]とし、また印加電極1と対向電極2を覆う絶縁体3は比誘電率εr=9.6のアルミナとし、印加電極1に印加された電圧Vは、周波数f=13.56[MHz]の振幅|V|=1.0[kV]の高周波電圧であるとする。また試料10は厚み5.0mm、比誘電率5.5のガラスとし、更に試料10の下側は空気とした。   The application electrode 1 and the counter electrode 2 are both perfect conductors, the distance between the application electrode 1 and the counter electrode is 3 [mm], the distance between the lower surface of the electrode unit 5 and the sample 10 is G = 4.0 [mm], The insulator 3 covering the application electrode 1 and the counter electrode 2 is made of alumina having a relative dielectric constant εr = 9.6, and the voltage V applied to the application electrode 1 has an amplitude | V of a frequency f = 13.56 [MHz]. It is assumed that | = 1.0 [kV] high-frequency voltage. Sample 10 was made of glass having a thickness of 5.0 mm and a relative dielectric constant of 5.5, and the lower side of sample 10 was made of air.

この時、同時にインピーダンス回路素子Zにより、印加電極1と対向電極2の間には
Vc=2V ……(19)
なる電圧が発生しているものとする。
この時、式(19)で示される電圧関係を発生しうるインピーダンス回路素子Zの値は、式(6)より以下のように表される。
Z=−Zc/2 ……(20)
At the same time, the impedance circuit element Z causes Vc = 2V between the applied electrode 1 and the counter electrode 2 (19).
It is assumed that a voltage is generated.
At this time, the value of the impedance circuit element Z that can generate the voltage relationship represented by Expression (19) is expressed as follows from Expression (6).
Z = −Zc / 2 (20)

また、この時、対向電極2と接地電位間の電位差Vzは式(7)より、
Vz=−V ……(21)
となり、対向電極2には、印加電極1に印加された電圧Vに対して大きさが等しく、位相
がπ(180°)だけ異なる電圧が発生していることになる。この時の試料近傍の電界強度分布計算結果を図6に示す。但し、図1中の3つある印加電極1の中央の電極の中央をX=0、Z=0[mm]とし、試料10の表面をY=0とし、試料10から電極ユニット5方向をY軸の正方向にとった。
At this time, the potential difference Vz between the counter electrode 2 and the ground potential is expressed by the equation (7):
Vz = −V (21)
Thus, a voltage is generated in the counter electrode 2 that is equal in magnitude to the voltage V applied to the application electrode 1 and is different in phase by π (180 °). FIG. 6 shows the calculation result of the electric field strength distribution near the sample at this time. However, the center of the center of the three application electrodes 1 in FIG. 1 is X = 0, Z = 0 [mm], the surface of the sample 10 is Y = 0, and the direction from the sample 10 to the electrode unit 5 is Y. Taken in the positive direction of the axis.

また、印加電極1の直下(X=0[mm]、Z=0[mm]、領域A′)の電界強度分布、及び印加電極1と対向電極2の間隔の中央部分(X=5.5[mm]、Z=0[mm]、領域B′)、また、対向電極2の直下(X=11.0[mm]、Z=0[mm]、領域C′)の電界強度分布計算グラフを図7に示す。   Further, the electric field intensity distribution immediately below the application electrode 1 (X = 0 [mm], Z = 0 [mm], region A ′) and the central portion (X = 5.5) between the application electrode 1 and the counter electrode 2. [Mm], Z = 0 [mm], region B ′), and electric field intensity distribution calculation graph immediately below the counter electrode 2 (X = 11.0 [mm], Z = 0 [mm], region C ′) Is shown in FIG.

また、比較のため、対向電極2にインピーダンス回路素子Zを介さずそのまま接地し、印加電極1に周波数f=13.56[MHz]、|V|=1.0[kV]の高周波電圧
を印加した場合の試料近傍の電界強度分布計算結果を図8に、また印加電極1の直下(X=0[mm]、Z=0[mm]、領域A″)の電界強度分布、及び印加電極1と対向電極2の間隔の中央部分(X=5.5[mm]、Z=0[mm]、領域B″)、また対向電極2の直下(X=11.0[mm]、Z=0[mm]、領域C″)の電界強度分布計算グラフを図9に示す。図8、図9は従来技術と同じ接地方式による計算結果となる。この場合の印荷電極1と対向電極2間の電位差VcはVc=V、また対向電極2と接地電位間の電
位差VzはVz=0となることは自明である。
Further, for comparison, the counter electrode 2 is grounded without passing through the impedance circuit element Z, and a high frequency voltage having a frequency f = 13.56 [MHz] and | V | = 1.0 [kV] is applied to the application electrode 1. FIG. 8 shows the calculation result of the electric field strength distribution in the vicinity of the sample, and the electric field strength distribution immediately below the application electrode 1 (X = 0 [mm], Z = 0 [mm], region A ″), and the application electrode 1. And the central portion of the gap between the counter electrode 2 (X = 5.5 [mm], Z = 0 [mm], region B ″), and directly below the counter electrode 2 (X = 11.0 [mm], Z = 0 FIG. 9 shows a calculation graph of electric field intensity distribution in [mm], region C ″). FIGS. 8 and 9 show the calculation results obtained by the same grounding method as in the prior art. In this case, between the imprint electrode 1 and the counter electrode 2. The potential difference Vc is Vc = V, and the potential difference Vz between the counter electrode 2 and the ground potential is Vz = 0. It is clear.

図6、図7に示すように、印加電極1と対向電極2の間の絶縁体3の窪み部分には最も大きな1.47E6[V/m]の電界強度が発生していることがわかる。この時、同時
に、印加電極1、及び対向電極2の直下の試料表面近傍には各々1.7E5、1.68E5[V/m]の電界強度が発生し、更に前記窪み部分の直下の試料10の表面近傍にも0
.5E5[V/m]の電界強度が発生している。
As shown in FIGS. 6 and 7, it can be seen that the largest electric field strength of 1.47E6 [V / m] is generated in the recessed portion of the insulator 3 between the application electrode 1 and the counter electrode 2. At the same time, electric field strengths of 1.7E5 and 1.68E5 [V / m] are generated in the vicinity of the surface of the sample immediately below the application electrode 1 and the counter electrode 2, respectively, and the sample 10 immediately below the depression is formed. 0 near the surface of
. An electric field strength of 5E5 [V / m] is generated.

また、図8、9に示すように対向電極2をインピーダンス回路素子Zを介さずに接地し、印加電極1に+1.0[kV]の電圧を印加した場合は、印加電極1と対向電極2の間の絶縁体3の窪み部分には同じ7.45E5[V/m]の電界強度しか発生していない
ことがわかる。この時同時に、対向電極2の直下の試料近傍表面には0.4[V/m]の
電界強度しか発生しないが、印加電極1の直下の試料表面近傍には1.2E5[V/m]
の電界強度が発生することが分かる。
8 and 9, when the counter electrode 2 is grounded without passing through the impedance circuit element Z and a voltage of +1.0 [kV] is applied to the application electrode 1, the application electrode 1 and the counter electrode 2 are applied. It can be seen that only the same electric field strength of 7.45E5 [V / m] is generated in the recessed portion of the insulator 3 between the two. At the same time, only an electric field strength of 0.4 [V / m] is generated on the surface near the sample immediately below the counter electrode 2, but 1.2E5 [V / m] is generated on the surface near the sample immediately below the application electrode 1.
It can be seen that the electric field strength of.

この時、図1に示される第一の実施形態において、印加電極1の印加電圧Vを大きく
してゆくと、最も大きな電界強度が発生している印加電極1と対向電極2の間の絶縁体3の窪み部分に、反応ガスに応じた大気圧プラズマが発生し前記大気圧プラズマ中で発生した活性種により試料10の表面に対し成膜、加工、表面処理を行なうのであるが、この時、印加電極1と対向電極2の間の絶縁体3の窪み部分の最も高い電界強度をEp1、試料10の表面上で最も高い電界強度をEs1とすると、Ep1/Es1=1.47E6/1.7E5=8.6倍であり、また図8、9に示すように対向電極2にはインピーダンス回路素子Zを介さずに接地し、印加電極1に+1.0[kV]の電圧を印加した場合は、Ep1/Es1=7.45E5/1.2E5=6.2倍となる。
At this time, in the first embodiment shown in FIG. 1, when the applied voltage V of the applied electrode 1 is increased, the insulator between the applied electrode 1 and the counter electrode 2 generating the greatest electric field strength. The atmospheric pressure plasma corresponding to the reaction gas is generated in the hollow portion 3 and the surface of the sample 10 is formed, processed, and surface-treated by the active species generated in the atmospheric pressure plasma. Assuming that the highest electric field strength of the hollow portion of the insulator 3 between the application electrode 1 and the counter electrode 2 is Ep1, and that the highest electric field strength on the surface of the sample 10 is Es1, Ep1 / Es1 = 1.47E6 / 1.7E5. When the counter electrode 2 is grounded without the impedance circuit element Z and a voltage of +1.0 [kV] is applied to the application electrode 1, as shown in FIGS. , Ep1 / Es1 = 7.45E5 / 1 2E5 = 6.2 times to become.

これは、対向電極2がインピーダンス回路素子Zを介して接地され、且つ前記インピーダンスZがZ=−Zc/2を満たす値に設定される時、印加電極1に印加された電圧Vを
増加させると、まず第一に印加電極1と対向電極2の間の絶縁体3の窪み部分の最も高い電界強度Ep1が発生する部分でプラズマが発生し、その時の印加電極1に対する印加電圧をVbdとし、その後更に電圧を増加させると、前記電圧Vbdの8.6倍の電圧を印加電極1に印加した時に試料10の表面に大気圧プラズマが発生し、表面に損傷を与えることを示している。
This is because when the counter electrode 2 is grounded via the impedance circuit element Z and the impedance Z is set to a value satisfying Z = −Zc / 2, the voltage V applied to the application electrode 1 is increased. First, plasma is generated in a portion where the highest electric field intensity Ep1 is generated in the hollow portion of the insulator 3 between the application electrode 1 and the counter electrode 2, and the applied voltage to the application electrode 1 at that time is set to Vbd, and thereafter It is shown that when the voltage is further increased, atmospheric pressure plasma is generated on the surface of the sample 10 when the voltage 8.6 times the voltage Vbd is applied to the application electrode 1, and the surface is damaged.

一方、対向電極2がインピーダンス回路素子Zを介さず直接接地される場合、印加電極1に印加された電圧Vを増加させると、同様に印加電極1と対向電極2の間の絶縁体3の
窪み部分の最も高い電界強度Ep1が発生する部分でプラズマが発生するが、その時の印加電極1に対する印加電圧をVbdとすると、前記電圧Vbdの6.2倍の電圧を印加電極1に印加した時に試料10の表面に大気圧プラズマが発生し、表面に損傷を与えることを示している。
On the other hand, when the counter electrode 2 is directly grounded without passing through the impedance circuit element Z, if the voltage V applied to the application electrode 1 is increased, the depression of the insulator 3 between the application electrode 1 and the counter electrode 2 is similarly performed. Plasma is generated in the portion where the highest electric field strength Ep1 is generated. If the voltage applied to the application electrode 1 at that time is Vbd, the sample is applied when a voltage 6.2 times the voltage Vbd is applied to the application electrode 1. 10 shows that atmospheric pressure plasma is generated on the surface 10 and the surface is damaged.

逆に、反応ガス種、流量条件、電極ユニット5−試料10間ギャップGなどが一定であればプラズマが発生する電界強度は一定であるため、試料10の表面でプラズマが発生し試料10の表面に損傷を与える直前まで印加電極1に電圧を印加する時、対向電極2をインピーダンス回路素子Zを介さず直接接地させる方はプラズマが発生する電界強度の6.2倍の電界強度しか印加電極1と対向電極2の間の窪み部分に発生させることができないが、対向電極2をインピーダンス回路素子Zを介して接地させる場合、プラズマが発生する電界強度の8.6倍の電界強度(インピーダンス回路素子Zを介して接地させない場合の8.6/6.2=約1.4倍)を印加電極1と対向電極2の間の窪み部分に発生させることができ、高い電界強度による反応ガスの分解により、より大きな処理速度を実現することができるのである。   Conversely, if the reaction gas type, flow rate conditions, gap G between the electrode unit 5 and the sample 10 are constant, the electric field intensity generated by the plasma is constant, so that plasma is generated on the surface of the sample 10 and the surface of the sample 10 is generated. When a voltage is applied to the application electrode 1 until just before damage is applied to the electrode 1, the method in which the counter electrode 2 is directly grounded without passing through the impedance circuit element Z has an electric field strength of only 6.2 times the electric field strength generated by the plasma. However, when the counter electrode 2 is grounded via the impedance circuit element Z, the electric field intensity (impedance circuit element) is 8.6 times the electric field intensity generated by the plasma. 8.6 / 6.2 = about 1.4 times when not grounded via Z) can be generated in the hollow portion between the application electrode 1 and the counter electrode 2, and the high electric field strength By the decomposition of the reaction gas, it is possible to achieve greater processing speeds.

また、試料10の表面にプラズマが発生し試料10の表面を損傷する直前まで印加電極1に電圧を印加させず、所望のプロセス条件等から決定される電界強度を印加電極1と対向電極2の間の窪み部分に発生させた場合においても、対向電極2をインピーダンス回路素子Zを介して接地させた場合の方が、試料10の表面でプラズマが発生し試料10の表面を損傷する現象に対して安全率が高い(インピーダンス回路素子Zを介して接地させない場合の8.6/6.2=約1.4倍安全率が高い)ことを示す。   Further, the voltage is not applied to the application electrode 1 until plasma is generated on the surface of the sample 10 and the surface of the sample 10 is damaged, and the electric field strength determined from the desired process conditions and the like is set between the application electrode 1 and the counter electrode 2. Even when the counter electrode 2 is generated in the recessed portion between the two, the case where the counter electrode 2 is grounded via the impedance circuit element Z is against the phenomenon in which plasma is generated on the surface of the sample 10 and the surface of the sample 10 is damaged. The safety factor is high (8.6 / 6.2 = about 1.4 times higher safety factor when not grounded via the impedance circuit element Z).

また、上述したように、式(20)で表されるインピーダンス回路素子Zを介して対向電極2を接地させた場合、式(19)よりVc/V=2が実現され、この時印加電極1と対向電極2の間の絶縁体3の窪み部分の最も高い電界強度をEp1と、試料10の表面上で最も高い電界強度をEs1の比(Ep1/Es1)は、Ep1/Es1=8.6を達成できるが、前記Vc/Vを1.0から2.0まで変化させた場合に、図6から図9と同様の電磁界分布計算を実施し、電界強度比(Ep1/Es1)の変化を求めた結果を図10、図11に示す。   As described above, when the counter electrode 2 is grounded via the impedance circuit element Z represented by the equation (20), Vc / V = 2 is realized from the equation (19). The ratio (Ep1 / Es1) of the highest electric field strength on the surface of the sample 10 to the highest electric field strength on the surface of the sample 10 (Ep1 / Es1) is Ep1 / Es1 = 8.6. However, when the Vc / V is changed from 1.0 to 2.0, the same electromagnetic field distribution calculation as that shown in FIGS. 6 to 9 is performed to change the electric field intensity ratio (Ep1 / Es1). The results obtained are shown in FIG. 10 and FIG.

但し、この時挿入されるインピーダンス回路素子Zの値を式(6)から各々算出し、同時に式(12)、式(18)から式(12)中に示される値A、及び式(7)からVz/Vを算出し、式(12)中に示される値Aに対する依存性として示した。(但し式(12)中のθはθ=0とした。)
図10、図11中、A=1の場合、Vc=V、Vz=0、Z=0、Ep1/Es1=6.2であり、挿入するインピーダンス回路素子Zの値がZ=0であることから従来技術に示される接続方式に等しい。
また、A=0.5の場合、Vc=2V、Vz=−V、Z=−Zc/2、Ep1/Es1=8.6であり、図1、図6、図7に示される場合に等しい。
However, the value of the impedance circuit element Z inserted at this time is calculated from the equation (6), and at the same time, the value A and the equation (7) shown in the equations (12), (18) to (12). Vz / V was calculated from the above and shown as the dependency on the value A shown in the equation (12). (However, θ in the equation (12) was set to θ = 0.)
10 and 11, when A = 1, Vc = V, Vz = 0, Z = 0, Ep1 / Es1 = 6.2, and the value of the impedance circuit element Z to be inserted is Z = 0. To the connection method shown in the prior art.
In addition, when A = 0.5, Vc = 2V, Vz = −V, Z = −Zc / 2, Ep1 / Es1 = 8.6, which is the same as the case shown in FIGS. .

更に、図10、図11より分かるように値Aを0.5≦A<1の範囲で変化させることにより、式(8)、式(9)を満たすVc、Vzを実現し、更に印加電極1と対向電極2の間の絶縁体3の窪み部分の最も高い電界強度をEp1と、試料10の表面上で最も高い電界強度をEs1の比(Ep1/Es1)を、従来方式に示される接続方式の時の電界強度比(Ep1/Es1)=6.2より大きくすることができ、従って試料10の表面近傍にプラズマを発生させず、試料10の表面に損傷を与えずにより高い電界強度を印加電極1と対向電極2の間の絶縁体3の窪み部分に発生させることができ、より高い反応ガスの分解による処理速度の増大を実現できる。   Further, as can be seen from FIGS. 10 and 11, Vc and Vz satisfying the expressions (8) and (9) are realized by changing the value A in the range of 0.5 ≦ A <1, and further, the applied electrode The ratio of the highest electric field strength Ep1 and the highest electric field strength Es1 on the surface of the sample 10 (Ep1 / Es1) between the first electrode 1 and the counter electrode 2 is shown in the conventional method. The electric field strength ratio (Ep1 / Es1) at the time of the system can be made larger than 6.2, so that no plasma is generated in the vicinity of the surface of the sample 10, and a higher electric field strength is obtained without damaging the surface of the sample 10. It can be generated in the recessed portion of the insulator 3 between the application electrode 1 and the counter electrode 2, and an increase in the processing speed due to higher decomposition of the reaction gas can be realized.

上記計算結果は式(12)、式(18)におけるθ=0の場合について電界強度比(Ep1/Es1)を算出したが、θは任意の実数であっても式(12)、式(18)を満たすインピーダンス回路素子Zであれば式(8)、式(9)を満たすVc、Vzを実現し、更に電界強度比(Ep1/Es1)を従来方式に示される接続方式の時の電界強度比より大きくすることができ、従って試料10の表面近傍にプラズマを発生させず、試料10の表面に損傷を与えずにより高い電界強度を印加電極1と対向電極2の間の絶縁体3の窪み部分に発生させることができ、より高い反応ガスの分解による処理速度の増大を実現できる。
上記は図6から図9に示される計算を行った条件のみに限定されるものでなく、内部の等価回路が図2で示されるような電極ユニット5を用いる場合の全てについて当てはまる。
In the above calculation results, the electric field strength ratio (Ep1 / Es1) was calculated for θ = 0 in the equations (12) and (18). However, even if θ is an arbitrary real number, the equations (12) and (18) If the impedance circuit element Z satisfies (), Vc and Vz satisfying the equations (8) and (9) are realized, and the electric field strength ratio (Ep1 / Es1) is the electric field strength when the connection method is shown in the conventional method. Therefore, a plasma is not generated in the vicinity of the surface of the sample 10, and a higher electric field strength is obtained without damaging the surface of the sample 10. A depression of the insulator 3 between the application electrode 1 and the counter electrode 2 can be obtained. It can be generated in the portion, and an increase in processing speed due to higher decomposition of the reaction gas can be realized.
The above is not limited only to the conditions for performing the calculations shown in FIGS. 6 to 9, but applies to all cases where the internal equivalent circuit uses the electrode unit 5 as shown in FIG.

次に本発明の第2の実施形態について図12を用いて説明する。
図12は本発明の第2の実施形態を示す概略図である。
図12中、15はバリアブルコンデンサ素子、16はインダクタンス素子である。その他の構成は図1に示される第一の実施形態と同様とする。即ち、図1で示されるインピーダンス回路素子Zをバリアブルコンデンサ素子15とインダクタンス素子16の直列接続にて実現している。
Next, a second embodiment of the present invention will be described with reference to FIG.
FIG. 12 is a schematic view showing a second embodiment of the present invention.
In FIG. 12, 15 is a variable capacitor element, and 16 is an inductance element. Other configurations are the same as those of the first embodiment shown in FIG. That is, the impedance circuit element Z shown in FIG. 1 is realized by connecting the variable capacitor element 15 and the inductance element 16 in series.

以下に前記バリアブルコンデンサ素子15とインダクタンス素子16の直列接続にて式(12)、及び式(18)を満たすインピーダンスZの実現が可能であることを示す。
この時、Zcは印加電極1と対向電極2間で形成されるインピーダンスであるため、プラズマが発生していない場合は式(1)で表されるが、プラズマが発生している場合のZcは以下の式(22)で表すことができる。
Zc=R+X・j ……(22)
但しRは、R≧0の実数、またXは任意の実数。
また図12に示されるバリアブルコンデンサ素子15の容量をCv、インダクタンス素子16のインダクタンスをLvとすると、インピーダンスZは容量CvとインダクタンスLvの直列回路によって構成されている為、以下の式(23)で表すことができる。
Hereinafter, it is shown that the impedance Z satisfying the expressions (12) and (18) can be realized by connecting the variable capacitor element 15 and the inductance element 16 in series.
At this time, since Zc is an impedance formed between the application electrode 1 and the counter electrode 2, when the plasma is not generated, it is expressed by the formula (1), but when the plasma is generated, Zc is It can be represented by the following formula (22).
Zc = R + X · j (22)
However, R is a real number of R ≧ 0, and X is an arbitrary real number.
Further, assuming that the capacitance of the variable capacitor element 15 shown in FIG. 12 is Cv and the inductance of the inductance element 16 is Lv, the impedance Z is constituted by a series circuit of the capacitance Cv and the inductance Lv. Can be represented.

従って式(12)、式(22)、式(23)より Therefore, from Formula (12), Formula (22), and Formula (23)

が成り立つ。 Holds.

ここでIm[Z]はLv、Cvの調整により任意の実数を取りうることから、様々なプラズマによるR、Xに対して(A・Exp[j・θ]−1)が図5で示される領域に調整することが可能となり、強いては式(8)、式(9)で表されるVとVc、Vzの関係を実現することができる。
但しX=0の場合、つまり印加電極1と対向電極2間で形成されるインピーダンスZcが純抵抗である場合のみ、式(24)は以下の式(25)のようになり、
Here, since Im [Z] can take an arbitrary real number by adjusting Lv and Cv, (A · Exp [j · θ] −1) is shown in FIG. 5 for R and X by various plasmas. It becomes possible to adjust to the region, and for this reason, it is possible to realize the relationship between V and Vc, Vz expressed by the equations (8) and (9).
However, when X = 0, that is, only when the impedance Zc formed between the application electrode 1 and the counter electrode 2 is a pure resistance, the equation (24) becomes the following equation (25):

が成り立たなければならない。 Must hold.

つまり(A・Exp[j・θ]−1)は純虚数でなければならない。ここで式(12)、式(18)より、(A・Exp[j・θ]−1)は純虚数は取らないことから、インピーダンスZcが純抵抗である場合のみ式(8)、式(9)で表されるVとVc、Vzの関係を実現することができない。   That is, (A · Exp [j · θ] −1) must be a pure imaginary number. Here, from (12) and (18), (A · Exp [j · θ] −1) does not take a pure imaginary number, and therefore only when the impedance Zc is a pure resistance, the equations (8) and (8) The relationship between V and Vc, Vz represented by 9) cannot be realized.

しかし、前述したようにZcは印加電極1と対向電極2間で形成されるインピーダンスであり、プラズマが発生していない場合は式(1)で表され、またプラズマが発生した場合においても前記プラズマのインピーダンスを含めたインピーダンスZcが純抵抗になることは無いことから、実質的に図12で示されるインダクタンス素子16とバリアブルコンデンサ素子15の直列回路によって式(8)、式(9)で表されるVとVc、Vzの関係を実現することができる。   However, as described above, Zc is an impedance formed between the application electrode 1 and the counter electrode 2, and is expressed by the equation (1) when the plasma is not generated, and the plasma is generated even when the plasma is generated. Since the impedance Zc including the impedance does not become a pure resistance, it is expressed by the equations (8) and (9) by the series circuit of the inductance element 16 and the variable capacitor element 15 shown in FIG. The relationship between V, Vc, and Vz can be realized.

強いては電界強度比(Ep1/Es1)を従来方式に示される接続方式の時の電界強度比より大きくすることができ、従って試料10の表面近傍にプラズマを発生させず、試料10の表面に損傷を与えずにより高い電界強度を印加電極1と対向電極2の間の絶縁体3の窪み部分に発生させることができ、より高い反応ガスの分解による処理速度の増大を実現できる。   Therefore, the electric field intensity ratio (Ep1 / Es1) can be made larger than the electric field intensity ratio in the connection method shown in the conventional method, so that plasma is not generated in the vicinity of the surface of the sample 10, and the surface of the sample 10 is damaged. Thus, a higher electric field strength can be generated in the recessed portion of the insulator 3 between the application electrode 1 and the counter electrode 2, and an increase in processing speed due to higher decomposition of the reaction gas can be realized.

本発明の第1の実施形態の構成を示す概略図である。It is the schematic which shows the structure of the 1st Embodiment of this invention. 図1に示す電極ユニット内部の等価回路である。It is an equivalent circuit inside the electrode unit shown in FIG. 図2のZとZcの関係1を示す説明図である。It is explanatory drawing which shows the relationship 1 of Z and Zc of FIG. 図2のZとZcの関係2を示す説明図である。It is explanatory drawing which shows the relationship 2 of Z and Zc of FIG. 図2のZとZcの関係3を示す説明図である。It is explanatory drawing which shows the relationship 3 of Z and Zc of FIG. 図1においてインピーダンスZを挿入する場合の試料近傍の電界強度分布の計算結果である。It is a calculation result of the electric field strength distribution in the vicinity of the sample when the impedance Z is inserted in FIG. 図1においてインピーダンスZを挿入する場合の試料近傍の電界強度分布の計算グラフである。It is a calculation graph of the electric field strength distribution in the vicinity of the sample when the impedance Z is inserted in FIG. 図1においてインピーダンスZを挿入しない場合の試料近傍の電界強度分布の計算結果である。It is a calculation result of the electric field strength distribution in the vicinity of the sample when the impedance Z is not inserted in FIG. 図1においてインピーダンスZを挿入しない場合の試料近傍の電界強度分布の計算グラフである。It is a calculation graph of the electric field strength distribution in the vicinity of the sample when the impedance Z is not inserted in FIG. 電圧比Vc/V、Vz/Vの変化を示すグラフである。It is a graph which shows the change of voltage ratio Vc / V, Vz / V. 電界強度比Ep1/Es1の変化を示すグラフである。It is a graph which shows the change of electric field strength ratio Ep1 / Es1. 本発明の第2の実施形態を示す概略図である。It is the schematic which shows the 2nd Embodiment of this invention. 電極浮上型高圧浮上電極の断面図である。It is sectional drawing of an electrode floating type high voltage | pressure floating electrode. 図13の電界強度分布の計算結果である。It is a calculation result of the electric field strength distribution of FIG. 図13の電界強度分布の計算グラフである。It is a calculation graph of the electric field strength distribution of FIG.

符号の説明Explanation of symbols

1 印加電極
2 対向電極
3 絶縁体
4 接地金属筐体
5 電極ユニット
6 電力伝達線路
7 インピーダンス素子
8 電源
9 マッチングボックス
10 試料
11 反応ガス供給口
12 反応ガス排気口
13 反応ガス流
14 大気圧プラズマ
DESCRIPTION OF SYMBOLS 1 Applied electrode 2 Opposite electrode 3 Insulator 4 Ground metal housing 5 Electrode unit 6 Power transmission line 7 Impedance element 8 Power supply 9 Matching box 10 Sample 11 Reactive gas supply port 12 Reactive gas exhaust port 13 Reactive gas flow 14 Atmospheric pressure plasma

Claims (5)

電源から発生した電力が印加される印加電極と、前記印加電極に対し絶縁体を挟んで対向する対向電極とを備えた電極ユニット、および前記対向電極と接地電位間に挿入されたインピーダンス素子を備え、前記電極ユニットが試料にギャップを置いて対向し、更に前記電極ユニットと試料の間に形成される空間に局所的に反応ガスを供給し、前記印加電極に印加された電力によって前記印加電極と対向電極間にプラズマを発生させ、反応ガスに基く試料の処理を行なうプラズマ処理装置。   An electrode unit including an application electrode to which power generated from a power source is applied, a counter electrode facing the application electrode with an insulator interposed therebetween, and an impedance element inserted between the counter electrode and a ground potential The electrode unit is opposed to the sample with a gap, and a reaction gas is locally supplied to a space formed between the electrode unit and the sample, and the applied electrode is separated from the applied electrode by electric power applied to the applied electrode. A plasma processing apparatus that generates plasma between counter electrodes and processes a sample based on a reaction gas. 前記印加電極と対向電極がその間にインピーダンスZcを有し、前記インピーダンス素子のインピーダンスZはZ=Zc(A・Exp[jθ]−1)、
但し、θは任意の実数、
Aは0≦A<1、且つ0.5≦A・cosθを満たす実数
である請求項1記載のプラズマ処理装置。
The application electrode and the counter electrode have an impedance Zc therebetween, and the impedance Z of the impedance element is Z = Zc (A · Exp [jθ] −1),
Where θ is any real number,
The plasma processing apparatus according to claim 1, wherein A is a real number satisfying 0 ≦ A <1 and 0.5 ≦ A · cos θ.
前記印加電極と対向電極がその間にインピーダンスZcを有し、前記インピーダンス素子のインピーダンスZは、Z=−Zc/2である請求項1記載のプラズマ処理装置。   The plasma processing apparatus according to claim 1, wherein the application electrode and the counter electrode have an impedance Zc therebetween, and the impedance Z of the impedance element is Z = −Zc / 2. 前記印加電極と対向電極がその間にインピーダンスZcを有し、前記インピーダンス素子のインピーダンスZは、Z=j・ Im[Zc(A・Exp[jθ]−1)]
但し、θは任意の実数、
Aは0≦A<1、且つ0.5≦A・cosθを満たす実数
である請求項1記載のプラズマ処理装置。
The application electrode and the counter electrode have an impedance Zc between them, and the impedance Z of the impedance element is Z = j · Im [Zc (A · Exp [jθ] −1)]
Where θ is any real number,
The plasma processing apparatus according to claim 1, wherein A is a real number satisfying 0 ≦ A <1 and 0.5 ≦ A · cos θ.
前記インピーダンス素子は、インダクタンス素子と可変容量素子との直列回路で形成される請求項1記載のプラズマ処理装置。   The plasma processing apparatus according to claim 1, wherein the impedance element is formed of a series circuit of an inductance element and a variable capacitance element.
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WO2014083623A1 (en) * 2012-11-28 2014-06-05 株式会社日立製作所 Plasma processing device
CN113825293A (en) * 2020-06-18 2021-12-21 中国石油化工股份有限公司 Electric field enhanced plasma discharge device and method for enhancing electric field by using same

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EP1964798A2 (en) 2007-02-28 2008-09-03 Seiko Epson Corporation Medium transferring mechanism and medium processor
WO2014083623A1 (en) * 2012-11-28 2014-06-05 株式会社日立製作所 Plasma processing device
CN113825293A (en) * 2020-06-18 2021-12-21 中国石油化工股份有限公司 Electric field enhanced plasma discharge device and method for enhancing electric field by using same

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