JP2007043718A5

JP2007043718A5 -

Info

Publication number: JP2007043718A5
Application number: JP2006211487A
Authority: JP
Filing date: 2006-08-02
Publication date: 2009-08-20
Anticipated expiration: 2026-08-02

Claims

A de-serializer circuit networks, the deserializer circuitry,
A CDR network that generates multiple versions of a retime serial data signal and a recovered clock signal, wherein the recovered clock signal has a frequency that is half that of the retime serial data signal, and the multiple versions are approximately 180 A CDR network including first and second versions that are out of phase with each other;
A first register network responsive to the first version that captures the bits of the retime serial data signal in even-numbered bit positions;
And a second register network responsive to the second version for capturing the bits of the retime serial data signal in odd numbered bit positions.

First deserializer circuitry for deserializing a selectable number of consecutive bits captured by the first register circuitry;
2. The circuitry defined in claim 1 further comprising a second deserializer circuitry that deserializes a selectable number of consecutive bits captured by the second register circuitry.

The circuitry defined in claim 2 wherein the selectable number comprises 4 or 5 bits.

The deserialized bits are interleaved to restore the deserialized bits by the first and second deserializer circuitry to their original even and odd numbered bit positions in the interleaved data. The circuitry defined in claim 2 further comprising:

Further comprising circuitry for selectively deserializing two consecutive groups of the interleaved data, the circuitry for selectively deserializing:
First and second data group register circuits connected to the network, interleaved with outputs that are parallel to each other and having the outputs, wherein the first and second data group register circuits First and second data group register circuits each capable of registering and outputting one of the groups of interleaved data in parallel;
A first clock having a frequency that is a controllably selectable one of (a) a rate at which the interleaving network outputs the interleaved successive groups and (b) half of the rate A clock circuit for applying a signal to the first data group register circuit and for applying a second clock signal 180 degrees out of phase with the first clock signal to the second data group register circuit With net
5. The network of claim 4, comprising:

The circuitry defined in claim 2 further comprising dynamic reconfigurable memory circuitry that controls the selectable number.

The circuitry defined in claim 5 further comprising dynamic reconfigurable memory circuitry that controls which one of the selectable clock circuitry to select .

A de-serializer circuit networks, the deserializer circuitry,
A CDR network for generating a retime serial data signal and a recovered clock signal having a frequency that is half the bit rate of the retime serial data signal;
A frequency division network that divides the frequency of the recovered clock signal by a selectable factor to generate a relatively low frequency clock signal;
Deserializer circuitry comprising: circuitry for deserializing the retime serial data signal using the low frequency clock signal.

The circuitry defined in claim 8 further comprising dynamic reconfigurable memory circuitry that controls the selectable factors.

The circuitry defined in claim 9 wherein the selectable factor may be selected to be 4 or 5.

A de-serializer circuit networks, the deserializer circuitry,
A CDR network for generating a retime serial data signal and a recovered clock signal having a frequency that is half the bit rate of the retime serial data signal;
The recovered clock signal is used to deserialize the retime serial data signal into parallel first and second data signals without using any clock signal having a frequency higher than the frequency of the recovered clock signal. A first deserializer network;
A second deserializer network for deserializing the first data signal into a first plurality of parallel data signals;
And a third deserializer network that deserializes the second data signal into a second plurality of parallel data signals.

12. The circuitry defined in claim 11 further comprising an interleave circuitry that interleaves the first and second plurality of parallel data signals to generate a third plurality of parallel data signals.

A fourth deserializer network that selectively deserializes the third plurality of consecutive signals to generate a fourth plurality of parallel data signals, the fourth deserializer circuit network further comprising: The circuitry defined in claim 12 wherein the circuitry is alternatively operable to not deserialize the third third plurality of signals .

The circuitry defined in claim 11 wherein each of the second and third deserializer circuitry is controllable with respect to a size of the first and second plurality of parallel data signals.

The circuitry defined in claim 14 further comprising dynamic reconfigurable memory circuitry that controls the second and third deserializer circuitry.

The circuitry defined in claim 13 further comprising dynamic reconfigurable memory circuitry that controls the fourth deserializer circuitry.

12. The frequency division network further comprising dividing the frequency of the recovered clock signal by a selectable factor to generate a lower frequency signal for use of the second and third deserializer circuitry. Circuit network as described in.

The circuitry defined in claim 17 further comprising dynamic reconfigurable memory circuitry for controlling the selectable factor.