JP2007043370A - Cdma receiving circuit and processing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CDMA receiving circuit which saves electric power. <P>SOLUTION: The CDMA receiving circuit includes an effective path delay quantity comparing circuit 302 which compares an effective path delay quantity output from a path search circuit 104 with a previously input effective path delay quantity, a power ratio comparing circuit 303 which compares a desired power-to-interference ratio with a predetermined standard, a path counter circuit 304 which performs counting on the basis of the comparison result of the power ratio comparing circuit 303, and an excellent reception decision circuit 305 which compares the count value of the path counter circuit 304 with a threshold determining a standard of a frequency at which the effective path delay quantity does not vary. When it is decided that the effective path delay quantity is equal to the previously stored effective path delay quantity, when it is decided that the desired power-to-interference power ratio is within a predetermined standard range and the pulse counter circuit 304 performs addition, and when it is decided the count value of the pulse counter circuit 304 after the addition exceeds the threshold, that is reported to the path search circuit 104. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a CDMA communication circuit, and more particularly to a path search of a receiving circuit.

  2. Description of the Related Art Conventionally, a CDMA (Code Division Multiple Access) communication method widely used for mobile communication or the like transmits and spreads bit data using a spread code sequence on the transmission side, and receives it. On the side, the transmission bit data is restored by performing despreading and demodulation processing after timing synchronization on the receiving side is obtained with the spreading code sequence used on the transmitting side.

  The operation of the conventional CDMA receiver circuit will be described with reference to FIG.

  As shown in the figure, the received signal input from the receiving antenna 201 is frequency-converted by the quasi-synchronous detection circuit 202 to a frequency band that allows baseband processing.

  The frequency-converted signal is A / D converted by an A / D (Analog to Digital) converter 203, and then used by a spread signal assigned to each designated user by a path search circuit 204. A delay profile for calculating a cross-correlation value with respect to the reception delay time is calculated.

  In this way, the path search circuit 204 designates a path delay position having a high correlation with the spread code of the designated user in the path search, and designates the effective path delay amount of this valid path as the finger circuit 2051. To ~ 205n.

  The finger circuits 2051 to 205n perform correlation value calculation by despreading received data using the effective path delay amount obtained from the path search circuit 204, and output the correlation value to the demodulation circuit 206.

  In the demodulation circuit 206, the correlation value calculation result of each finger circuit 2051 to 205n is subjected to bit phase adjustment by fading and then in-phase addition is performed, and signal processing in units of slots and frames not shown is performed.

  On the other hand, the output of the demodulation circuit 206 is input to a desired power-to-interference power ratio calculation circuit 207 to calculate an SIR (Signal to Interference power Ratio) value, and a power control unit of a transmission side device (not shown). Used for.

  As power control used in such a CDMA communication system, a system using a TPC (Transmission power Control) bit is generally used.

  In this method using TPC bits, a fixed pilot bit pattern, which is a reference signal pattern, is periodically inserted into the transmission data format for transmission, and the inserted pilot bit pattern portion is despread on the receiving side. Later, the SIR value is estimated.

  If the estimated SIR value is larger than the designated reference SIR value, a TPC bit on the transmission side is generated so as to reduce the transmission power. If the estimated SIR value is smaller than the designated reference SIR value, transmission is performed. The TPC bit on the transmission side is generated so as to increase the power.

There has been proposed a wireless communication device and a wireless communication device power consumption control method for performing finger path allocation processing that reduces power consumption while maintaining good reception quality (see Patent Document 1).
JP 2001-24557 A

  However, in the conventional CDMA receiving circuit, when the distance between the base station apparatus and the mobile terminal is close, the reception quality is good, and the mobile terminal side is almost stationary (for example, good visibility using the mobile terminal) In the case of data communication with a base station apparatus having a small cell radius), since the reception delay position of the effective path does not fluctuate, the information of the effective path position output to the finger circuit is not changed by the operation of the path search circuit.

  Therefore, in such a communication environment with good reception quality, the operation of the path search circuit is not necessary, and power consumption is wasted in this good communication state.

  Therefore, an object of the present invention is to detect a case where the base station apparatus and the mobile terminal have good visibility and the mutual reception quality is good and the mobile terminal side is almost stationary, and if detected, the operation of the path search circuit is performed. It is an object of the present invention to provide a CDMA receiving circuit capable of reducing power consumption by simplification.

In order to achieve the above object, a first invention of a CDMA receiving circuit according to the present invention includes a path search circuit that calculates and outputs an effective path delay amount of a received high-frequency signal, and uses the effective path delay amount to A desired power-to-interference power ratio calculating circuit for calculating a desired power-to-interference power ratio indicating a reception state of a high-frequency signal, and a CDMA receiving circuit comprising:
An effective path delay amount comparison circuit that inputs the effective path delay amount and compares the effective path delay amount with an already input effective path delay amount;
A power ratio comparison circuit that compares the desired power-to-interference power ratio with a desired power-to-interference power ratio reference that is a reference for a predetermined reception state of a high-frequency signal;
A pass counter circuit for counting based on the comparison result of the power ratio comparison circuit;
A reception goodness determination circuit that compares a count value of the path counter circuit with a path stability criterion that is a predetermined criterion indicating that the effective path delay amount is stable, and
The effective path delay amount comparison circuit determines that the effective path delay amount and the already input effective path delay amount are equal,
The power ratio comparison circuit determines that the desired power to interference power ratio is within a range of the desired power to interference power ratio reference;
After the count value of the pass counter circuit is added,
When the reception goodness determination circuit determines that the count value after addition of the path counter circuit is equal to or greater than the path stability reference, the reception goodness determination circuit sends the path search circuit to the reception goodness determination circuit. It is a CDMA receiving circuit that notifies the determination result.

A second invention is the CDMA receiver circuit according to the first invention, wherein:
A path stability determination circuit that compares a count value of the path counter circuit with the path stability reference;
A temporary reception counter circuit for counting based on a comparison result of the path stability determination circuit;
A temporary reception determination circuit that compares a count value of the temporary reception counter circuit with a temporary reception criterion indicating a predetermined criterion of instability of a temporary reception state, and
The power ratio comparison circuit determines that the desired power to interference power ratio is out of a range of the desired power to interference power ratio reference;
The path stability determination circuit determines that the count value of the path counter circuit is greater than or equal to the path stability reference;
After the count value of the temporary reception counter circuit is added,
When the temporary reception determination circuit determines that the count value after addition of the temporary reception counter circuit is smaller than the temporary reception reference, the temporary reception determination circuit sends the path search circuit to the temporary reception determination circuit. The determination result is notified.

A third invention calculates a path search circuit that calculates and outputs an effective path delay amount of a received high-frequency signal, and calculates a desired power-to-interference power ratio indicating a reception state of the high-frequency signal using the effective path delay amount. A processing method of a CDMA receiving circuit having a desired power to interference power ratio calculating circuit,
Inputting the effective path delay amount, and comparing the effective path delay amount with an already input effective path delay amount;
Comparing the desired power-to-interference power ratio with a desired power-to-interference power ratio reference that is a reference for a predetermined reception state of a high-frequency signal;
Counting based on a comparison result between the desired power to interference power ratio and the desired power to interference power ratio reference;
Comparing the count value of the path counter circuit with a path stability criterion, which is a predetermined criterion indicating that the effective path delay amount is stable,
It is determined that the effective path delay amount is equal to the already input effective path delay amount,
The desired power to interference power ratio is determined to be within the range of the desired power to interference power ratio reference;
After the count value is added,
When the count value after the addition is determined to be greater than or equal to the path stability criterion, the processing method of the CDMA receiving circuit notifies the path search circuit to that effect.

  Since the CDMA receiver circuit is usually used in mobile communication, the reception state is not improved because the distance between the transmission side and the reception side always changes, or fading occurs between the transmission side and the reception side. A stable state occurs.

  In order to ensure stable reception even under these bad conditions, the CDMA reception circuit has a path search function that always performs path monitoring.

  However, this path search is not always necessary. When the mobile terminal such as a mobile phone and the base station of this mobile terminal talk are in a state of good propagation of radio waves, and the mobile phone user is walking or stopped, the effective path delay amount in this space There is often little change in.

  The CDMA receiver circuit of the present invention is provided with an effective path delay amount comparison circuit for detecting the presence or absence of such a change in the effective path delay amount. Furthermore, when the change in the effective path delay amount is equal to the previous reception, the number of times that the desired power to interference power ratio is determined to be within the reference range by comparing with a predetermined desired power to interference power ratio reference Is counted by a pass counter circuit.

  If the counted number is equal to or greater than a predetermined reference number, it is understood that the reception state in the CDMA receiving circuit is stable and there is no change in the effective path delay amount. There is no need to perform a search, or a simple path search can be performed to obtain a stable reception state.

  The CDMA receiving circuit has a function of notifying the path search circuit that this simple path search is performed.

  According to the present invention, a CDMA receiver circuit capable of reducing power consumption by detecting a case where reception quality is good and the mobile terminal side is almost stationary and simplifying the operation of the path search circuit is obtained. It is done.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of a CDMA receiver circuit according to the present embodiment.

  Referring to FIG. 1, the CDMA receiver circuit of this embodiment includes an antenna 101 that receives a high-frequency signal transmitted from a mobile terminal, and a quasi-synchronization that converts the received high-frequency signal into a frequency band that allows baseband processing. A detection circuit 102, an A / D converter 103 for A / D converting the frequency-converted signal, and a spread signal assigned to each designated user for the A / D-converted signal for each reception delay time A path search circuit 104 that calculates a cross-correlation value and calculates and outputs an effective path delay amount, a finger circuit 1051 to 105n that calculates a correlation value by despreading received data using the effective path delay amount, and a finger circuit Based on the correlation value calculation results obtained at 1051 to 105n, demodulation circuit 106 that performs in-phase addition and demodulation, and a demodulated signal output from demodulation circuit 106 A desired power-to-interference power ratio calculation circuit 107 that calculates a desired power-to-interference power ratio indicating a reception state of a high-frequency signal and a path search control circuit 108 that controls a path search operation of the path search circuit 104 are configured. The

  The path search control circuit 108 includes an effective path delay amount comparison circuit 302 that compares the effective path delay amount input from the path search circuit 104 with the effective path delay amount obtained immediately before reception, and the desired power. A power ratio comparison circuit 303 that compares the power ratio to interference power ratio with a desired power to interference power ratio reference that is a reference for a reception state of a predetermined high-frequency signal, and a path counter that counts based on the comparison result of the power ratio comparison circuit 303 The circuit 304 and a good reception determination circuit 305 that compares the count value of the path counter circuit 304 with a path stability criterion that is a predetermined criterion indicating that the effective path delay amount is stable.

  The antenna 101 is connected to the input terminal of the quasi-synchronous detection circuit 102, the output terminal of the quasi-synchronous detection circuit 102 is connected to the input terminal of the A / D converter 103, and the output terminal of the A / D converter 103 is the path search circuit. The output terminal of the A / D converter 103 is connected to the input terminals of the finger circuits 1051 to 105n.

  The output terminal of the path search circuit 104 is connected to the input terminal of each finger circuit 1051 to 105n, the output terminal of each finger circuit 1051 to 105n is connected to the input terminal of the demodulation circuit 106, and the output terminal of the demodulation circuit is the desired power pair. The interference power ratio calculation circuit 107 is connected to the input terminal, and the desired power-to-interference power ratio calculation circuit 107 output terminal is connected to the power control means of the transmission side device (not shown).

  The output terminal of the path search circuit 104 is connected to the input terminal of the effective path delay amount comparison circuit 302, the output terminal of the effective path delay amount comparison circuit 302 is connected to the input terminal of the power ratio comparison circuit 303, and the power ratio comparison circuit 303. Are connected to the input terminal of the pass counter circuit 304, the output terminal of the pass counter circuit 304 is connected to the input terminal of the good reception determination circuit 305, and the output terminal of the good reception determination circuit 305 is connected to the path search circuit 104. Has been.

  The output terminal of the effective path delay comparison circuit 302 is connected to the path search circuit 104, the output terminal of the power ratio comparison circuit 303 is connected to the path search circuit 104, and the output terminal of the desired power to interference power ratio calculation circuit 107 is power. It is connected to the input terminal of the ratio comparison circuit 303.

  The good reception determination circuit 305 stores in advance a path stability criterion that is a criterion indicating that the effective path delay amount is stable.

  The effective path delay amount does not change when the reception state of the high-frequency signal is good and the high-frequency signal is transmitted while moving at a very low speed on the transmission side.

  Therefore, the stability at which the effective path delay amount does not change can be indicated by the number of times the effective path delay amount is received without changing.

  Therefore, a path stability criterion is set in advance as a reference value indicating the stability of the effective path delay amount with respect to the number of times the effective path delay amount is received without change, and the path stability criterion and the effective path delay amount change. The stability of the path of the high-frequency signal in the CDMA receiving circuit can be determined by comparing the number of times of reception without receiving.

  Next, the operation of the CDMA receiver circuit of this embodiment will be described in detail with reference to FIGS.

  The CDMA receiving circuit receives a high-frequency signal transmitted from a mobile terminal (not shown) by the antenna 101. The received signal input from the antenna 101 is input to the quasi-synchronous detection circuit 102, is quasi-synchronously detected by the quasi-synchronous detection circuit 102, is frequency-converted to a signal in a frequency band that can be baseband processed, and is A / D converted. Is output to the device 103.

  The frequency-converted signal input to the A / D converter 103 is A / D-converted, and then the path search circuit 104 uses a spread signal corresponding to each designated user to correspond to each reception delay time. The cross correlation value is obtained by calculation. After the cross correlation value of each reception delay time is obtained, the path search circuit 104 creates each delay profile.

  An example of the delay profile obtained by the path search circuit 104 is shown in FIG.

  As shown in the figure, the horizontal axis indicates the path delay time, and the vertical axis indicates the cross-correlation value. In the figure, a cross-correlation value corresponding to the path delay time is shown, and this is a delay profile obtained by the path search circuit 104. In the figure, a broken line indicating the effective path threshold value TH is shown.

  The path search circuit 104 designates, from the delay profile obtained in this way, a path delay position having a high correlation with the spreading code of the designated user in the path search, as an effective path.

  The effective path threshold TH is used as a reference for specifying the effective path, and the path delay time indicating the cross-correlation value exceeding the effective path threshold TH is correlated with the spread code of the specified user. It hits the path delay position with high probability.

  The path search circuit 104 outputs the effective path delay amount information as the effective path delay amount to the finger circuits 1051 to 105n.

  The finger circuits 1051 to 105n perform correlation value calculation by despreading received data using the effective path delay amount obtained from the path search circuit 104, and output the correlation value calculation result to the demodulation circuit 106.

  The output correlation value calculation result includes the influence of fading that has occurred during radio wave propagation from the mobile terminal until it is received by the antenna 101. This is a phase shift. appear.

  The demodulating circuit 106 adjusts the bit phase of the input correlation value calculation result so as to be in phase with each other, and then performs in-phase addition of the output signals of the finger circuits 1051 to 105n, thereby not-shown slot unit and frame unit signals. Output to a signal processing circuit for processing.

  On the other hand, the output of the demodulation circuit 106 is input to a desired power-to-interference power ratio calculation circuit 107, the SIR value is calculated, and this calculation result is used for the power control means of the transmission side device (not shown).

  In the power control of the transmission side device, the transmission power is decreased if the SIR value is larger than the designated reference SIR value, and the transmission power is increased if the SIR value is smaller than the designated reference SIR value. Like that.

  The effective path delay amount and the output signal of the desired power / interference power ratio calculation circuit 107 which are output signals of the path search circuit 104 are also input to the path search control circuit 108.

  The path search control circuit 108 constantly monitors the effective path delay amount input from the path search circuit 104, and the SIR value output from the desired power to interference power ratio calculation circuit 107 is long with the effective path position fixed. When the time is stable, the subsequent path search operation of the path search circuit 104 is simply performed. In other cases, a control signal for performing the normal path search operation is notified to the path search circuit 104. The path search circuit 104 performs a simple path search or a normal path search operation according to a control signal from the path search control circuit 108.

  The detailed operation of the path search control circuit 108 will be described with reference to the flowchart shown in FIG.

  FIG. 2 is a flowchart showing the operation of the path search control circuit of the CDMA receiver circuit of this embodiment.

  The effective path delay amount 1 output from the path search circuit 104 is input to the effective path delay amount comparison circuit 302 of the path search control circuit 108 (step 2011). Similarly, the effective path delay amount 2 output from the path search circuit 104 is input to the effective path delay amount comparison circuit 302 (step 2012), and the effective path delay amount n output from the path search circuit 104 is effective. This is input to the path delay amount comparison circuit 302 (step 201n).

  In the effective path delay amount comparison circuit 302, each of the input effective path delay amounts 1 to n and the effective path delay input to the effective path delay amount comparison circuit 302 and stored in the effective path delay amount comparison circuit 302 at the previous comparison. A comparison with the quantity is made (step 2502).

  As a result of comparison, when all the effective path delay amounts 1 to n are not different from the previous effective path delay amount, the comparison result of the effective path delay amount comparison circuit 302 is “YES” below step 2502 in the figure. The flow is traced and notified to the power ratio comparison circuit 303.

  As a result of the comparison, if the input effective path delay amount changes with respect to the previous effective path delay amount, the flow of No in the left side of step 2502 is followed, and the path search control circuit 108 performs the next path search operation. Notifies the path search circuit 104 to perform the normal operation (step 2509). In response to the notification from the path search control circuit 108, the path search circuit 104 performs a normal path search operation on a signal input from the A / D converter 103 next time.

  The effective path delay amount for the previous reception input to the path search control circuit 108 is stored in a memory (not shown) provided in the path search control circuit 108. After the comparison by the effective path delay amount comparison circuit 302, the stored contents of this memory are updated to the effective path delay amount input this time for the next comparison.

  Here, when the previous comparison is not performed, that is, when the effective path delay amount is input to the effective path delay amount comparison circuit 302 for the first time, it is the same as when there is a change from the previous effective path delay amount. Following the No flow on the left side of step 2502, the path search control circuit 108 notifies the path search circuit 104 so that the next path search operation is performed as a normal operation.

  Next, the power ratio comparison circuit 303 determines whether or not the SIR value, which is the calculation result of the desired power to interference power ratio calculation circuit 107, is within ± α dB with respect to a predetermined reference SIR value (step) 2503).

  As a result of the determination, if the SIR value is within ± α dB with respect to the reference SIR value, the flow of YES below step 2503 is followed, and the determination result is notified to the pass counter circuit 304.

  As a result of the determination by the power ratio comparison circuit 303, if the SIR value is not within ± α dB with respect to the reference SIR value, the flow of No in the left side of step 2503 is followed. When the SIR value is not within ± α dB, the power ratio comparison circuit 303 notifies the path search circuit 104 to perform a path search for normal operation (step 2509), and the path search circuit 104 receives this notification. The next path search operation is performed as a normal operation.

  In this case, the effective path delay amount does not change, but it means that the reception state is not stable for some reason and the reception electric field is weak.

  Next, the path counter circuit 304 adds 1 to the count value m of the path counter circuit 304 when the effective path delay amount has not changed from the previous time and the SIR value is within ± α dB with respect to the reference SIR value. (Step 2504).

  The count value m indicated by the path counter circuit 304 is an input signal of an effective path delay amount whose effective path delay amount is unchanged from the previous time and whose SIR value is within ± α dB with respect to the reference SIR value. The number of times inputted to 108 is the result of integration, and the larger the number m of times of reception, the better and more stable the reception state of the CDMA receiver circuit is.

  Next, the count value m indicated by the path counter circuit 304 is input to the good reception determination circuit 305, and a predetermined standard indicating that the effective path delay amount stored in the good reception determination circuit 305 is stable. Is compared with a path stability criterion Z that is (step 2505).

  As a result of the comparison by the good reception determination circuit 305, when the count value m is equal to or larger than the path stability criterion Z, which is a predetermined threshold value, YES in the lower part of step 2505 is set. Following the flow, the path search control circuit 108 notifies the path search circuit 104 to perform the next path search operation by a simple operation (step 2508).

  In response to the notification from the path search control circuit 108, the path search circuit 104 performs a simple path search operation on the next signal input from the A / D converter 103.

  If the count m is smaller than the path stability criterion Z as a result of the comparison by the good reception determination circuit 305, the flow of No in the left side of Step 2505 is followed, and the path search control circuit 108 performs the next path search. The operation is notified to the path search circuit 104 so as to perform the normal operation (step 2509). In response to the notification from the path search control circuit 108, the path search circuit 104 performs a normal path search operation on the next signal input from the A / D converter 103.

  The number of times m of the path counter circuit 304 counts the number of consecutive times, satisfying the condition that the effective path delay amount is unchanged from the previous time and the SIR value is within ± α dB with respect to the reference SIR value. If not, the pass counter circuit 304 is reset.

  This is because for some reason the prospects between the base station device and the mobile terminal are poor, the reception quality of the base station device and the mobile terminal is not good, or the mobile terminal side moves without being stationary. It corresponds to such a case.

  As described above, in the CDMA receiving circuit, the path search control circuit 108 constantly monitors the effective path delay amount input from the path search circuit 104. When the effective path position is fixed and the SIR value output from the desired power-to-interference power ratio calculation circuit 107 is stable for a long time, the path search operation of the subsequent path search circuit 104 is simply performed. In this case, it becomes possible to notify the path search circuit 104 of a control signal for performing a normal path search operation.

  For this reason, it is possible for the path search circuit 104 to reduce the power consumption of the CDMA receiving circuit by performing a simple path search based on the notification from the path search control circuit 108.

  Note that examples of the path search simplification operation in the path search circuit 104 include a method of calculating a delay profile by thinning out the delay amount with respect to the path search range in the path search circuit 104, or a time for the path search range. There is a method of calculating a delay profile at an interval, and the method may be selected as appropriate.

  Further, in the present embodiment, a plurality of antennas 101 for receiving are provided, each antenna 101 is provided with a quasi-synchronous detection circuit and an A / D converter, input to the path search circuit 104, and searched by the path search circuit 104 Can be realized in the same way even in a configuration having a plurality of antennas, and the same effect can be obtained.

  Such a CDMA receiving circuit can be applied to a receiving circuit of a CDMA base station apparatus or mobile terminal.

As described above, according to the present invention, the following excellent effects can be obtained.
(1) The CDMA receiving circuit is provided with detecting means for detecting a case where the reception quality between the base station apparatus and the mobile terminal is good and the mobile terminal side is almost stationary, and the path is good and stable by this detecting means. When the state is detected, the subsequent operation of the path search circuit can be simplified.
(2) By simplifying the operation of the path search circuit, the CDMA receiving circuit can reduce the power consumption for the path search operation during the time when the path search operation is not required.
(3) The CDMA receiver circuit communicates with a base station having a small cell radius in a very low-speed movement state in which the mobile station does not require stationary or frequent path search operations in a clear communication environment. In this case, the path search can be simplified, which is effective.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 4 is a block diagram showing a configuration example of the path search control circuit of the CDMA receiver circuit of this embodiment.

  Referring to the figure, the path search control circuit 408 of the present embodiment compares the count value of the path counter circuit 304 and the path stability reference Z in addition to the configuration of the path search control circuit 108 shown in FIG. A stability determination circuit 506, a temporary reception counter circuit 507 that counts based on a comparison result of the path stability determination circuit 506, and a temporary reception determination circuit 508 that compares the count value of the temporary reception counter circuit 507 with a predetermined temporary reception reference. It is configured with.

  3 is different from the path search operation control circuit 108 in FIG. 3 in that a processing circuit is added in the power ratio comparison circuit 303 when the SIR value is not within ± α dB with respect to a predetermined reference SIR value. It is.

  The output terminal of the path counter circuit 304 is connected to the input terminal of the path stability determination circuit 506, the output terminal of the path stability determination circuit 506 is connected to the input terminal of the temporary reception counter circuit 507, and the output terminal of the temporary reception counter circuit 507 is The temporary reception determination circuit 508 is connected to the input terminal, and the temporary reception determination circuit 508 is connected to the path search circuit 104 at its output terminal.

  The output terminal of the path stability determination circuit 506 is connected to the path search circuit 104, and the output terminal of the temporary reception determination circuit 508 is connected to the path search circuit 104.

  FIG. 5 is a flowchart showing the operation of the path search control circuit of the CDMA receiver circuit of this embodiment.

  As can be seen from the figure, this flowchart is different from the flowchart shown in FIG. 2 in the processing of steps 2602 to 2608 that follows the flow of No on the left side of step 2503. Here, description of the flow of the same part as the flowchart of FIG.

  It is determined whether or not the SIR value is within ± α dB with respect to a predetermined reference SIR value (step 2503). If the SIR value is not within ± αdB, the flow of No on the left side of step 2503 is followed. The path stability determination circuit 506 is notified that the SIR value is not within ± α dB.

  In this case, the effective path delay amount does not change, but it means that the reception state is not stable for some reason and the reception electric field is weak.

  When the path stability determination circuit 506 receives this notification from the power ratio comparison circuit 303, the count value m indicated by the path counter circuit 304 is input to the path stability determination circuit 506 or the number m accumulated in the path stability determination circuit 506. Is compared with a predetermined path stability criterion Z stored in the path stability determination circuit 506 (step 2606).

  As a result of the comparison by the path stability determination circuit 506, if the count value m is the same as the predetermined path stability criterion Z or larger than the path stability criterion Z, the flow of YES below step 2606 is followed. Only 1 is added to the count value p of the reception counter circuit 507 (step 2607).

  As a result of the comparison by the path stability determination circuit 506, if the count value m becomes smaller than the predetermined path stability reference Z, the flow of No in the left side of step 2606 is followed, and the path search control circuit 108 next time. The path search circuit 104 is notified to perform the path search operation in the normal operation (step 2709). In response to the notification from the path search control circuit 108, the path search circuit 104 performs a normal path search operation on the next signal input from the A / D converter 103.

  Next, the count value p indicated by the temporary reception counter circuit 507 is input to the temporary reception determination circuit 508 and is stored in the temporary reception determination circuit 508 in a temporary reception state that is a predetermined threshold value. It is compared with a temporary reception reference W indicating an unstable criterion (step 2608).

  As a result of the comparison by the temporary reception determination circuit 508, when the count value p becomes smaller than the predetermined temporary reception reference W, the flow of Yes below step 2608 is followed, and the path search control circuit 108 next time. The path search circuit 104 is notified to perform the path search operation by a simple operation. In response to the notification from the path search control circuit 108, the path search circuit 104 performs a simple path search operation on the next input signal from the A / D converter 103 (step 2708).

  As a result of the comparison by the temporary reception determination circuit 508, if the count value p is equal to or larger than the temporary reception reference W, which is a predetermined threshold value, the No. The path search control circuit 108 notifies the path search circuit 104 to perform the next path search operation in the normal operation (step 2709). In response to the notification from the path search control circuit 108, the path search circuit 104 performs a path search for normal operation on the next signal input from the A / D converter 103.

  The number of times p of the temporary reception counter circuit 507 counts the number of consecutive times, and even once satisfies the condition that the effective path delay amount does not change from the previous time and the SIR value does not satisfy the standard SIR value within ± α dB. If not, the count value p of the temporary reception counter circuit 507 is reset.

  This corresponds to a case where the prospects of the base station apparatus and the mobile terminal are deteriorated for some reason, or the reception quality of the base station apparatus and the mobile terminal is not good.

  If the temporary reception counter circuit 507 is starting to count up, the count m counted by the pass counter circuit 304 is not reset and maintains its state.

  As described above, in this embodiment, in the power ratio comparison circuit 303, even when the SIR value is not within ± α dB with respect to the predetermined reference SIR value, the simple operation of the path search is performed within a certain period. The circuit configuration is permitted.

  For this reason, for example, when the reception state is good and the mobile terminal is in a stationary state, even if the reception field is temporarily attenuated due to shadowing caused by a person passing by, the new path search operation is not performed. Without receiving, the receiving operation with the current effective path delay amount is continued. By continuing this reception operation, the stable reception state in which the reception state is good and the mobile terminal is stationary after the passage of a person is restored, and the path search can be simply performed again. In such a state, the CDMA receiving circuit can achieve an effect of reducing power consumption without performing an extra path search operation.

It is a block diagram which shows the structural example of the CDMA receiver circuit of this embodiment. It is a flowchart which shows operation | movement of the path search control circuit of the CDMA receiver circuit of this embodiment. It is a figure which shows a delay profile. FIG. 3 is a block diagram illustrating a configuration example of a CDMA receiver circuit according to the first embodiment. 3 is a flowchart illustrating an operation of a path search control circuit of the CDMA reception circuit according to the first exemplary embodiment. It is a block diagram which shows the structural example of the conventional CDMA receiver circuit.

Explanation of symbols

Reference Signs List 101 antenna 102 quasi-synchronous detection circuit 103 A / D converter 104 path search circuit 106 demodulation circuit 107 desired power-to-interference power ratio calculation circuit 108 path search control circuit 201 antenna 202 quasi-synchronous detection circuit 203 A / D converter 204 path search Circuit 206 Demodulation circuit 207 Desired power-to-interference power ratio calculation circuit 108 Path search control circuit 302 Effective path delay amount comparison circuit 303 Power ratio comparison circuit 304 Path counter circuit 305 Good reception determination circuit 506 Path stability determination circuit 507 Temporary reception counter circuit 508 Temporary reception determination circuit 1051 to 105n Finger circuit 2051 to 205n Finger circuit W Temporary reception reference Z path stability reference

Claims (3)

A path search circuit that calculates and outputs an effective path delay amount of the received high-frequency signal, and a desired power-to-interference power that calculates a desired power-to-interference power ratio indicating the reception state of the high-frequency signal using the effective path delay amount A CDMA receiving circuit having a ratio calculating circuit;
An effective path delay amount comparison circuit that inputs the effective path delay amount and compares the effective path delay amount with an already input effective path delay amount;
A power ratio comparison circuit that compares the desired power-to-interference power ratio with a desired power-to-interference power ratio reference that is a reference for a predetermined reception state of a high-frequency signal;
A pass counter circuit for counting based on the comparison result of the power ratio comparison circuit;
A reception goodness determination circuit that compares a count value of the path counter circuit with a path stability criterion that is a predetermined criterion indicating that the effective path delay amount is stable, and
The effective path delay amount comparison circuit determines that the effective path delay amount and the already input effective path delay amount are equal,
The power ratio comparison circuit determines that the desired power to interference power ratio is within a range of the desired power to interference power ratio reference;
After the count value of the pass counter circuit is added,
When the reception goodness determination circuit determines that the count value after addition of the path counter circuit is equal to or greater than the path stability reference, the reception goodness determination circuit sends the path search circuit to the reception goodness determination circuit. A CDMA receiving circuit that notifies a determination result. The CDMA receiver circuit according to claim 1,
A path stability determination circuit that compares a count value of the path counter circuit with the path stability reference;
A temporary reception counter circuit for counting based on a comparison result of the path stability determination circuit;
A temporary reception determination circuit that compares a count value of the temporary reception counter circuit with a temporary reception criterion indicating a predetermined criterion of instability of a temporary reception state, and
The power ratio comparison circuit determines that the desired power to interference power ratio is out of a range of the desired power to interference power ratio reference;
The path stability determination circuit determines that the count value of the path counter circuit is greater than or equal to the path stability reference;
After the count value of the temporary reception counter circuit is added,
When the temporary reception determination circuit determines that the count value after addition of the temporary reception counter circuit is smaller than the temporary reception reference, the temporary reception determination circuit sends the path search circuit to the temporary reception determination circuit. A CDMA receiving circuit that notifies the determination result. A path search circuit that calculates and outputs an effective path delay amount of the received high-frequency signal, and a desired power-to-interference power that calculates a desired power-to-interference power ratio indicating the reception state of the high-frequency signal using the effective path delay amount A processing method of a CDMA receiving circuit having a ratio calculating circuit,
Inputting the effective path delay amount, and comparing the effective path delay amount with an already input effective path delay amount;
Comparing the desired power-to-interference power ratio with a desired power-to-interference power ratio reference that is a reference for a predetermined reception state of a high-frequency signal;
Counting based on a comparison result between the desired power to interference power ratio and the desired power to interference power ratio reference;
Comparing the count value of the path counter circuit with a path stability criterion, which is a predetermined criterion indicating that the effective path delay amount is stable,
It is determined that the effective path delay amount is equal to the already input effective path delay amount,
The desired power to interference power ratio is determined to be within the range of the desired power to interference power ratio reference;
After the count value is added,
When it is determined that the count value after the addition is greater than or equal to the path stability criterion, the path search circuit is notified to that effect.

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