JP2007042085A - Development support program, development support device, and storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize convenience at a practical product level regarding a development support for system development. <P>SOLUTION: A menu (M32), a system display screen (V30), and a file display screen (V32) are displayed on a display section of a development support device. A selection icon (M321), an actor icon (M322), an object icon (M323), an activation icon (M324), a pipeline icon (M325), a message icon (M326), a parts icon (M327), a divergence icon (M328), an error trap icon (M329), a tag icon (M330), an input icon (M331), an output icon (M332), a copy activation icon (M333), a copy message icon (M334), and a partial magnification icon (M335) are included in the menu (M32). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a development support program, a development support apparatus, and a storage medium for a system including an electronic device or a system configured by computer software.

  Conventionally, CAD systems (computer-aided design systems) have been put into practical use in various technical fields such as small-scale electronic circuits, integrated circuits, machines, etc., and development efficiency has been improved.

  As described in Non-Patent Document 1, page 1, the complexity of integrated circuits is significantly increased compared to productivity, and the abstraction of development objects such as specifications, architectures, communications, components, tools, methods, methodologies, etc. There is a high need to increase the level. Therefore, Non-Patent Document 1 proposes a system specification description language capable of hardware / software co-design.

  In the system description language of Non-Patent Document 1, communication is described separately from computation, and the communication function and interface are described by the concept of “channel” and can be concealed.

  Similarly, the information processing apparatus disclosed in Patent Document 1 conceals the system description language for accessing the hardware model in developing SOC (SYSTEM ON CHIP) using the system description language, and develops software that does not depend on the system description language. Is possible.

Daniel D. Gajski et al., Tsuneo Kinoshita et al., “SpecC Specification Language and Methodology”, CQ Publishing, published December 20, 2000 JP 2004-220223 A

  In the system description described in Non-Patent Document 1 and Patent Document 1, the development results such as communication specifications are displayed so that both hardware developers and software developers can easily recognize them. There is no mention of convenience.

  The present invention was devised to solve such conventional problems, and aims to realize convenience at a practical product level in development support related to system development.

  The present invention is a computer-executable development support program for describing the configuration of a system, and includes an activation symbol generation step for generating an activation symbol based on the specification of a processing block inside the system, and a pair of the above-described activity A communication symbol generating step for generating a communication symbol connecting the pair of activation symbols based on a specification of communication between the activation symbols, and a connection to the activation symbol based on a specification of an input signal for the activation symbol An input signal symbol generating step for generating the input signal symbol, an output signal symbol generating step for generating an output signal symbol connected to the activation symbol based on a specification of an output signal for the activation symbol, Arrangement line thin capable of arranging one or a plurality of activation symbols on a straight line Generating a layout line symbol, generating an external element symbol based on a specification of an element external to the system connected to an activation symbol on the layout line symbol, and generating the external element symbol Program code for causing a computer to execute a display step of displaying each of the symbols, the display step arranging the activation symbols on the placement line symbol in order of processing timing in one direction of the placement line symbol. Including.

As a result, it is excellent in convenience at a practical product level, such as displaying so that both hardware developers and software developers can easily recognize them.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  The development support program according to the present invention further includes a command symbol defining step for defining, as one command symbol, a system including at least one activation symbol arranged in at least one arrangement line symbol. May be.

As a result, higher processing blocks can be defined, and assets such as system hierarchies and development results can be used more effectively.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  A development support program according to the present invention includes a command communication symbol generation step for generating a command communication symbol that connects a pair of command symbols based on a communication specification between the pair of command symbols, and an input signal for the command symbol. A command input signal symbol generation step for generating a command-and-input signal symbol connected to the command symbol based on the specification of the command, and a command-and-output connected to the command symbol based on the specification of the output signal from the command symbol. A command output signal symbol generating step for generating a signal symbol, an arrangement line symbol generating step for generating an arrangement line symbol capable of arranging one or a plurality of the command symbols on a straight line, and an activation symbol on the arrangement line symbol Connected to An external element symbol generation step for generating an external element symbol based on a specification of an element outside the system; and a display step for displaying each of the generated symbols, wherein the activation symbol on the placement line symbol is It may include a display step arranged in order of processing timing in one direction of the arrangement line symbol.

As a result, it is excellent in convenience at a practical product level, such as displaying so that both hardware developers and software developers can easily recognize them.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support program according to the present invention, for the command symbols on the same arrangement line symbol, a command symbol pair setting step for setting a first command symbol that operates first and a second command symbol that operates thereafter And defining a first signal notifying that the second command symbol is operable and is transmitted from the second command symbol to the first command symbol when the second command symbol is operable. When the first command symbol finishes its operation, it waits for the first signal and is transmitted from the first command symbol to the second command symbol. Defining a second signal to be performed.

As a result, the asynchronous processing circuit or the software representation thereof along the arrangement line can be easily configured.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support program according to the present invention, the first command symbol on the first arrangement line symbol and the command symbol on a second arrangement line symbol different from the first arrangement line symbol, A command symbol pair setting step for setting a second command symbol that operates in cooperation with the first command symbol in parallel; and when the second command symbol is operable, the second command symbol to the first command Defining a first signal sent to the symbol notifying that it is operable, and waiting for the first signal when the first command symbol starts operation, Defines a second signal transmitted from the command symbol to the second command symbol, causing the second command symbol to start operation. It may be a step.

As a result, an asynchronous processing circuit between the arrangement lines or a software expression thereof can be easily configured.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support program according to the present invention, a global operation unit generating step in which a command is processed at a timing along the arrangement line symbol, and a local operation unit in which the command symbol is processed at a timing based on communication between the command symbols. A generation step may be included, and the generation step of the global operation unit may include each step according to claim 3, and the generation step of the local operation unit may include a vertical chain generation step and / or a horizontal chain generation step.

As a result, various system configurations including both the global operating unit and the local operating unit can be realized.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support program according to the present invention, pipeline symbols that are sequentially connected by the communication symbols between the activation symbols at successive processing timings and generate pipeline symbols indicating pipeline processing between the processing block symbols And a pipe for generating a communication symbol from the activation symbol at the previous processing timing to the pipeline symbol based on the specification of the input signal to the pipeline symbol from the activation symbol at the previous processing timing. A communication symbol from the pipeline symbol to an activation symbol at a later processing timing based on a specification of an output signal from the pipeline symbol to the activation symbol at a later processing timing. Generate pipeline It may further include an output symbol generation step.

This makes it easy to describe pipeline processing.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support program according to the present invention, for a plurality of systems, a command symbol integration step for converting the common command symbol to one command symbol, and converting the common external element symbol to one external element symbol An external element symbol integration step, a communication symbol integration step for converting the common communication symbol into one communication symbol, and an integrated communication symbol so that communication equivalent to the communication symbol in the plurality of systems is performed. An arbiter generation step for generating an arbiter processing block that outputs a control signal to arbitrate communication according to, and a control signal connection step for associating the control signal of the arbiter processing block with the command symbol.

This can automatically simplify the system configuration.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  The development support program according to the present invention further includes a switching element symbol generation step for connecting the common communication symbol to a single switching element symbol for a plurality of systems, wherein the arbiter processing block includes the plurality of systems. The switching element symbol may be controlled so that communication equivalent to the communication symbol is performed.

As a result, the communication connection line can be saved in the system part constituted by hardware. In addition, the variable configuration can be simplified in the system portion configured by software.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support program according to the present invention, a step of defining a variable transferred from the first command symbol to the second command symbol in synchronization with the second signal, and the variable as the first signal Defining a connection for transmitting from a command symbol to the second command symbol; generating a communication symbol for generating a communication symbol for transmitting the variable from the first command symbol to the second command symbol; May be further provided.

As a result, the asynchronous pipeline processing circuit or its software representation can be easily configured.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support program according to the present invention, a bus generation step for generating a bus, a step of connecting a plurality of the command symbols to the bus, and an arbiter for generating an arbiter processing block for controlling communication of the command symbols to the bus A generation step and a control signal connection step for associating the control signal of the arbiter processing block with the command symbol may be further included.

This can automatically simplify the system configuration.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  The present invention is a development support apparatus for describing the configuration of a system, and includes an activation symbol generating means for generating an activation symbol based on the specification of a processing block inside the system, and communication between a pair of the activation symbols A communication symbol generating means for generating a communication symbol connecting the pair of activation symbols based on the specifications of the input signal, and an input signal symbol connected to the activation symbol based on the specifications of the input signal for the activation symbol An output signal symbol generating means for generating an output signal symbol connected to the activation symbol based on a specification of an output signal for the activation symbol, and one or more of the one or more An arrangement line symbol generating means for generating an arrangement line symbol capable of arranging activation symbols on a straight line; An external element symbol generating means for generating an external element symbol based on a specification of an element outside the system, connected to an activation symbol on the line symbol, and a display means for displaying the generated symbols. And display means for arranging the activation symbols on the arrangement line symbols in order of processing timing in one direction of the arrangement line symbols.

As a result, it is excellent in convenience at a practical product level, such as displaying so that both hardware developers and software developers can easily recognize them.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  The development support apparatus according to the present invention further comprises command symbol defining means for defining at least one system including one or more activation symbols arranged in one or more arrangement line symbols as one command symbol. May be.

As a result, higher processing blocks can be defined, and assets such as system hierarchies and development results can be used more effectively.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support apparatus according to the present invention, a command communication symbol generating means for generating a command communication symbol connecting the pair of command symbols based on a specification of communication between the pair of command symbols, and an input signal for the command symbol Command input signal symbol generation means for generating a command-and-input signal symbol connected to the command symbol based on the specification of the command, and a command-and-output connected to the command symbol based on the specification of the output signal from the command symbol Command output signal symbol generating means for generating a signal symbol, placement line symbol generating means for generating a placement line symbol capable of placing one or a plurality of the command symbols on a straight line, and an activation symbol on the placement line symbol Connected to the outside of the system An external element symbol generating means for generating an external element symbol based on a raw specification; and a display means for displaying the generated symbols, wherein the activation symbol on the placement line symbol is represented by a placement line symbol. Display means arranged in order of processing timing in one direction.

As a result, it is excellent in convenience at a practical product level, such as displaying so that both hardware developers and software developers can easily recognize them.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

In the development support apparatus according to the present invention, for the command symbols on the same arrangement line symbol, a command symbol pair setting means for setting a first command symbol that operates first and a second command symbol that operates thereafter When,
Means for defining a first signal that is operable to be transmitted from the second command symbol to the first command symbol when the second command symbol is operable; and When the first command symbol finishes operation, the second command symbol transmitted from the first command symbol to the second command symbol is waited for the first signal to start the operation. Means for defining two signals.

As a result, the asynchronous processing circuit or the software representation thereof along the arrangement line can be easily configured.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support apparatus according to the present invention, the first command symbol on the first arrangement line symbol and the command symbol on a second arrangement line symbol different from the first arrangement line symbol, Command symbol pair setting means for setting a second command symbol that operates in cooperation with the first command symbol in parallel, and when the second command symbol is operable, the second command symbol to the first command Means for defining a first signal to be sent transmitted for the symbol indicating that it is operable, and when the first command symbol starts operation, waiting for the first signal, Means for defining a second signal transmitted from the command symbol to the second command symbol and causing the second command symbol to start operation. Good.

As a result, an asynchronous processing circuit between the arrangement lines or a software expression thereof can be easily configured.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support apparatus according to the present invention, a global operating unit generating means for processing a command at a timing along the arrangement line symbol, and a local operating unit for processing the command symbol at a timing based on communication between the command symbols. 15. The generating unit of the global operating unit includes the steps according to claim 14, and the generating unit of the local operating unit includes a vertical chain generating step and / or a horizontal chain generating unit, and the vertical chain The generating means may include each means according to claim 15, and the horizontal chain generating means may include each means according to claim 16.

As a result, various system configurations including both the global operating unit and the local operating unit can be realized.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support apparatus according to the present invention, pipeline symbols that are sequentially connected by the communication symbols between the activation symbols at successive processing timings and generate pipeline symbols indicating pipeline processing between the processing block symbols And a pipe for generating a communication symbol from the activation symbol of the previous processing timing to the pipeline symbol based on the specification of the input signal to the pipeline symbol from the activation symbol of the previous processing timing A communication symbol from the pipeline symbol to an activation symbol at a later processing timing based on a specification of an output signal from the pipeline symbol to the activation symbol at a later processing timing. Generated pipeline output symbol It may further comprise forming means.

This makes it easy to describe pipeline processing.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support apparatus according to the present invention, for a plurality of systems, command symbol integration means for converting the common command symbol into one command symbol, and converting the common external element symbol into one external element symbol. External element symbol integration means, communication symbol integration means for converting the common communication symbol into one communication symbol, and communication symbols integrated so that communication equivalent to the communication symbols in the plurality of systems is performed. An arbiter generation unit that generates an arbiter processing block that outputs a control signal to arbitrate communication according to the above, and a control signal connection unit that associates the control signal of the arbiter processing block with the command symbol.

This can automatically simplify the system configuration.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  The development support apparatus according to the present invention further includes switching element symbol generation means for connecting the common communication symbol to one switching element symbol for a plurality of systems, and the arbiter processing block includes the switching element symbol in the plurality of systems. The switching element symbol may be controlled so that communication equivalent to the communication symbol is performed.

As a result, the communication connection line can be saved in the system part constituted by hardware. In addition, the variable configuration can be simplified in the system portion configured by software.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support apparatus according to the present invention, means for defining a variable transferred from the first command symbol to the second command symbol in synchronization with the second signal, and the variable as the first signal Means for defining a connection for transmitting from a command symbol to the second command symbol; communication symbol generating means for generating a communication symbol for transmitting the variable from the first command symbol to the second command symbol; May be further provided.

As a result, the asynchronous pipeline processing circuit or its software representation can be easily configured.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  In the development support apparatus according to the present invention, a bus generating means for generating a bus, a means for connecting a plurality of the command symbols to the bus, and an arbiter for generating an arbiter processing block for controlling communication of the command symbols to the bus You may provide the production | generation means and the control signal connection means which matches the control signal of the said arbiter processing block, and the said command symbol.

This can automatically simplify the system configuration.
Here, the system includes a system composed entirely of hardware, a system composed entirely of software, and a system composed of hardware and software.

  Next, preferred embodiments of the development support program and the development support apparatus according to the present invention will be described with reference to the drawings.

[Development support equipment]
1 is a block diagram showing an embodiment of a development support apparatus according to the present invention, FIG. 2 is a block diagram showing a state where the development support apparatus of FIG. 1 is connected to a plurality of networks, and FIG. 3 is a development of FIG. It is a functional block diagram of a support device.

  In FIG. 1, a development support apparatus 1000 includes a display unit 1010 such as a color LCD (liquid crystal display), and a display control unit 1012 that drives the display unit 1010 based on an image to be displayed and displays an image. The development support apparatus 1000 displays a chart (FIG. 4) for describing a system such as an electronic device.

  The display control unit 1012 is connected to a control unit 1020 configured by an interface (not shown) that controls the entire development support apparatus 1000 and inputs / outputs information to / from each block, and the control unit 1020 includes A system memory 1030, a ROM 1032 and a storage medium 1034 such as a memory card are connected. An image to be displayed on the display unit 1010 is generated by the control unit 1020, or stored in the system memory 1030, the ROM 1032, and the storage medium 1034.

  The control unit 1020 is connected to an operation input unit 1060 for various communications and operations and a timer 1080 for time measurement.

  The control unit 1020 is connected to a communication I / F 1040 for communicating with an external device by communication means such as a communication line.

  Programs and data for system description in the development support apparatus 1000 are loaded from the storage medium 1034 or downloaded by data communication.

  Further, the development support apparatus 1000 reads a system description language source code (for example, FIG. 37) in which the system is described from the storage medium 1034 or the communication I / F into the system memory 1030 and displays a chart showing the system configuration and operation. To do. The operations referred to here include electronic circuit operations of hardware and various operations resulting from the execution of software.

  As shown in FIG. 2, a plurality of development support apparatuses 1001 to 1004 are connected to a server SV through a LAN, assets such as development results are jointly used, and further remote development support apparatuses 1005 are connected via the Internet IN. 1007 may be connected to the server SV.

In FIG. 3, the control unit 1020 in the development support apparatus 1000 includes a display unit 1202, an activation symbol generation unit 1224, a communication symbol generation unit 1226, a command communication symbol generation unit 1227, and an input signal symbol generation unit together with a system memory 1030 and a ROM 1032. 1228, command input signal symbol generation means 1229, pipeline input signal symbol generation means 1264,
Output signal symbol generation means 1230, command output signal symbol generation means 12
31, pipeline output signal symbol generation means 1266, arrangement line symbol generation means 1232, external element symbol generation means 1234, pipeline symbol generation means 1236, processing block symbol definition means 1237 (including command symbol definition means 1238), configuration Element integration means 1254 (including command symbol integration means 1240, external element symbol integration means 1242 and object symbol integration means 1252), communication symbol integration means 1244, arbiter generation means (bus arbitration means) 1246, switching element symbol generation means 1248 , Global operation unit generation unit 1260, local operation unit generation unit 1262, vertical and horizontal chain realization unit (processing block pair setting unit / first signal definition unit / second signal definition unit / variable definition unit) 1250, the control signal connection means 1268, a bus generation unit 1270, functions as a command bus connection means 1272.

  As shown in FIG. 4, the system defined by the development support apparatus (for example, 1000) includes one or a plurality of global operation units GC operated by global control of the entire system, and mutual communication between the processing blocks PB1 to PB6. And one or more local operation units LC based on the control based on the above.

  6, the display unit 1010 in the development support apparatus (for example, 1000) includes a basic software menu M30 such as an OS, a menu M32 of the development support apparatus 1000, a system display screen V30, a file display screen V32, and a file name display unit M340. A creation date display part M342, a creator display part M344, a version display part M346, and a comment display part M348 are displayed. Regarding the display of the chart, the display unit 1010, the display control unit 1020, the control unit 1020, the system memory 1030, and the ROM 1032 function as the display unit 1202.

  The menu M32 includes a selection icon M321, an actor icon M322, an object icon M323, an activation icon M324, a pipeline icon M325, a message icon M326, a part icon M327, a branch icon M328, an error trap icon M329, a sticky note icon M330, an input An icon M331, an output icon M332, a copy activation icon M333, a copy message icon M334, and a partial enlargement icon M335 are included.

  As illustrated in FIG. 6B, the file display screen V32 includes a chart (for example, “chart”, “chart1”, “chart2”, “func1”, “func2”), merge parts such as a merge scenario (for example, “Merge”, “merge1”, “merge2”), error traps and conditional branches (eg, “atrap”, “branch1”, “branch2”), external variables (eg, “Globalfiles”, “gA”) If you right-click these displays with the mouse, you can edit these files.

  When the chart display is right-clicked, an icon ED1 for starting a chart editor for the chart is displayed. It is also possible to delete the chart in the icon ED1.

  When the display of the merge part is right-clicked, an icon ED2 for starting the merge part editor for the merge part is displayed. In the icon ED2, the merge scenario can be deleted.

  When an error trap or conditional branch display is right-clicked, an icon ED3 for starting an external editor is displayed. In the icon ED3, an error trap or the like can be deleted.

  When the external variable display is right-clicked, an icon ED4 for starting global variable editing is displayed. It is also possible to delete the external variable in the icon ED4.

  Regarding the definition of the global operation part GC, all the icons other than the part icon M327 can be used, and regarding the definition of the local operation part LC, the actor icon M322, the object icon M323, and the part icon M327 can be used. It is.

  As shown in FIGS. 3 and 3-1, the global operation unit GC is generated by a global operation unit generation unit 1260. The global operation unit generation unit 1260 includes a display unit 1202, a command signal symbol generation unit 1227, a command input signal symbol. The generation unit 1229, the command output signal symbol generation unit 1231, the arrangement line symbol generation unit 1232, and the external element symbol generation unit 1234 can be considered.

  Furthermore, in the definition of the local operation unit LC, as shown in FIG. 5, a table defining processing blocks, objects, vertical chains, and horizontal chains is used.

  As shown in FIGS. 3 and 3-2, the local operation unit GC is generated by the local operation unit generation unit 1260. The local operation unit generation unit 1262 includes a display unit 1202, a command signal symbol generation unit 1227, a command input signal symbol. The generation unit 1229, the command output signal symbol generation unit 1231, the arrangement line symbol generation unit 1232, the external element symbol generation unit 1234, and the vertical / horizontal chain generation unit 1250 can be considered.

  For example, the local operation unit LC of FIG. 4 includes three objects OBJ1, OBJ2, and OBJ3. The object OBJ1 includes two processing blocks PB1 and PB2, and the object OBJ2 includes three processing blocks PB3. , PB4, and PB5, and the object OBJ3 includes one processing block PB6.

  In the table of FIG. 5, for the processing block PB1, the belonging object OBJ1 and the counterpart processing block PB2 constituting the vertical chain are defined, for the processing block PB2, the belonging object OBJ1 is defined, and for the processing block PB3, the belonging object OBJ2 and horizontal The partner processing block PB6 constituting the chain is defined, the belonging object OBJ2 is defined for the processing block PB4, the partner processing block PB5 constituting the vertical chain is defined, the belonging object OBJ2 is defined for the processing block PB5, and the processing block PB6 is defined. , Belonging object OBJ3 is defined.

  The operation of the vertical chain and the horizontal chain will be described later.

  On the other hand, the global operation part GC in FIG. 4 includes, for example, four objects OBJ4, OBJ5, OBJ6, and OBJ7. The object OBJ4 includes two processing blocks PB7 and PB8, and one object OBJ5 has one. The processing block PB9 is included, the object OBJ6 includes one processing block PB10, and the object OBJ7 includes two processing blocks PB11 and PB12, which can be defined by the following operations.

  As shown in FIG. 7, when the actor icon M322 is selected by the operation input unit 1060 such as a mouse, the actor symbol 400 can be arranged on the system display screen V30. The actor symbol 400 means a person or an object (referred to as an external element symbol) or a test pattern located outside the system generated and edited on the system display screen V30, and which actor symbol is a sticky note They are distinguished by paper symbols 406 (described later), colors, and the like. The actor symbol 400 includes a doll object 402 and a lifeline (an “arrangement line symbol” in which activation and the like can be arranged on a straight line) 404 on which a processing block (an activation symbol 600 described later) and the like are arranged. The lifeline extends in the vertical direction, and the processing blocks on the lifeline are sequentially executed downward. The processing block corresponds to a processing block of an electronic circuit or a processing module of software. The processing block symbol is used not only for the definition of the global operation part but also for the definition of the local operation part.

  The actor symbol is used not only in the definition of the global operation part GC but also in the definition of the local operation part LC.

  A sticky note symbol 406 for entering various attributes can be added to the actor symbol 400 by selecting the sticky note icon M330. Since a system including an actor symbol of a test pattern itself includes an external test pattern input, it can perform a simulation alone.

  Further, after selecting the selection icon M321, by designating the actor symbol 400 by the operation input unit 1060, the object symbol 402 can be moved, changed in size, changed in attribute, and changed in the lifeline 404 length.

  The object symbol is used not only in the definition of the global operation unit GC but also in the definition of the local operation unit LC.

  Regarding generation of the actor symbol 400, the control unit 1020 functions as an external element generation unit 1234 together with the system memory 1030 and the ROM 1032.

  As shown in FIG. 8, when the object icon M322 is selected by the operation input unit 1060 such as a mouse, the object symbol 500 can be arranged on the system display screen V30. The object symbol 500 means an object existing inside the system generated and edited on the system display screen V30, and includes a rectangular object 502 and a lifeline 404. Various attributes are displayed in the object 502.

  Further, after selecting the selection icon M321, the object symbol 500 is designated by the operation input unit 1060, whereby the object 502 can be moved, changed in size, changed in attribute, changed in length of the lifeline 404, and the like.

  Regarding the generation of the lifeline 404 in the generation of the actor symbol 400 and the object symbol 500, the control unit 1020 functions as the arrangement line generation unit 1232 together with the system memory 1030 and the ROM 1032.

  As shown in FIG. 9, when the activation icon M323 is selected by the operation input unit 1060 such as a mouse, the activation symbol 600 can be arranged on the lifeline 404 on the system display screen V30. The activation symbol 600 means a processing block such as an electronic circuit block or a software module existing in the system generated and edited on the system display screen V30.

  In addition, after selecting the selection icon M321, the activation symbol 600 is designated by the operation input unit 1060, whereby the activation symbol 600 can be moved, changed in size, changed in attribute, and the like.

  The activation symbol can be selected from one that should be completed in one cycle of the system clock, one that should be completed in two or more designated cycles (n cycles), and one that is not limited in processing time. The processing is distinguished from each other, for example, blue is displayed, n-cycle processing is displayed in green, and no limit is displayed in white. The activation symbol can set whether or not to perform a pre-check.

  As shown in FIG. 41, when pre-checking is performed, first, predetermined processing is executed (step S2701), and then the process proceeds to step S2702 to determine whether or not a specified condition is satisfied. If the condition is satisfied, the process is terminated as it is. If not, the process returns to step S2701.

  Regarding generation of the activation symbol 600, the control unit 1020 functions as an activation symbol generation unit 1224 together with the system memory 1030 and the ROM 1032.

  As shown in FIG. 10, when the pipeline icon M325 is selected by the operation input unit 1060 such as a mouse, the pipeline symbol 700 can be arranged on the lifeline 404 on the system display screen V30. The pipeline symbol 700 means pipeline processing inside the system generated and edited on the system display screen V30.

  For example, when the object symbol 510, 512, 514 and the activation symbol 610, 612 on the object symbol 510, 514 are already arranged, the pipeline symbol 700 is arranged on the lifeline 404 in the center object symbol 512 and The activation symbols 610 and 612 and the pipeline symbol 700 are connected by communication symbols (message symbols 800IN and 800OUT described later). As a result, the output of the activation symbol 610 is input to the pipeline symbol 700 (pipeline input symbol 800IN), and then output from the pipeline symbol 700 (pipeline output symbol 800OUT) at a predetermined timing. Pipeline processing, such as passed to 612, may be defined. However, the pipeline timing and the like are individually defined for the message symbols 800IN and 800OUT, and the pipeline symbol 700 calls attention to the fact that the preceding and following messages should be pipelined. This makes it possible to easily execute error chucking related to pipeline processing.

  Further, after selecting the selection icon M321, the pipeline symbol 700 can be designated by the operation input unit 1060, whereby the pipeline symbol 700 can be moved, changed in size, changed in attribute, or the like.

  Regarding the generation of the pipeline symbol 700, the control unit 1020 functions as a pipeline symbol generation unit 1236 together with the system memory 1030 and the ROM 1032.

  As shown in FIG. 11, when the message icon M326 is selected, the message symbol 800 between the lifelines 410 and 420, the message symbol 810 between the activation symbols 610 and 612, the activation symbol 612 and the lifeline 410 on the system display screen V30. A message symbol 820 in between may be generated. Message symbols 800, 810, and 820 mean one-way communication between commands (described later) in the system (“communication symbol”). The direction of communication is indicated by arrows 802, 812, 822.

  A command defines a system that includes one or more activation symbols as part of an integral processing block. A system including one or a plurality of commands is defined as an integrated processing block. Regarding the command definition, the control unit 1020 functions as a command symbol defining unit 1237 together with the system memory 1030 and the ROM 1032.

Also, define a system containing multiple commands as one processing block, etc.
It is also possible to define processing blocks of higher layers sequentially, and the control unit 1020 functions as processing block symbol definition means 1238 together with the system memory 1030 and the ROM 1032 regarding the definition of processing block symbols of each layer.

  The processing block symbol definition unit 1238 is a superordinate concept of the command symbol definition unit 1237 and includes a command symbol definition unit 1237.

  Further, by selecting the message symbol 800, 810, or 820 after selecting the selection icon M321, it is possible to change message symbols, change attributes, or the like.

  The message symbol can be selected from those transmitted / received in the same cycle of the system clock and those transmitted / received in the next cycle, and is distinguished from each other by, for example, indicating the former as a dotted line and the latter as a solid line. In addition, the flag type or data type can be selected as the data format, and as additional attributes, a constant type that is repeatedly transmitted and received a specified number of times, a FOR type that repeats until the specified condition is satisfied, and repeats while the specified condition is satisfied Either WHILE type can be selected.

  The flag type message is provided with the same cycle type and the next cycle type. When the flag type message of the same cycle is input to the activation 600 or the like, the value of the message, for example, “1” or “0” is immediately determined. When the value of the message reaches a predetermined value, processing such as activation 600 is executed. On the other hand, the flag-type message of the next cycle is not transmitted until the next cycle, and the message is transmitted only after the next cycle, and the value of the message is judged on the receiving side for the message. When the value of the message reaches a predetermined value, processing such as activation 600 is executed.

  The flag-type message in the same cycle corresponds to, for example, a wire connection in an electronic circuit, and the generated data is reflected in a signal on the wire. On the other hand, the flag-type message in the next cycle corresponds to a configuration in which generated data is temporarily held by a flip-flop.

  As shown in FIG. 39, when a flag-type message of the same cycle is input, the activation 600 or the like first receives the message (step S2501) and determines whether or not the specified condition is satisfied (step S2501). S2502). If the condition is satisfied, the process is immediately executed (step S2503). If the condition is not satisfied, the process returns to step S2501. Here, steps S2501 to S2503 in FIG. 39 are expressed as step S2500.

  As shown in FIG. 40, when inputting / outputting a flag type message in the next cycle, the transmission side first waits until the next cycle (step S2601), and transmits the message when the next cycle is reached (step S2602). Next, the receiving side such as the activation 600 receives the message (step S2603), and determines whether the designated condition is satisfied (step S2604). When the condition is satisfied, the process proceeds to step S2605, and when the condition is not satisfied, the process returns to step S2603. In step S2605, processing is executed. Here, steps S2601 to S2605 in FIG. 40 are denoted as step S2600.

  It is possible to input a flag-type message 800 or the like to the activation 600 and designate a pre-check for the activation 600 to perform double conditional processing. In this case, it is possible to variously set which of the flag-type message condition and the pre-check condition is prioritized. For example, in FIG. 42, the flag-type message condition is prioritized. That is, first, flag type message processing (step S2801) is executed. Step S2801 is equivalent to step S2500 or S2600. Next, in step S2802, if the condition is satisfied, the process is terminated as it is. If not, the process returns to step S2801.

  Regarding generation of the message symbols 800, 800 IN, 800 OUT, 810, and 820, the control unit 1020 functions as a communication symbol generation unit 1226 together with the system memory 1030 and the ROM 1032. In particular, regarding generation of the message symbols 800IN and 800OUT, the control unit 1020 functions as a pipeline input signal symbol generation unit 1264 and a pipeline input signal symbol generation unit 1266 together with the system memory 1030 and the ROM 1032.

  Further, by selecting the message symbol 800, 810, or 820 after selecting the selection icon M321, it is possible to change message symbols, change attributes, or the like.

  The command defines a system including one or more activation symbols as a part of an integrated processing block, and the patterns shown in FIGS. 31 to 36 exist in the global operation unit.

  In FIG. 31, an activation symbol 600 is arranged on a lifeline 404 of an object symbol 500, and an input signal symbol 1200 (described later) and an output signal symbol 1202 (described later) are connected to the activation symbol 600. Yes.

  In FIG. 32, activation symbols 610 and 614 are arranged on the life line 410 of the actor symbol 400, and activation symbols 612 and 616 are arranged on the life line 420 of the object symbol 500. A message symbol 800 from the activation symbol 610 to the activation symbol 612 is provided between the activation symbols 610 and 612, and a message from the activation symbol 614 to the activation symbol 616 is provided between the activation symbols 614 and 616. A symbol 810 is provided.

  In FIG. 33, activation symbols 610 and 616 are arranged on the lifeline 410 of the actor symbol 400, activation symbols 612 and 618 are arranged on the lifeline 412 of the object symbol 500, and on the lifeline 414 of the actor symbol 440. Are arranged with activation symbols 614 and 620.

  A message symbol 800 from the activation symbol 610 to the activation symbol 612 is provided between the activation symbols 610 and 612, and a message from the activation symbol 612 to the activation symbol 614 is provided between the activation symbols 612 and 614. A symbol 810 is provided, a message symbol 812 from the activation symbol 616 to the activation symbol 618 is provided between the activation symbols 616 and 618, and an activation symbol 618 is activated between the activation symbols 618 and 620. A message symbol 814 is provided that points to the conversion symbol 620.

  In FIG. 34, activation symbols 610 and 616 are arranged on the life line 410 of the actor symbol 400, activation symbols 612 and 618 are arranged on the life line 412 of the object symbol 500, and on the life line 414 of the object symbol 510. Are arranged with activation symbols 614 and 620.

  A message symbol 800 from the activation symbol 610 to the activation symbol 612 is provided between the activation symbols 610 and 612, and a message from the activation symbol 612 to the activation symbol 614 is provided between the activation symbols 612 and 614. A symbol 810 is provided, a message symbol 812 from the activation symbol 616 to the activation symbol 618 is provided between the activation symbols 616 and 618, and an activation symbol 618 is activated between the activation symbols 618 and 620. A message symbol 814 is provided that points to the conversion symbol 620.

  In FIG. 35, activation symbols 610 and 616 are arranged on the lifeline 410 of the actor symbol 400, activation symbols 612 and 620 are arranged on the lifeline 412 of the object symbol 500, and on the lifeline 414 of the object symbol 510. The activation symbols 614 and 622 are arranged on the alive symbol 4, and the activation symbols 616 and 624 are arranged on the lifeline 4106 of the actor symbol 440.

  A message symbol 800 from the activation symbol 610 to the activation symbol 612 is provided between the activation symbols 610 and 612, and a message from the activation symbol 612 to the activation symbol 614 is provided between the activation symbols 612 and 614. A symbol 810 is provided, a message symbol 812 from the activation symbol 614 to the activation symbol 616 is provided between the activation symbols 614 and 616, and an activation symbol 618 is activated between the activation symbols 618 and 620. A message symbol 814 directed to the activation symbol 620 is provided, a message symbol 816 directed from the activation symbol 620 to the activation symbol 622 is provided between the activation symbols 620 and 622, and between the activation symbols 622 and 624, Activated thin Message symbols 818 going from Le 622 in the activation symbol 624 is provided.

  In FIG. 36, activation symbols 610 and 614 are arranged on the lifeline 410 of the object symbol 500, and activation symbols 612 and 616 are arranged on the lifeline 412 of the object symbol 510. A message symbol 800 from the activation symbol 610 to the activation symbol 612 is provided between the activation symbols 610 and 612, and a message from the activation symbol 614 to the activation symbol 616 is provided between the activation symbols 614 and 616. A symbol 810 is provided.

  It is also possible to define a component (a processing block for a bus component) by grouping commands including a plurality of global operation units and / or local operation units.

  As shown in FIG. 12, when the component message icon M327 is selected, a command communication symbol 900 between the commands 910 and 920 can be defined on the system display screen V30. For example, the commands 910 and 920 are arranged on the lifeline 410 of the object symbol 500 and the lifeline 412 of the actor symbol 400, respectively.

  Further, by selecting the command communication symbol 900 after selecting the selection icon M321, the command communication symbol 900 can be switched, the attribute can be changed, and the like.

  Regarding generation of the command communication symbol 900, the control unit 1020 functions as command communication symbol generation means 1227 together with the system memory 1030 and the ROM 1032.

  As shown in FIG. 13, when the branch icon M328 is selected, a conditional branch of the lifeline 410 can be defined on the system display screen V30. For example, the activation 2010 and the command 2020 are arranged on the lifeline 410, and the branch symbol 2000 is generated so as to bypass the front and rear of the command 2020.

  When the predetermined condition is satisfied, the branch symbol 2000 bypasses the lifeline 410 and the command 2020 is not executed.

  In addition, by selecting the branch symbol 2000 after selecting the selection icon M321, the branch symbol 2000 can be moved, changed in size, changed in attribute, and the like.

  As shown in FIG. 14, when the error trap icon M329 is selected, the end condition of the lifeline 410 can be defined on the system display screen V30. For example, the activation 2010 and the command 2020 are arranged on the lifeline 410, and the error trap symbol 1100 is generated so as to surround the activation 2010.

  When a predetermined condition is satisfied inside the error trap symbol 1100 (activation 2010 in FIG. 14), the processing being executed at that time is stopped and the processing set by the error trap symbol 1100 is started.

  Further, by selecting the error icon and the lap symbol 1100 after selecting the selection icon M321, the error trap symbol 1100 can be moved, changed in size, changed in attribute, and the like.

  As shown in FIG. 15, when the input signal icon M331 and the output signal icon M332 are selected, for example, activation 600 of an external variable (displayed in the external variable box 1220 in FIG. 15) on the system display screen V30. An input signal symbol 1210 and an output signal symbol 1220 may be defined. The input signal symbol 1210 and the output signal symbol 1220 can be set in a flag form and a data form similarly to the message symbol 800 and the like (FIG. 11). Further, polling can be set for the data type input signal symbol 1210 and the output signal symbol 1220, and the processing is started when the data satisfies a predetermined condition.

  When an external variable is defined, arbiters J1420 (FIG. 18), J1620 (FIG. 30), etc. are automatically generated in order to prevent data interference and collision.

  Further, by selecting the selection icon M321 and then specifying the input signal symbol 1210 and the output signal symbol 1220, the error trap symbol 1100 can be moved, changed in size, changed in attribute, and the like.

  Regarding the generation of the input signal symbol 1210 and the output signal symbol 1220, the control unit 1020 functions as the input signal symbol generation unit 1228 and the output signal symbol generation unit 1230 together with the system memory 1030 and the ROM 1032.

  Further, as shown in FIG. 38, for input / output for passing variables between commands 2400 and 2402, an input port symbol 2410 and an output port symbol 2420 are defined in the command 2400, and an input port symbol 2412 and output are output for the command 2402. The port symbol 2422 is defined, and the variable 2400X of the output port symbol 2420 and the variable of the input port symbol 2412 are made common. This makes it possible to pass variables between serial commands.

  The input port symbols 2410 and 2412 and the output port symbols 2420 and 2422 can be set in flag form and data form similarly to the message symbol 800 and the like (FIG. 11).

As described above, the system chart described by the development support apparatus 1000 is referred to as “scenario”, and the development support apparatus 1000 automatically generates a system scenario in which a plurality of scenarios are combined (referred to as “scenario merge”). Can do.
[Scenario merge (part 1)]
FIG. 16 shows a scenario JPEG_enc for JPEG encoding and a scenario JPEG_dec for JPEG decoding.

  In the scenario JPEG_enc, an actor symbol D1300 corresponding to the PCI bus, an object symbol D1310 for encoding processing, an object symbol D1320 having a frame buffer function, and an object symbol D1330 for encryption are provided.

  In the scenario JPEG_dec, an actor symbol E1300 corresponding to the PCI bus, an object symbol E1310 for encoding processing, an object symbol E1320 having a frame buffer function, and an object symbol E1330 for encryption are provided.

  A message D1340 from the lifeline D1302 to the lifeline D1312 is provided between the lifeline D1302 of the actor symbol D1300 and the lifeline D1312 of the object symbol D1310, and the message D1340 reads the data on the PCI bus. The PCI_read name is attached.

  As shown in FIG. 16B, PCI_read is a protocol for reading data from the PCI bus, and is executed by commands D1312_1 and D1312_3 on the lifeline D1302, and a command D1312_2 on the lifeline D1312. When reading data, a message of IRDY = 1 is transmitted from the command D1312_1 to the command D1312_2, and a message of TRDY = 1 is transmitted from the command D1312_2 to the command D1312_3.

The message IRDY = 1 is a command output signal symbol for the command D1312_1 and a command input signal symbol for the command D1312_2. On the other hand, the message TRDY = 1 is a command output signal symbol for the command D1312_2 and a command input signal symbol for the command D1312_3.
Regarding the generation of the command input signal symbol and the command output signal symbol, the control unit 1020 functions as the command input signal symbol generation unit 1229 and the command output signal symbol generation unit 1231 together with the system memory 1030 and the ROM 1032.

  On the lifeline D1312 of the object symbol D1310, a command D1350 for DCT processing, a command D1360 for quantization, and a D1370 for Huffman coding are sequentially arranged downward, and the data of the message D1340 is the command Processed sequentially by D1350, D1360, and D1370.

  A message D1380 is provided between the lifeline D1312 of the object symbol D1310 and the lifeline D1322 of the object symbol D1320 from the lower side of the command D1370 in the lifeline D1312 to the lifeline D1322, and the message D1380 contains a message in the frame buffer A Send_frame name meaning that data is sent is attached.

  A message D1390 from the lifeline D1322 toward the lifeline D1332 is provided between the lifeline D1322 of the object symbol D1320 and the lifeline D1332 of the object symbol D1330. Name is attached.

  A message E1340 from the lifeline E1302 to the lifeline E1312 is provided between the lifeline E1302 of the actor symbol E1300 and the lifeline E1312 of the object symbol E1310. In the message E1340, meaning that data of the PCI bus is read. The PCI_read name is attached.

  On the lifeline E1312 of the object symbol E1310, a command E1350 for Huffman decoding, a command E1360 for inverse quantization, and a command E1370 for DCT processing are sequentially arranged downward, and the data of the message E1340 is The commands E1350, E1360, and E1370 are sequentially processed.

  A message E1380 is provided between the lifeline D1312 of the object symbol E1310 and the lifeline E1322 of the object symbol E1320 from the lower side of the command E1370 in the lifeline E1312 to the lifeline E1322, and the message E1380 includes a frame buffer. A Send_frame name meaning that data is sent is attached.

  A message E1390 from the lifeline E1322 to the lifeline E1332 is provided between the lifeline E1322 of the object symbol E1320 and the lifeline E1332 of the object symbol E1330. Name is attached.

  FIG. 17 shows a scenario JPEG obtained by scenario merging the two scenarios of FIG.

  In the scenario JPEG of FIG. 17, an actor symbol J1400 corresponding to a PCI bus common to both encoding and decoding processing, object symbols D1310, D1320, E1310, E1320 similar to FIG. 16, and an actor symbol J1410 on the output side are provided. It has been.

  That is, the scenario JPEG in FIG. 17 integrates the actor symbols D1300 and E1300 in FIG. 16 into one actor symbol J1400, and integrates the object symbols D1330 and E1330 into one actor symbol J1410. It is planned. As a result of such integration, message symbols D1340 and E1340 are transmitted from common actor symbol D1300, and message symbols D1390 and E1390 are transmitted to common actor symbol J1410. Arbiter J1420 is provided for mediation of E1340 and message symbols D1390 and E1390, respectively.

  The arbiter J1420 switches between encoding and decoding, outputs the message symbol D1390 when inputting the message symbol D1340, and outputs the message symbol E1390 when inputting the message symbol E1340.

  As described above, scenario merging is a result of paying attention to processing block symbols such as common actor symbols, object symbols, commands, etc., but in order from the output side to the input side (from the final stage to the first stage) The system can be simplified by focusing on message symbols. This simplification is called “command sharing”.

  Regarding the integration of messages in the scenario merging process, the control unit 1020 functions as a communication symbol integration unit 1224 together with the system memory 1030 and the ROM 1032.

  FIG. 18 shows a scenario in which command sharing processing is further applied to the scenario of FIG. In the command sharing scenario in FIG. 18, the message symbols D1390 and E1390 of the final output in FIG. 17 are integrated into one message symbol J1390. Accordingly, the object symbols D1320 and E1320 in the frame buffer in FIG. 17 are integrated into one object symbol J1320. The object symbol J1320 is arranged on the lifeline J1322.

  This creates a simpler system scenario than FIG.

  Regarding the integration of the actor symbols D1300 and E1300 in the command sharing process, the control unit 1020, the system memory 1030, and the ROM 1032 function as an actor (external element) symbol integration unit 1242. The control unit 1020 relates to the integration of the object symbols D1320 and E1320. The system memory 1030 and the ROM 1032 function as the object symbol integration unit 1252.

  Of course, it is also possible to integrate common command symbols. In this case, the control unit 1020 functions as the command symbol integration unit 1240 together with the system memory 1030 and the ROM 1032 regarding the integration of the command symbols.

  The above integration of the actor symbol, the object symbol, and the command symbol means the integration of common system components. Hereinafter, these are collectively referred to as component integration. Regarding the integration of components, the control unit 1020 functions as a component integration unit 1254 together with the system memory 1030 and the ROM 1032.

[Scenario merge (part 2)]
19 to 29 are diagrams showing another example of scenario merging to which the local operation unit is applied.

  19 is a diagram showing two scenarios to be merged with other scenarios, FIG. 20 is a configuration diagram showing a scenario in which the two scenarios in FIG. 19 are merged, and FIG. 21 is a diagram of the merge scenario in FIG. FIG. 22 is a trace diagram showing another example of the operation of the merge scenario of FIG. 20, FIG. 23 is a flowchart showing the operation of the command CM 12 in the merge scenario of FIG. 20, and FIG. 20 is a flowchart showing the operation of the command CM 13 in the merge scenario of FIG. 20, FIG. 25 is a flowchart showing the operation of the arbiter ABT1 in the merge scenario of FIG. 20, and FIG. 26 shows an example of a common message in the two scenarios of FIG. 27 is a diagram showing a scenario in which the scenario of FIG. 26 is merged using switching elements, and FIG. 28 is a diagram of FIG. Flowchart illustrating the operation of the command CM13 in merging scenario, Figure 29 is a flowchart showing the operation of the command CM14 in merging scenario of FIG.

  Scenario SCENARIO1 has three objects Obj11, Obj12 and Obj13, and scenario SCENARIO2 has three objects Obj21, Obj22 and Obj23.

  Commands CM11 and CM12 are sequentially provided for the object Obj11, commands CM13 and CM14 are provided for the object Obj12, and a command CM15 is provided for Obj13. A message symbol MC123 is provided between the commands CM12 and CM13, and a message symbol MC145 is provided between the commands CM14 and CM15.

  The object Obj21 is provided with a command CM24, the object Obj22 is provided with commands CM22 and CM23, and the Obj23 is provided with a command CM21. A message symbol MC212 is provided between the commands CM21 and CM22, and a message symbol MC234 is provided between the commands CM23 and CM24.

  In FIG. 20, the merge scenario MSCENARIO1 has three objects Objm1, Objm2, and Objm3. The object Objm1 is provided with commands CM11, CM12, and CM24 in the objects Obj11 and Obj21. The object Objm2 is provided with commands CM13, CM14, CM22, and CM23 in the objects Obj12 and Obj22. The object Objm3 is provided with commands CM15 and CM21 in the objects Obj13 and Obj23.

  In the figure, the commands CM11 and CM12, the commands CM13 and CM14, and the commands CM22 and CM23 have a “vertical chain” dependency, and are connected by side connection lines VL1, VLK2, and VL3, respectively. , CM15 operate depending on commands CM11, CM13, CM22, respectively.

  In the merge scenario MSCENARIO1, arbiters ABT1 and ABT2 are provided. The arbiter ABT1 executes arbitration of commands CM12, CM24, CM13 and CM23, and the arbiter ABT2 executes arbitration of commands CM14, CM22, CM15 and CM21.

  The operation of the merge scenario configured as described above can be variously set by the arbiters ABT1 and ABT2. For example, the operations of the trace diagrams of FIGS. 21 and 22 are realized.

  In FIG. 21, the merge scenario MSCENARIO1 has three objects Objm1, Objm2, and Objm3. In the object Objm1, commands CM11, CM12, and CM24 are sequentially executed, in the object Objm2, commands CM13, CM22, CM23, and CM14 are sequentially executed, and in the object Objm3, commands CM21 and CM15 are sequentially executed.

  In the figure, broken lines SL1 and SL2 crossing the objects Objm1, Objm2 and Objm3 indicate delimiters that restrict the execution order of the commands, and a plurality of commands across the broken lines SL1 and SL2 are not executed simultaneously. The command is a concept higher than the activation, and the definition of the cycle of each command is complicated. Therefore, the cycle is not defined in the scenario. However, it is naturally possible to have a cycle concept at the scenario level.

  In the merge scenario trace diagram TMSCENARIO1 of FIG. 21, the command CM11 is executed in the first cycle, the commands CM12, CM13, CM21, CM22 are executed in the second cycle, and the commands CM24, CM23, CM14, CM 15 is executed.

  In this way, the corresponding commands are executed in the same order as the execution of CM11, CM12, CM13, CM14, CM15 in scenario SCENARIO1, while the execution of CM21, CM22, CM23, CM24 in scenario SCENARIO2 It can be seen that the corresponding commands are executed in the same order as and processes equivalent to the scenarios SCENARIO1 and SCENARIO2 are realized.

  In FIG. 22, the merge scenario trace diagram TMSCENARIO1 similarly includes three objects Objm1, Objm2, and Objm3. In the object Objm1, the commands CM11, CM12, and CM24 are sequentially executed. In the object Objm2, the commands CM22, CM13, CM23, and CM14 are sequentially executed. In the object Objm3, the commands CM21 and CM15 are sequentially executed.

  In the trace diagram TMSCENARIO1 of FIG. 22, commands CM11, CM22, and CM21 are executed in the first cycle, commands CM12 and CM13 are executed in the second cycle, and commands CM24, CM23, CM14, and CM15 are executed in the third cycle. Executed.

  Therefore, processing equivalent to the scenarios SCENARIO1 and SCENARIO2 is realized. In the figure, broken lines SL3 and SL4 that cross the objects Objm1, Objm2, and Objm3 indicate the delimiters that restrict the execution order of the commands, similarly to SL1 and SL2.

  As described above, the processes equivalent to the scenarios SCENARIO1 and SCENARIO2 can be realized by the merge scenario MSCENARIO1 in various modes.

  23 and 24 are flowcharts showing the operations of the commands CM12 and CM13 in the merge scenario of FIG. 20, respectively. FIG. 25 is a flowchart showing the operation of the arbiter ABT1 of FIG.

  In FIG. 23, the command CM 12 executes processing while communicating with the arbiter ABT1 by the following steps.

  Step S12001: When the command CM12 is to start processing, first, a bus use request signal req is transmitted to the arbiter ABT1, and a permission signal ack from the arbiter ABT1 is waited for.

  Step S12002: It is determined whether or not the signal ack is received, and the process waits until the signal ack is received. When the signal ack is received, the process proceeds to step S12003.

  Step S12003: The process of the command CM12 is executed, and the process proceeds to step S12004.

  Step S12004: The release of the signal req is transmitted to the arbiter ABT1, and the process proceeds to step S12005.

  Step S12005: Wait until the arbiter ABT1 releases the bus, and when the bus is released, the processing is terminated as it is.

  In FIG. 24, the command CM 13 executes processing while communicating with the arbiter ABT1 by the following steps.

  Step S12101: The command CM13 can start processing when selected as a command to be executed by the arbiter ABT1, and waits for a signal select for selection from the arbiter ABT1. The command CM 13 determines whether or not the signal select is received, and when the signal select is received, the process proceeds to step S12102.

  Step S12102: The command CM13 transmits the reception confirmation of the signal select to the arbiter ABT1, and transmits a signal using to the arbiter ABT1 in order to declare that the bus is used.

  Step S12103: Following step S12102, the process of the command CM13 is executed, and the process proceeds to step S12104.

  Step S12104: The release of the signal using is transmitted to the arbiter ABT1, and the process proceeds to step S12105.

  Step S12105: Wait until the arbiter ABT1 releases the bus, and when the bus is released, the processing is terminated as it is.

  In FIG. 25, the arbiter ABT1 causes the commands CM12 and CM13 to execute processing in the following steps.

  Step S12201: The arbiter ABT1 waits for a request signal req from any command, and when receiving a signal req from one or more commands, the process proceeds to step S1222.

  Step S12202: One of the commands that issued the signal req, for example, the command CM12 is selected, and the process proceeds to step S12203.

  Step S12203: A signal ack indicating that the request has been accepted is transmitted to the selected command, for example, the command CM12, and a signal select permitting bus use is transmitted to the command CM13 cooperating with the command CM12.

  Step S12204: After step S12203, the process waits for the end of processing of the commands CM12 and CM13, that is, release of the using signal. When the use signal is released, the process proceeds to step S12205. Otherwise, the process proceeds to step S12207.

  Step S12205: It is determined whether or not the select signal has already been released. If released, the process jumps to step S12207; otherwise, the process proceeds to step S12206.

  Step S12206: The select signal is released, and the process proceeds to step S12207.

  Step S12207: It is determined whether or not the req signal is released. When the req signal is released, the process proceeds to step S12208. Otherwise, the process returns to step S12204.

  Step S12208: The signal ack is released and the processing is terminated as it is.

  By repeating the above processing, the arbiter ABT1 sequentially permits the command to use the bus in response to the processing request, and causes the command to execute processing.

  FIG. 26 is a diagram illustrating an example of a common message in the two scenarios of FIG. 18, and FIG. 27 is a configuration diagram illustrating a scenario in which the scenario of FIG. 26 is merged using switching element symbols.

  In FIG. 26, two activation symbols AC121 and AC122 are sequentially provided in the command CM12 in the scenario SCENARIO1, and the activation symbol AC13 is provided in the command CM13. A message symbol MA11 is provided from the activation symbol AC121 toward the activation symbol AC13, and a message symbol MA12 is provided from the activation symbol AC13 toward the activation symbol AC122.

  In FIG. 19, the message symbol MC123 from the command symbol CM12 toward the command symbol CM13 corresponds to the message symbols MA11 and MA12 between the activation symbols AC121 and AC122 and the activation symbol AC13 in FIG. The message symbol MC234 from the command symbol CM23 toward the command symbol CM24 corresponds to the message symbols MA11 and MA12 between the activation symbols AC231 and AC232 and the activation symbol AC24 in FIG. Messages between command symbols are called “command messages” and correspond to a plurality of message symbols between activation symbols. The direction of the command message is set so as to go from the command symbol that outputs the req signal described in the vertical chain (FIGS. 20 to 25) to the counterpart command symbol specified by the select signal.

  On the other hand, two activation symbols AC231 and AC232 are sequentially provided in the command CM23 in the scenario SCENARIO2, and an activation symbol AC24 is provided in the command CM24. A message symbol MA11 is provided from the activation symbol AC231 toward the activation symbol AC24, and a message symbol MA12 is provided from the activation symbol AC24 toward the activation symbol AC232.

  When scenario SCENARIO1 and scenario SCENARIO2 are contrasted, message symbols MA11 and MA12 are common. Therefore, these message symbols can be switched using switching element symbols such as multiplexers and selectors, and the merge scenario MSCENARIO2 of FIG. 26 can be generated.

  In FIG. 27, commands CM12 and CM24 are connected to the input side of the switching element symbol SW241 and also connected to the output side of the switching element symbol SW242. On the other hand, the commands CM13 and CM23 are connected to the output side of the switching element symbol SW243 and also connected to the input side of the switching element symbol SW244.

  A message symbol MA11 directed from the switching element symbol SW241 to SW243 is provided between the switching element symbols SW241 and SW243, and a message symbol MA12 directed from the switching element symbol SW244 to SW242 is provided between the switching element symbols SW242 and SW244. Yes.

  Further, arbitration is executed by the arbiter ABT1 for the commands CM12, 13, 23, 24 and the switching element symbols SW241, SW242, SW243, SW244. Regarding the realization of arbitration, the control unit 1020 functions as a bus arbitration unit (arbiter generation unit) 1246 together with the system memory 1030 and the ROM 1032.

  The switching element symbol SW241 alternatively selects the command CM12 or CM24, the switching element symbol SW242 alternatively selects the command CM12 or CM24, and the switching element symbol SW243 alternatively selects the command CM13 or CM23. The switching element symbol SW244 alternatively selects the command CM13 or CM23.

  When the arbiter ABT1 selects the command CM12 by the switching element symbol SW241, the arbiter ABT1 selects the command CM13 by the switching element symbol SW243, and simultaneously executes the processes of the commands CM12 and CM13.

  When the arbiter ABT1 selects the command CM24 with the switching element symbol SW241, the arbiter ABT1 selects the command CM23 with the switching element symbol SW243, and simultaneously executes the processes of the commands CM24 and CM23.

  When the arbiter ABT1 selects the command CM24 with the switching element symbol SW242, the arbiter ABT1 selects the command CM23 with the switching element symbol SW244, and simultaneously executes the processes of the commands CM24 and CM23.

  When the arbiter ABT1 selects the command CM24 with the switching element symbol SW242, the arbiter ABT1 selects the command CM23 with the switching element symbol SW244, and simultaneously executes the processes of the commands CM24 and CM23.

  As a result, processing equivalent to the scenarios SCENARIO1 and SCENARIO2 can be executed alternatively. Regarding the generation of the switching element symbols SW241, SW242, SW243, and SW244, the control unit 1020 functions as the switching element symbol insertion unit 1248 together with the system memory 1030 and the ROM 1032.

  FIG. 28 is a flowchart showing the operation of the command CM13 of the vertical chain VL2 in the merge scenario of FIG. 20, and FIG. 29 is a flowchart showing the operation of the command CM14 in the vertical chain VL2.

  In FIG. 28, the command CM 13 executes vertical chain processing by the following steps.

  Step S12501: First, the process of the command CM13 is executed, and the process proceeds to step S12502.

  Step S12502: Waiting for a state in which variable transmission to the command CM 14 is possible. When the command CM 14 can cooperate with the command CM 13, the signal finished (first signal) in the command CM 14 is set to “0”, and in other cases, finished = 1. The command CM 13 waits for reception of the finished = 0 signal from the command CM 14, and proceeds to step S12503 when receiving the finished = 0.

  Step S12503: A signal Cndgo = 1 (second signal) for causing the command CM 14 to start processing is transmitted to the command CM 14, and the process proceeds to Step S12504.

  Step S12504: The variable Transmission signal Transgo = 1 and the processing result variable are transmitted to the command CM14, and the processing is terminated.

  In FIG. 29, the command CM 14 executes vertical chain processing by the following steps.

  Step S12601: Waiting for reception of the Cmndgo = 1 signal (second signal) from the command CM13, and if received, the process proceeds to step S12602.

  Step S12602: Finished = 0 (first signal) is set to a variable receivable state, and the process proceeds to step S12603.

  Step S12603: Waiting for reception of Transgo = 1 and variable from the command CM13. When Transgo = 1 and a variable are received, the process proceeds to step S12604.

  Step S12604: The process of the command CM14 is executed, and the process proceeds to Step S12605.

  Step S12605: The signal finished = 1 is transmitted to the command CM13, and the process is terminated.

  By configuring such a vertical chain, an asynchronous pipeline processing circuit can be easily realized. In the vertical chain, an asynchronous processing circuit that does not pass variables can be easily realized. Similarly to the vertical chain, it is possible to define a horizontal chain that is a dependency relationship between processing blocks between different objects. Processing blocks in a horizontal chain relationship operate in parallel.

  Since the operations of the other vertical chains VL1 and VL3 and the operation of the horizontal chain are the same, the description thereof is omitted.

  Regarding the realization of the vertical and horizontal chains, the control unit 1020, together with the system memory 1030 and the ROM 1032, sets a command (processing block) pair (command symbol pair setting unit) that follows and sends a finished signal (first symbol). It functions as a vertical and horizontal chain realization means 1250 including a signal definition means), a means for transmitting a Cmndgo signal (second signal definition means), and a variable definition means for defining a variable transferred between commands.

  Furthermore, as shown in FIGS. 43 to 46, for each processing block, a processing block can be generated by combining the arbitration processing shown in FIGS. 23 to 25 and the vertical chain processing shown in FIGS. 28 and 29. . Here, the entire process in FIG. 23 is referred to as step S4101, the entire process in FIG. 24 as step S4102, the entire process in FIG. 28 as step S4103, and the entire process in FIG. 29 as step S4104.

  43, when combining the processing of FIG. 23 and the processing of FIG. 28, it is first determined whether or not the processing is arbitration (step S4100), and in the case of arbitration processing, step S4101 is executed. If it is not an arbitration process, the process advances to step S4110 to determine whether the process is a vertical chain process. In the case of a vertical chain, step S34103 is executed, and then the process ends. If it is determined in step S4110 that the chain is not a vertical chain, the process ends.

  44, when combining the processing of FIG. 23 and the processing of FIG. 29, it is first determined whether or not the processing is arbitration (step S4100), and in the case of arbitration processing, step S4101 is executed. If it is not an arbitration process, the process advances to step S4110 to determine whether the process is a vertical chain process. In the case of a vertical chain, step S34104 is executed, and then the process ends. If it is determined in step S4110 that the chain is not a vertical chain, the process ends.

  45, when combining the process of FIG. 24 and the process of FIG. 28, it is first determined whether or not it is an arbitration process (step S4100), and in the case of an arbitration process, step S4102 is executed. If it is not an arbitration process, the process advances to step S4110 to determine whether the process is a vertical chain process. In the case of a vertical chain, step S34103 is executed, and then the process ends. If it is determined in step S4110 that the chain is not a vertical chain, the process ends.

  In FIG. 46, when combining the processing of FIG. 24 and the processing of FIG. 29, it is first determined whether or not it is an arbitration process (step S4100), and in the case of an arbitration process, step S4102 is executed. If it is not an arbitration process, the process advances to step S4110 to determine whether the process is a vertical chain process. In the case of a vertical chain, step S34104 is executed, and then the process ends. If it is determined in step S4110 that the chain is not a vertical chain, the process ends.

[Bus parts]
FIG. 30 shows a scenario that is automatically generated by setting a bus in advance for commands included in the two scenarios shown in FIG.

  30, in addition to the configuration similar to that in FIG. 16, a common pair of buses J1600 and J1610 are generated between the object symbols D1310 and D1630 and between the object symbols E1310 and E1630.

  Message symbol D1380 transmitted from object symbol D1310 and message symbol E1380 transmitted from object symbol E1310 are input to bus J1600. On the other hand, the message symbols message symbols D1380 and E1380 transmitted to the object symbols D1630 and E1630 are input from the bus J1610 to the object symbols D1630 and E1630. A message symbol of data Data, index Index, and control control is transmitted from the bus J1600 to J1610 between the buses J1600 and J1610.

  Further, the buses J1600 and J1610 are arbitrated by an arbiter J1620, and the arbiter J1620 performs arbitration by controlling the buses J1600 and J1610 by control signals J1624 and J1626, respectively. The arbiter J1620 is controlled by a control signal J1628 output from the control unit 1020.

  As a result, encoding and decoding are switched and executed. That is, message symbol J1640 is output when message symbol D1380 is input, and message symbol E1670 is output when message symbol E1380 is input. For this arbitration, message symbols D1380 and E1380 are also input to the arbiter J1620.

  Regarding generation of the buses J1600 and J1610, the control unit 1020 functions as a bus generation unit 1270 together with the system memory 1030 and the ROM 1032. It functions as command bus connection means 1272 together with the system memory 1030 and ROM 1032.

  Regarding bus arbitration based on the control signal J1628, that is, associating the control signal J1628 with the commands D1350 to D1370 and E1350 to E1370, the control unit 1020 functions as a control signal connection unit together with the system memory 1030 and the ROM 1032.

That is, a plurality of scenarios can be integrated by bus generation and its arbitration.
As described above, a combination of a plurality of commands by the common bus and arbiter is referred to as a “bus component”.

  FIG. 30-2 conceptually shows an example of bus parts, and two commands CM31 and CM32 are appropriately arbitrated by the arbiters AB31 and AB32. A plurality of commands CML1, CML2,... CMLn are registered in the library LIB3, and various bus components can be generated by selecting a plurality of commands and configuring the bus components. Bus parts are also registered as a library.

[Top system]
The scenario shown in FIG. 16 is applied to, for example, hardware such as an integrated circuit (referred to as “top system”) shown in FIG. 30-3.

  The top system is configured by connecting scenarios JPEG_enc, JPEG_dec, and encryption scenario 30310 to buses 30300 and 30350, and further connecting other merge scenario 30320 and memory 303030 to bus 303000.

  The scenario 30300 includes a command 30311 for reading data from the JPEG_enc command Send_data, a command 30312 for encrypting the read data, a command 30313 for writing the encrypted data to the PCI bus, and an arbiter 30314.

  The bus 30350 is connected to an off-chip (outside integrated circuit) PCI bus 303080, and the memory 30330 is connected to a CPU 30370 outside the chip (integrated circuit) via a memory IF.

  The buses 303000 and 303050 are arbitrated by the arbiter ABT 303.

  FIG. 30-4 conceptually shows the top system. Merge scenarios MSC3041, MSC3042, and MSC3043 are sequentially connected, and actor symbols 3044 and 3045 are connected to the merge scenarios MSC3041 and MSC3043.

  Merge scenarios MSC3041, MSC3042, and MSC3043 are generated by merging a plurality of scenarios as described above.

  The outline of the system design by the above development support apparatus is expressed along the steps of FIG. 47, for example.

  Step S4701: First, a global variable (external variable) is defined.

  Step S4702: Following step S4702, a command and specification model are generated, and the function model is verified. As mentioned above, the basic flow of communication and functions can be defined as multiple commands.

  Step S4703: Following step S4703, a combination of commands and a bus component are generated. As described above, the bus component is a grouping of commands and corresponds to the bus design.

  Step S4704: Following step S4703, a bus part is incorporated to generate a scenario, a specification model is generated, and function verification is performed. As described above, the scenario includes commands and bus components that describe the communication and function flow of the system.

  Step S4705: Following step S4704, a scenario is combined to generate a merge scenario, a specification model is generated, and function verification is performed.

  Step S4706: Following step S4705, merge scenarios are combined and inter-block variables are defined to generate parts for the top system, a specification model is generated, and function verification is performed.

  Step S4707: Following step S4706, specifications are divided and output for system hardware and software implementation.

  Step S4708: Following step S4707, a VHDL and RTL (Register Transmission Level) block diagram is created by the high-level synthesis tool for system hardware implementation. Furthermore, for the software implementation of the system, the software specification is compiled to generate an execution module.

  By integrating the basic flow of communication and functions from the bottom up in this way, an advanced system can be constructed, and commands, scenarios, etc. can be combined arbitrarily, so past assets can be used effectively .

  48 to 50 are block diagrams showing an example of a system development flow by the development support apparatus of FIG. 1 in correspondence with FIG.

48, a block B4701-1 (global variable definition), a block B4701-2 (global variable model generation), and a block B4701-3 (global variable specification model) corresponding to step S4701 of FIG. 47 are provided. The block B4701-2 is executed by the global variable generated by -1, and the global variable model is stored by the block B4701-3.
The generated global variable is transferred to the block corresponding to step S4702.

  As blocks corresponding to step S4702, block B4702-1 (chart (command / scenario) creation), block B4702-2 (chart diagram (bus) save), block B4702-3 (command save), block B4702-4 (block save) Specification model generation), block B4702-5 (single specification model storage), and block B4702-6 (function verification) are provided, and the global variable generated in step S4701 is passed to block B4702-1.

  In block B4702-1, commands and scenarios are created, and the created commands and scenarios are stored in blocks B4702-2 and B4702-3. In block B4702-2, buses are stored, and in block B4702-3 other commands and scenarios are stored.

In block B4702-4, a specification model is generated, and the generated specification model is stored in block B4702-5. The stored specification model is verified in block B4702-6.
The result of the function verification is fed back to the block B4702-1. The block B4702-1 corrects the command and the scenario based on the verification result.

  As blocks corresponding to step S4703, block B4703-1 (bus component creation), block B4703-2 (bus component creation), block B4703-3 (chart diagram (buses) save), block B4703-4 (bus component save) ) And the commands stored in the blocks 4702-2 and B4702-3 are transferred to the blocks B4703-1 and B470-2, respectively, and bus components are created.

  The bus parts created in block B4703-1 are saved in block B4703-3, and the bus parts created in block B4703-2 are saved in block B4703-4.

  In FIG. 49, block B4704-1 (specification model generation), block B4704-2 (bus specification model storage), block B4704-3 (specification model generation), block B4704-4 (command, corresponding to step S4704 in FIG. Scenario storage) and block B4704-5 (bus exchange) are provided, and the bus parts stored in block B4703-4 are transferred to blocks B4704-1 and B4704-3.

  Further, block B4705-1 (merge scenario parts creation), block B4705-2 (scenario merge), block B4705-3 (save merge scenario), block B4705-4 (specification model generation) corresponding to step S4705 of FIG. 47, Block B4705-5 (specify model of merge scenario), block B4705-6 (provisional top system creation), block B4705-7 (stimulus description), and block B4705-8 (functional verification) are provided and saved in block B4703-3 The global variable specification models stored in the chart diagram and block B4701-3 are transferred to blocks B4705-1 and B4705-6, respectively.

  In block B4705-1, a merge scenario part is created based on the chart, and the created scenario is passed to block B4705-2. Block B4705-2 merges scenario parts to generate a merge scenario, which is passed to block B4705-3.

  Block B4705-3 stores the merge scenario, and block B4705-4 generates a specification model based on the stored merge scenario. The specification model generated in block B4705-4 is stored in block B4705-5.

  In block B4704-1, a specification model is generated based on the bus parts, and the generated bus specification model is passed to block B4704-2 and stored in block B4704-2.

  In block B 4704-3, a specification model is generated based on the bus parts, and the generated specification model is transferred to block B 4704-4 and stored in block B 4705-4.

  The specification model stored in block B 4704-4 is appropriately replaced in block B 4704-5 and transferred to block B 4705-5.

The specification model stored in block B4705-5 is transferred to block B4705-6, and a temporary top system is created in block B4705-6. For this temporary top system, a stimulus such as a test pattern is described in block B4705-7, and functional verification is performed in block B4705-8.
The result of the function verification is fed back to the block B4705-2, and the block B4705-2 corrects the merge scenario based on the verification result.

  50, block B4706-1 (top system component generation, hierarchical storage, IO block generation, local bus generation) corresponding to step S4706 of FIG. 47, block B4706-2 (specification model of top system component), block B4706 3 (top system editing), block B4706-4 (stimulus description), block B4706-5 (functional verification, performance verification, stimulus description), block B4706-6 (functional verification, performance verification) are provided, and block B4705-5 And the global variable specification model stored in block B4701-3 are passed to block B4706-1.

  Further, a block B4707-1 (saving the top system specification model) and a block B4707-2 (specification output for mounting) corresponding to step S4707 in FIG. 47 are provided. The output is passed to block B4707-1, and the output of block B4707-1 is passed to block B4706-4.

  The block B4706-1 generates a top system component based on the specification model and the global variable specification model, and executes hierarchical storage, IO block generation, and local bus generation. The generated top system component is stored in the block B4706-2. hand over. Block B4706-1 stores the specification model of the top system component.

  The specification model of the top system part stored in block B4706-1 is transferred to block B4706-3 and edited. The top system edited in block B4706-3 is saved in block B4707-1.

In the block B4706-4, a stimulus such as a test pattern is described for the top system specification model stored in the block B4707-1, and functional verification and performance verification are performed in the block B4706-5.
In block B 4706-5, the stimulus is described for the top system component (stored in block B 4706-2) included in the top system.

  With respect to the top system output of block B4706-5, functional verification and performance verification are performed in block B4706-6, and the verification result is fed back to block B4706-1. Block B4706-1 modifies the top system based on the verification result.

  Corresponding to step S4708 of FIG. 47, block B4708-1 (HW specification model storage), block B4708-2 (high level synthesis), block B4708-3 (VHDL / RTL), block B4708-4 (SW specification model storage) , Block B4708-5 (compiled), block B4708-6 (execution module storage), and block B4708-7 (cooperative verification) are provided. In block B4707-2, the specification model of the divided top system is block B4708- 1 and block B4708-4.

  The block B4708-1 stores the divided top system specification model as a hardware specification model, and the stored specification model is synthesized at a high level in the block B4708-2. In the block B4708-3, the VHDL or RTL block is stored. Saved as

  In block B 4708-4, the specification model of the top system divided and output is saved as a software specification model. The saved specification model is compiled in block B 4708-5 and saved as an execution module in block B 4708-6. The

  The hardware system and the software system stored in block B4708-3 and block B4708-6, respectively, are collaboratively verified in block B4708-7.

  As described above, it goes without saying that the present invention is realized by hardware or software, or can be applied to the development of a system based on cooperation between the two.

It is a block diagram which shows one Example of the development assistance apparatus which concerns on this invention. It is a block diagram which shows the state which connected the development assistance apparatus of FIG. 1 to multiple networks. It is a functional block diagram of the development support apparatus of FIG. It is a block diagram which shows the global action | operation part production | generation means of FIG. It is a block diagram which shows the local action | operation part production | generation means of FIG. It is a figure which shows the example of the system defined by the development assistance apparatus of FIG. It is a figure which shows the table for defining the local action | operation part in FIG. It is a figure which shows the screen in the display part of the development assistance apparatus of FIG. It is a figure which shows the detail of the file display screen V32 in the screen of FIG. It is a figure which shows the process example of the actor in the menu of FIG. It is a figure which shows the example of a process of the object in the menu of FIG. It is a figure which shows the example of a process of activation in the menu of FIG. It is a figure which shows the example of a pipeline process in the menu of FIG. It is a figure which shows the example of a process of the message in the menu of FIG. It is a figure which shows the example of a process of the components message in the menu of FIG. It is a figure which shows the example of a branch process in the menu of FIG. It is a figure which shows the example of a process of the error trap in the menu of FIG. It is a figure which shows the example of an input and output process in the menu of FIG. It is a figure which shows two scenarios. It is a figure which shows message PCI_read in the scenario of FIG. It is a figure which shows the scenario which merged two scenarios of FIG. It is a figure which shows the scenario which command-shared the scenario of FIG. It is a figure which shows two scenarios used as the object of another scenario merge. It is a block diagram which shows the scenario which merged two scenarios of FIG. FIG. 21 is a trace diagram showing an example of operation of the merge scenario of FIG. 20. FIG. 21 is a trace diagram showing another example of the operation of the merge scenario of FIG. 20. FIG. 21 is a flowchart showing an operation of a command CM 12 in the merge scenario of FIG. 21 is a flowchart showing an operation of a command CM 13 in the merge scenario of FIG. 21 is a flowchart showing an operation of the arbiter ABT1 in the merge scenario of FIG. It is a figure which shows the example of the common message in two scenarios of FIG. It is a figure which shows the scenario which merged the scenario of FIG. 26 using the switching element. It is a flowchart which shows operation | movement of command CM13 in the merge scenario of FIG. It is a flowchart which shows operation | movement of command CM14 in the merge scenario of FIG. It is a figure which shows the scenario which carried out the bus connection of the two scenarios of FIG. It is a figure which shows the concept of a bus component. It is a figure which shows the example of the top system containing the scenario of FIG. It is a figure which shows the example of a top system notionally. It is a figure which shows the example of command components. It is a figure which shows the other example of a command component. It is a figure which shows the further another example of a command component. It is a figure which shows the further another example of a command component. It is a figure which shows the further another example of a command component. It is a figure which shows the further another example of a command component. It is a figure which shows the example of the source code of a system description language. It is a figure which shows the example of a process of input and output of a local variable. 12 is a flowchart illustrating a processing example of a flag in the same cycle in the message of FIG. 11. 12 is a flowchart illustrating a processing example of a next cycle flag in the message of FIG. 11. 10 is a flowchart illustrating an example of a precheck process in the activation of FIG. 9. 41 is a flowchart illustrating the process of FIG. 41 and the process example of FIG. 39 or 40. It is a flowchart which shows the process of the process block applied combining the process of arbitration of FIG. 23, and the process of the vertical chain of FIG. It is a flowchart which shows the process of the process block applied combining the process of arbitration of FIG. 23, and the process of the vertical chain of FIG. It is a flowchart which shows the process of the process block applied combining the process of arbitration of FIG. 24, and the process of the vertical chain of FIG. It is a flowchart which shows the process of the process block applied combining the process of arbitration of FIG. 24, and the process of the vertical chain of FIG. It is a flowchart which shows the flow of the system development by the development assistance apparatus of FIG. It is a block diagram which shows the flow of the system development by the development assistance apparatus of FIG. FIG. 49 is a block diagram showing a flow of system development following FIG. 48. It is a block diagram which shows the flow of the system development following FIG.

Explanation of symbols

1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007 Development support device 1010 Display unit 1020 Control unit 1030 System memory 1060 Operation input unit 1202 Display unit 1224 Activation symbol generation unit 1226 Communication symbol generation unit 1227 Command communication symbol generation Means 1228 Input signal symbol generating means 1229 Command input signal symbol generating means 1230 Output signal symbol generating means 1232 Arrangement line symbol generating means 1234 External element symbol generating means 1236 Pipeline symbol generating means 1237 Processing block symbol defining means 1238 Processing block symbol defining means 1240 Command symbol integration means 1242 External element symbol integration means 1244 Communication symbol integration means 124 6 Arbiter generation means 1248 Switching element symbol generation means 1250 Vertical and horizontal chain realization means 1252 Object symbol integration means 1254 Component element integration means 1260 Global operation part generation means 1262 Local operation part generation means 1264 Pipeline input signal symbol generation means 1266 Pipeline Output signal symbol generation means 1268 Control signal connection means 1270 Bus generation means 1272 Command bus connection means

Claims (23)

A development support program for describing the system configuration,
An activation symbol generation step for generating an activation symbol based on the specification of a processing block in the system;
A communication symbol generating step for generating a communication symbol connecting the pair of activation symbols based on a specification of communication between the pair of activation symbols;
An input signal symbol generation step for generating an input signal symbol connected to the activation symbol based on a specification of an input signal for the activation symbol;
An output signal symbol generation step for generating an output signal symbol connected to the activation symbol based on a specification of an output signal for the activation symbol;
An arrangement line symbol generating step for generating an arrangement line symbol capable of arranging one or a plurality of the activation symbols on a straight line;
An external element symbol generation step for generating an external element symbol based on a specification of an element outside the system connected to the activation symbol on the arrangement line symbol;
A display step for displaying the generated symbols, wherein the activation symbols on the placement line symbols are arranged in order of processing timing in one direction of the placement line symbols;
A computer-executable development support program including program code for causing a computer to execute the program. A command symbol defining step for defining, as one command symbol, a system including at least one or more activation symbols arranged in one or more arrangement line symbols;
2. The development support program according to claim 1, further comprising program code to be executed by a computer. A development support program according to claim 2,
A command communication symbol generating step for generating a command communication symbol connecting the pair of command symbols based on a specification of communication between the pair of command symbols;
A command input signal symbol generating step for generating a co-and-input signal symbol connected to the command symbol based on a specification of an input signal for the command symbol;
A command output signal symbol generation step for generating a co-and-output signal symbol connected to the command symbol based on a specification of an output signal from the command symbol;
An arrangement line symbol generating step for generating an arrangement line symbol capable of arranging one or a plurality of the command symbols on a straight line;
An external element symbol generation step for generating an external element symbol based on a specification of an element outside the system connected to the activation symbol on the arrangement line symbol;
A display step for displaying each of the generated symbols, wherein the activation symbols on the placement line symbol are arranged in order of processing timing in one direction of the placement line symbol;
A computer-executable development support program, further comprising program code for causing a computer to execute the program. A development support program according to claim 3,
A command symbol pair setting step for setting a first command symbol operating first and a second command symbol operating thereafter for the command symbols on the same placement line symbol;
Defining a first signal that is operable to be transmitted from the second command symbol to the first command symbol when the second command symbol is operable;
When the first command symbol finishes its operation, it waits for the first signal and causes the second command symbol transmitted from the first command symbol to the second command symbol to start the operation. Defining a second signal;
A computer-executable development support program, further comprising program code for causing a computer to execute the program. A development support program according to claim 3,
The first command symbol on the first placement line symbol and the command symbol on a second placement line symbol different from the first placement line symbol, in parallel with the first command symbol A command symbol pair setting step for setting a second command symbol that operates in cooperation;
Defining a first signal that is operable to be transmitted from the second command symbol to the first command symbol when the second command symbol is operable;
When the first command symbol starts operation, the second command symbol transmitted from the first command symbol to the second command symbol is started after waiting for the first signal. Defining a second signal;
A computer-executable development support program, further comprising program code for causing a computer to execute the program. 3. The development support program according to claim 2, wherein a step of generating a global operation unit in which a command is processed at a timing along the arrangement line symbol and a local processing in which the command symbol is processed at a timing based on communication between the command symbols. A program code for causing the computer to execute the generating step of the operating unit;
The step of generating the global operation unit includes the steps according to claim 3,
The generation step of the local operation unit includes a vertical chain generation step and / or a horizontal chain generation step, the vertical chain generation step includes each step according to claim 4, and the horizontal chain generation step according to claim 5. With each step,
A computer-executable development support program. A development support program according to claim 1,
A pipeline symbol generation step for generating pipeline symbols that are sequentially connected by the communication symbols between the activation symbols at successive processing timings and that indicate pipeline processing between the processing block symbols;
Pipeline input symbol generation for generating a communication symbol from the activation symbol at the previous processing timing to the pipeline symbol based on the specification of the input signal to the pipeline symbol from the activation symbol at the previous processing timing Steps,
Pipeline output symbol generation for generating a communication symbol from the pipeline symbol to an activation symbol at a later processing timing based on a specification of an output signal from the pipeline symbol to the activation symbol at a later processing timing Steps,
A computer-executable development support program, further comprising program code for causing a computer to execute the program. For multiple systems
A command symbol integration step for converting the common command symbol into one command symbol;
An external element symbol integration step for converting the common external element symbol into one external element symbol;
A communication symbol integration step of converting the common communication symbol into one communication symbol;
An arbiter generating step for generating an arbiter processing block that outputs a control signal to mediate communication by the integrated communication symbol so that communication equivalent to the communication symbol in the plurality of systems is performed;
A control signal connection step for associating the control signal of the arbiter processing block with the command symbol;
7. The computer-executable development support program according to claim 2, further comprising program code for causing a computer to execute the program. For multiple systems
Further comprising program code for causing a computer to execute a switching element symbol generation step of connecting the common communication symbol to one switching element symbol,
The arbiter processing block controls a switching element symbol so that communication equivalent to the communication symbol in the plurality of systems is performed.
A computer-executable development support program according to any one of claims 1 to 8. Defining a variable transferred from the first command symbol to the second command symbol in synchronization with the second signal;
Defining a connection to transmit the variable from the first command symbol to the second command symbol;
A communication symbol generating step for generating a communication symbol for transmitting the variable from the first command symbol to the second command symbol;
The computer-executable development support program according to any one of claims 4 to 6, further comprising program code for causing a computer to execute the program. A development support program according to claim 2,
A bus generation step for generating a bus;
Connecting a plurality of the command symbols to the bus;
An arbiter generation step for generating an arbiter processing block for controlling communication of the command symbol to the bus;
A control signal connection step for associating the control signal of the arbiter processing block with the command symbol;
A computer-executable development support program, further comprising program code for causing a computer to execute the program. A development support device for describing the configuration of a system,
An activation symbol generating means for generating an activation symbol based on the specification of a processing block in the system;
A communication symbol generating means for generating a communication symbol connecting the pair of activation symbols based on a specification of communication between the pair of activation symbols;
An input signal symbol generating means for generating an input signal symbol connected to the activation symbol based on a specification of an input signal for the activation symbol;
Output signal symbol generation means for generating an output signal symbol connected to the activation symbol based on a specification of an output signal for the activation symbol;
Arrangement line symbol generating means for generating an arrangement line symbol capable of arranging one or a plurality of the activation symbols on a straight line;
An external element symbol generating means for generating an external element symbol connected to the activation symbol on the arrangement line symbol and based on a specification of an element outside the system;
Display means for displaying the generated symbols, wherein the activation symbols on the placement line symbols are arranged in order of processing timing in one direction of the placement line symbols;
Development support device with 13. A command symbol defining means for defining, as at least one command symbol, a system including at least one activation symbol arranged in one or more arrangement line symbols. The development support apparatus described. The development support apparatus according to claim 13,
Command communication symbol generating means for generating a command communication symbol connecting the pair of command symbols based on a specification of communication between the pair of command symbols;
Command input signal symbol generation means for generating a co-and-input signal symbol connected to the command symbol based on the specification of the input signal for the command symbol;
Command output signal symbol generating means for generating a co-and-output signal symbol connected to the command symbol based on a specification of an output signal from the command symbol;
Arrangement line symbol generating means for generating an arrangement line symbol capable of arranging one or a plurality of the command symbols on a straight line;
An external element symbol generating means for generating an external element symbol connected to the activation symbol on the arrangement line symbol and based on the specification of an element outside the system;
Display means for displaying each of the generated symbols, the display means for arranging the activation symbols on the placement line symbols in order of processing timing in one direction of the placement line symbols;
Development support device with The development support apparatus according to claim 14,
Command symbol pair setting means for setting a first command symbol that operates first and a second command symbol that operates thereafter for the command symbols on the same placement line symbol;
Means for defining a first signal that is operable to be transmitted from the second command symbol to the first command symbol when the second command symbol is operable;
When the first command symbol finishes its operation, it waits for the first signal and causes the second command symbol transmitted from the first command symbol to the second command symbol to start the operation. Means for defining a second signal;
Development support device with The development support apparatus according to claim 14,
The first command symbol on the first placement line symbol and the command symbol on a second placement line symbol different from the first placement line symbol, in parallel with the first command symbol Command symbol pair setting means for setting a second command symbol that operates in cooperation;
Means for defining a first signal that is operable to be transmitted from the second command symbol to the first command symbol when the second command symbol is operable;
When the first command symbol starts operation, the second command symbol transmitted from the first command symbol to the second command symbol is started after waiting for the first signal. Means for defining a second signal;
Development support device with 14. The development support apparatus according to claim 13, wherein a global operation unit generating means for processing a command at a timing along the arrangement line symbol and a local processing for processing the command symbol at a timing based on communication between the command symbols. Comprising a generating means of the operating part,
The global actuating unit generating means includes the steps according to claim 14,
The generating means of the local actuating unit includes a vertical chain generating step and / or a horizontal chain generating means, the vertical chain generating means includes each means according to claim 15, and the horizontal chain generating means according to claim 16. A development support apparatus comprising each means. The development support apparatus according to claim 12,
Pipeline symbol generation means for generating pipeline symbols that are sequentially connected by the communication symbols between the activation symbols at successive processing timings and indicate pipeline processing between the processing block symbols;
Pipeline input symbol generation for generating a communication symbol from the activation symbol of the previous processing timing to the pipeline symbol based on the specification of the input signal to the pipeline symbol from the activation symbol of the previous processing timing Means,
Pipeline output symbol generation for generating a communication symbol from the pipeline symbol to an activation symbol at a later processing timing based on a specification of an output signal from the pipeline symbol to the activation symbol at a later processing timing Means
Further development support equipment. For multiple systems
Command symbol integration means for converting the common command symbol into one command symbol;
External element symbol integration means for converting the common external element symbol into one external element symbol;
Communication symbol integration means for converting the common communication symbol into one communication symbol;
An arbiter generating means for generating an arbiter processing block that outputs a control signal to arbitrate communication using the integrated communication symbols so that communication equivalent to the communication symbols in the plurality of systems is performed;
Control signal connection means for associating the control signal of the arbiter processing block with the command symbol;
The development support apparatus according to claim 13, further comprising: For multiple systems
Switching element symbol generating means for connecting the common communication symbol to one switching element symbol;
The arbiter processing block controls a switching element symbol so that communication equivalent to the communication symbol in the plurality of systems is performed.
The development support apparatus according to any one of claims 12 to 19, Means for defining a variable to be transferred from the first command symbol to the second command symbol in synchronization with the second signal;
Means for defining a connection to transmit the variable from the first command symbol to the second command symbol;
Communication symbol generating means for generating a communication symbol for transmitting the variable from the first command symbol to the second command symbol;
The development support apparatus according to claim 15, further comprising: The development support apparatus according to claim 13,
Bus generating means for generating a bus;
Means for connecting a plurality of the command symbols to the bus;
Arbiter generating means for generating an arbiter processing block for controlling communication of the command symbol to the bus;
Control signal connection means for associating the control signal of the arbiter processing block with the command symbol;
Development support device with A computer-readable storage medium in which the development support program according to claim 1 is stored.

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