JP2007041813A - Information processing system and information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing system with which processing efficiency can be improved. <P>SOLUTION: This information processing system 1 is provided with a buffer memory 122 connected to a memory bus 16, and mapped on a first address space for performing access to the first arithmetic means 11, a transfer means 11 for, when page fault is generated, transferring block data in a block size with a portion or whole part of a page frame as a unit to the buffer memory 122 in a batch based on the address on the first address space and an external memory control means 130 for, when the page fault is generated, transferring a page frame between external memories 140 to 143 and the buffer memory 122 based on the address mapped on the second address space. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing system and an information processing method for performing swapping processing.

  Conventionally, as an information processing apparatus called a silicon disk, a RAM disk, and an extended memory, a standard input / output bus such as a PCI bus, a standard input / output interface for a hard disk such as IDE or SCSI, and a dedicated input / output interface are used. What is connected exists as a product.

  There is a Rocket Drive of CENATEK, etc. that is mounted on the PCI bus, and there is a RST SD series of TEXA (see “Non-patent Document 1”) that is connected to the SCSI.

  There is software that can set a part of main memory such as a personal computer as a RAM disk. There are also packaged software and free software that can achieve high speed by allocating temporary files to the area.

  For example, although the capacity is severely limited, as a simple one, the MS-DOS RAMDISK. Some of them come with the OS, such as a SYS driver. Also, in Windows (registered trademark), the CENATEK RAMDiskNT and the IODATA RamPhantom, which have improved capacity restrictions and usability, correspond to this method.

  A memory module with a prefetch function is known (for example, refer to “Patent Document 1”). In this memory module, a mother board, a chip set, and a CPU can be mounted with a memory having a storage capacity that is larger than a capacity that can be originally mounted in a memory slot while using general-purpose components.

JP 2004-272576 A TEXA “RDS SD Series Leaflet” Product Catalog (2004.09.09)

  The extended memory attached to the PCI bus such as the above-mentioned CENATEK's Rocket Drive has a short delay time enough to find a merit as an alternative to the hard disk. However, it has a low bandwidth and a high delay compared to the access path to the main memory. For this reason, it is expected that there will be a significant performance degradation depending on the processing contents, as compared with the case where everything is processed on the main memory on a system having a sufficiently large main storage capacity.

  Further, in software that sets a part of the main memory as a RAM disk, a part of the main memory cannot be used as the original main memory. For this reason, it is difficult to provide too much capacity as extended storage. If you use it incorrectly, such as setting more capacity than the limit, as an extended memory, it will cause performance degradation.

  Furthermore, on many personal computers having a 32-bit architecture, an address space of 4 Gbytes or more cannot be handled as main memory, and it is difficult to provide a large-capacity extended memory that exceeds this limitation.

  As described above, the information processing apparatus called a conventional silicon disk, RAM disk, and extended storage is compared with the case where all are processed on the main memory on a system having a sufficiently large main storage capacity. Depending on the processing content, a significant performance degradation will occur.

  The present invention has been made in view of the above, and exhibits application processing performance comparable to the case of processing everything on the main memory on a system having a sufficiently large main storage capacity while suppressing the cost. Provide an information processing system that can

  In order to solve the above-described problems and achieve the object, the present invention includes a calculation means, a main storage device, and an information processing apparatus connected to the calculation means and the main storage device via a memory bus. The information processing apparatus is connected to the memory bus and assigned to an address in a first address space accessible by the arithmetic means, and when a page fault occurs, the information processing device A block means for transferring block data of a block size in units or whole to the buffer memory on the basis of an address in the first address space, and when the page fault occurs, Based on the address assigned to the address on the address space, the external memory connected to the information processing apparatus is accessed, and the address And having an external memory control unit for transferring page frame between the parts memory and the buffer memory.

  According to another aspect of the present invention, there is provided an information processing method in an information processing system including a calculation unit, a main storage device, and an information processing device connected to the calculation unit and the main storage device via a memory bus. When a page fault occurs, the page frame is connected to the memory bus and connected to the buffer memory allocated on the first address space accessible by the arithmetic means. A block step of transferring block data having a block size in units of all or part of the block data to the buffer memory based on an address in the first address space, and when the page fault occurs, The external memory connected to the information processing apparatus is accessed based on the address assigned in the address space of 2. And characterized by having an external memory control step for transferring page frame between the external memory and the buffer memory.

  In the information processing system according to the present invention, when a page fault occurs, a page frame is transferred between the main storage device and the buffer memory in units of the data size of the buffer memory mapped on the first address space. A page frame is transferred between the external memory and the buffer memory on the basis of the addresses transferred in a lump and mapped onto the second address space. As described above, since page frames can be transferred to and from a large-capacity external memory via the memory bus and the buffer memory, the processing efficiency can be improved.

  Embodiments of an information processing system and an information processing method according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
FIG. 1 is a diagram showing the overall configuration of the information processing system 1. The information processing system 1 includes a CPU 11, a north bridge 12, a south bridge 13, main memories 14 a and 14 b, a memory bus 16, and a memory module 100.

  The CPU 11 performs calculations using data in the main memories 14a and 14b and the external memories 140 to 143. The north bridge 12 and the south bridge 13 mediate between the CPU 11 and other devices. A memory bus 16 is connected to the north bridge 12. Main memories 14 a and 14 b and a memory module 100 are connected to the memory bus 16. The north bridge 12 directly accesses the main memories 14 a and 14 b and the memory module 100 via the memory bus 16.

  The information processing system 1 includes three memory slots (not shown) whose upper limit is 1 GB. Two of these are equipped with 512 MB memory modules with a low bit unit price. As a result, a total of 1 GB of main memories 14a and 14b is obtained. Further, a memory module 100 with a vector load store function for functioning as a silicon disk is attached to the remaining one.

  The memory module 100 is a memory module with a vector load / store function, and is formed on a silicon disk. The memory module 100 is accessed in a page fault handler. Furthermore, it is also accessed in a cache miss hit.

  The memory module 100 includes an information processing device 150 and a plurality of external memories 140 to 143. The information processing apparatus 150 includes a network control unit 110, a memory bus interface 120, and an external memory control unit 130. Each part of the information processing apparatus 150 is formed on an electronic circuit board.

  In the memory module 100, four memory modules constituting a 2 GB external memory are mounted. Thereby, the external memories 140 to 143 having a total capacity of 8 GB are mounted. The 8 GB external memories 140 to 143 are installed in a memory slot whose upper limit is 1 GB.

  The memory bus interface 120 includes a buffer memory 122, a buffer memory monitoring unit 124, and an address extension register 126. The external memory control unit 130 has an address generation unit 132.

  The external memories 140 to 143 of the memory module 100 store data used by the CPU 11. More specifically, the external memories 140 to 143 store page frames exchanged with the main memories 14a and 14b when a page fault occurs.

  The information processing apparatus 150 controls access to the external memories 140 to 143 and the network. The memory bus interface 120 of the information processing apparatus 150 manages data transfer with the memory bus 16.

  The external memory control unit 130 controls data transfer between the external memories 140 to 143 and the buffer memory 122. Specifically, continuous access is performed by a vector load command. The address generation unit 132 of the external memory control unit 130 acquires a vector load command or a vector store command from the CPU 11 via the memory bus 16. Here, the vector load refers to reading data of a predetermined size from the external memories 140 to 143 and writing it to the buffer memory 122. The vector store refers to reading data of a predetermined size and writing it to the external memories 140 to 143.

  When the address generation unit 132 acquires the vector load command or the vector store command, the address generation unit 132 generates a command address to be accessed in the command based on the acquired command. Here, the command address is an address on the I / O space that can be accessed by the external memory control unit 130 of the memory module 100. External memories 140 to 143 are mapped in the I / O space.

  The buffer memory 122 of the memory bus interface 120 temporarily stores data read from the external memories 140 to 143 by the external memory control unit 130 or data read from the main memories 14a and 14b.

  The buffer memory monitoring unit 124 monitors the buffer memory 122. Specifically, it is monitored whether or not data corresponding to the data size of the buffer memory 122, that is, a page frame in units of data blocks, is stored in the buffer memory 122.

  The external memory control unit 130 accesses the external memories 140 to 143 in units of data and writes necessary data to the buffer memory 122. When the writing of data for the data size to the buffer memory 122 is completed, the data stored in the buffer memory 122 is transferred to the main memories 14a and 14b via the CPU 11. At this time, the data in the buffer memory 122 is transferred in batches in units of data corresponding to the size of the buffer memory 122, that is, data blocks. That is, the data block is a size in which the whole or part of the page frame is a unit. The size of the sub-block of the buffer memory 122 is desirably the line size of the lowest hierarchy cache of the CPU from the viewpoint of improving the transfer bandwidth by burst transfer.

  When data stored in the buffer memory 122 is written to the external memories 140 to 143 based on the command address generated by the vector store command, the data continuously stored in the buffer memory 122 is stored in the external memory. Write to the area specified by the address in the address space.

  As described above, the external memory control unit 130 writes and reads predetermined data using the command address generated from the vector load command or the vector store command. The vector load command and the vector store command are issued, for example, when a page fault occurs during execution of the application. Also issued when a cache miss hit occurs.

  When a page fault occurs, a page fault handler is activated. The page fault handler performs paging processing. The page fault handler further issues a vector load command or a vector store command to the memory bus interface 120 instead of accessing the disk at startup.

  The CPU 11 can access data stored in the buffer memory 122 mapped on the CPU address space, which is an address space accessible by the CPU. However, the external memories 140 to 143 are not mapped on the CPU address space. This is because the upper limit of the 32-bit CPU 11 is 4 GB, and the entire capacity of the external memory 140 to 143 of 8 GB cannot be mapped as the main memory on the CPU address space that can be directly accessed from the CPU 11. Therefore, the external memory address space cannot be accessed.

  Therefore, for example, when a page fault occurs and the page frames stored in the main memories 14a and 14b are written to the external memories 140 to 143, a vector store command is first issued by the page fault handler. Then, the page frames of the main memories 14a and 14b are written into the buffer memory 122 by the vector store command. The page frame once written in the buffer memory 122 is read from the buffer memory 122 by the external memory control unit 130 and written in a predetermined area of the external memories 140 to 143. At this time, the external memory control unit 130 accesses a predetermined area of the external memories 140 to 143 based on an address in the external memory address space independent of the CPU address space.

  As described above, the page frames stored in the main memories 14 a and 14 b are indirectly written to the external memories 140 to 143 through the buffer memory 122.

  Furthermore, since addresses in the external memory address space are used, even if the CPU 11 has a 32-bit dedicated architecture such as the IA32 architecture, it can be loaded and stored in the 8 GB external memories 140 to 143 without any problem.

  On the other hand, when a page frame stored in the external memories 140 to 143 is written in the main memories 14a and 14b, a vector load command is first issued by the page fault handler. Then, the page frame is written from the external memories 140 to 143 to the buffer memory 122 by the vector load command.

  Then, after the vector load in the buffer memory 122 is completed, read access to the buffer memory 122 is performed, a page frame is read from the buffer memory 122 in units of data blocks, and is transferred to the main memories 14a and 14b at once. As described above, the page frames stored in the external memories 140 to 143 indirectly from the buffer memory 122 are transferred to the main memories 14 a and 14 b via the buffer memory 122. As described above, the external memories 140 to 143 are mapped on the external memory address space and are used as page frame storage areas.

  The network control unit 110 of the memory module 100 accesses the external memories 140 to 143 to read / write data related to transmission / reception. Further, the CPU 11 reads / writes control data from / to the network control unit 110, so that the network control unit 110 accesses the external memories 140 to 143 and executes communication instructed by the CPU 11 as a network interface. Fulfills the function.

  FIG. 2 is a flowchart of the swapping process performed by the information processing system 1 according to the first embodiment. If a page fault occurs during execution of the application (step S100, Yes), a page fault handler is called (step S102). Here, the page fault handler operates as a page fault control means.

  Next, the page fault handler performs address extension processing (step S104). Here, the address expansion process is a process of writing an address for identifying the external memories 140 to 143 into the address expansion register 126. In the present embodiment, the memory bus is 32 bits wide. Therefore, the address of the upper 3 bits of the external memories 140 to 143 that are insufficient is written to the address extension register 126.

  Next, the page fault handler issues a vector store command (step S110). Here, the vector store command is an instruction for saving the data stored in the buffer memory 122 to the external memories 140 to 143. In the vector store command, it is possible to specify whether the data is saved to a continuous address or a discontinuous address in the external memories 140 to 143.

  When the vector store command is issued, the page frames stored in the predetermined areas of the main memories 14a and 14b are transferred to the buffer memory 122 via the memory bus 16. And it writes in order to the buffer memory 122 (step S112). Next, the address generation unit 132 of the external memory control unit 130 generates a command address to be accessed by the vector store command based on the vector store command. Then, the external memory control unit 130 writes the page frame stored in the buffer memory 122 in an area specified by the command address generated by the external memory control unit 130 in the external memories 140 to 143 (step S114). As described above, the page frames stored in the main memories 14a and 14b are transferred via the memory bus 16 and saved in the external memories 140 to 143. This completes the swap-out.

  As described above, at the time of writing from the host CPU 11, the write data is stored in the buffer memory 122 and then copied from the buffer memory 122 to the external memories 140 to 143 using the vector store command to write the data.

  As described above, when a page fault occurs, the page frames in the main memories 14a and 14b are saved via the memory bus 16, so that the processing efficiency can be improved.

  Further, when the saving of the page frames in the main memories 14a and 14b is completed, the page fault handler issues a vector load command (step S120). Here, the vector load command is an instruction to read data stored in a predetermined area of the external memories 140 to 143 through the buffer memory 122. In the vector load command, data can be read from an area corresponding to either a continuous address or a discontinuous address in the external memories 140 to 143.

  When the vector load command is issued, the external memory control unit 130 acquires the vector load command via the memory bus 16. Then, the address generation unit 132 generates a command address to be accessed by the vector load command based on the vector load command. Then, the external memory control unit 130 sequentially writes the page frames stored in the external memories 140 to 143 to the buffer memory 122 (step S122).

  When a page frame corresponding to the data size of the buffer memory 122 is written (step S124, Yes), the page frame stored in the buffer memory 122 is sent to the memory bus 16 in units of data blocks and is collectively stored in the main memories 14a and 14b. Transferred (step S126). Thus, the swap-in is completed. Thus, the swapping process by the information processing system 1 according to the first embodiment is completed.

  As described above, when reading from the CPU 11, the host CPU 11 reads the buffer memory 122 and takes in the data after loading necessary data from the external memories 140 to 143 into the buffer memory 122 using the vector load command.

  Here, a process in which the CPU 11 monitors whether or not a page frame for the data size has been written in the buffer memory 122 will be described. Specifically, the buffer memory 122 is divided into a plurality of sub data blocks. For example, it is divided into 64 bytes according to the cache line size of the CPU 11 from the viewpoint of improving the transfer bandwidth by burst transfer. A flag is provided for each sub data block. This flag indicates whether writing of block data constituting the page frame is completed. By reading this flag, the CPU 11 monitors whether or not writing of block data constituting the page frame to each sub data block is completed. When the buffer memory is 512 bytes and the page frame is 4 KB, the transfer using the buffer memory including 8 sub-blocks from 512/64 = 8 is repeated 8 times from 4 KB / 512B = 8, so that the entire page frame Can be transferred.

  When it is confirmed that the value indicates completion of page frame writing, an actual read command is issued to obtain a corresponding sub data block. By monitoring the completion of page frame writing in this way, it is possible to prevent a read command from being issued before page frame writing is completed. In other words, even when the completion of page frame writing is delayed, it is possible to respond flexibly.

  In this case, it is preferable that the buffer memory 122 is mounted with a flag using, for example, a register disposed at a close position on the memory bus interface 120 so that the CPU 11 can read the flag. Furthermore, it is preferable that a plurality of (for example, 64 bits) flag states can be acquired by one read access.

  As described above, when the page fault handler performs swap-in / swap-out, the information processing system 1 according to the first embodiment uses the memory bus 16 having a higher transfer speed instead of accessing the disk. The connected buffer memory 122 is accessed. As a result, the processing efficiency can be improved.

  For example, it is assumed that the main memory 14a, 14b has only 1 GB, and an application program that requires access to, for example, a total of 3 GB of array data is executed. At this time, it is assumed that a page fault has occurred and a swap-in / swap-out has occurred with the page frame. Even in this case, in the information processing system 1 according to the first embodiment, it is possible to access a page frame with a high bandwidth and a low delay as the main memory.

  Therefore, in the event of a page fault, the performance that occurs when accessing a hard disk or accessing a silicon disk that is accessed via an interface that has a lower bandwidth and higher latency than main memory such as SCSI. Decline can be prevented.

  Furthermore, the processing can be executed without changing the application program at all with the performance as if the main memory is 4 GB in the case of the 32-bit OS and 9 GB in the case of the 64-bit OS.

  As described above, the information processing system 1 according to the present embodiment can perform processing by regarding the memory module 100 as a disk.

  Thus, without modifying the application program, a relatively small and inexpensive personal computer is used as a component, and a silicon disk having a sufficiently large capacity is mounted, thereby avoiding unstable operation and performance degradation of the OS. Application processing performance comparable to the case where everything is processed on the main memory on a system having a sufficiently large main storage capacity can be exhibited.

  Furthermore, the information processing system 1 according to the first embodiment can perform processing by regarding the memory module 100 as main memory.

  FIG. 3 is a flowchart of the preload process performed by the information processing system 1 according to the first embodiment. In the preload process, the memory module 100 can be operated like a main memory that can be operated by a programmer specifying an address with a command. Here, not only high-speed transfer of page frames but also a case where a vector load command is issued as a preload command will be described in order to avoid frequent occurrence of cache miss hits during discontinuous access.

  When the vector load command is issued by the CPU 11 (step S200), the vector load command is transferred to the memory module 100 via the north bridge 12 and the memory bus 16.

  Next, in the memory module 100, a vector load command is activated. Then, the address generator 132 of the external memory controller 130 generates a command address to be accessed in the vector load command.

  Next, the external memory control unit 130 accesses the external memories 140 to 143 based on the command address generated by the address generation unit 132, and sequentially writes the obtained data in the buffer memory 122 (step S202).

  If one column shown on the left side of FIG. 4 is one line of the cache, when discontinuous access is performed in the normal main memory, only the black circle data is valid, whereas the buffer memory 122 is used. It is possible to increase the hit rate by collecting the black circle data using the vector load command and then loading it into the cache.

  On the other hand, the CPU 11 monitors whether or not the data for the buffer memory 122 is stored in the buffer memory 122, that is, whether or not the preload is completed. When preloading is completed (step S206, Yes), a read command is issued (step S208).

  Specifically, the buffer memory 122 is divided into a plurality of sub data blocks. A flag is provided for each sub data block. This flag indicates whether or not preloading has been completed. By reading this flag, the CPU 11 monitors whether or not preloading of each sub data block is completed, that is, whether or not data is stored in the sub data block.

  When it is confirmed that the value indicates completion of preloading, an actual read command is issued to obtain a corresponding data block. By monitoring the completion of the preload in this way, it is possible to prevent a read command from being issued before the preload is completed. That is, even when the preload completion is delayed, it can be flexibly dealt with.

  As described above, the CPU 11 issues a read command (step S208), and transfers the read command to the memory module 100 via the north bridge 12 and the memory bus 16. When acquiring the read command, the memory module 100 collectively transfers the data corresponding to the read command, that is, the data stored in the buffer memory 122 to the CPU 11 in units of data blocks (step S210). Thus, the preload process in the information processing system 1 is completed.

  As described above, the information processing system 1 according to the first embodiment can perform the preload process by regarding the memory module 100 as the main memory.

  Further, as described with reference to FIG. 2, the external memories 140 to 143 are provided with an area that is accessed as a disk via a page fault handler, and an area that is accessed as a main memory in the application program. Is controlled to be variable. For each process, the memory module 100 is switched between being used as a disk and as being used as a main memory.

  Specifically, the OS is set so that the swap area allocation can be changed. In other words, as an attribute of the virtual address in the address conversion table, an area that can be regarded as main memory or an area that can be regarded as a disk is set. As described above, the OS operates as an accessible area designating unit.

  For example, assume that an application is executed that preferably has a large main memory and high speed reading and writing to a continuous address area. In this case, it is preferable to increase the area accessed on the external memories 140 to 143 as a disk. Thereby, an application program can be executed at high speed.

  On the other hand, it is assumed that an application that preferably has a high speed at equal intervals and random reading / writing to discontinuous addresses for a large amount of data is executed. In this case, it is preferable to increase the area accessed from the application program as the main memory. Thereby, although the application is required to support such processing, the application program can be executed at high speed.

(Embodiment 2)
FIG. 5 is a diagram illustrating an overall configuration of the information processing system 1 according to the second embodiment. The hardware configuration of the information processing system 1 according to the second embodiment is the same as that of the information processing system 1 according to the first embodiment. In the second embodiment, when the general-purpose page fault handler is activated, the dedicated driver is activated. The dedicated driver performs the swapping process between the memory module 100 and the main memories 14a and 14b as described in the first embodiment.

  The dedicated driver is a driver for making the external memories 140 to 143 mapped to the external memory address space appear as virtual disks. That is, it functions as a page fault control means. The dedicated driver can be realized by switching the procedure part for accessing the main memory to the data transfer procedure using the vector load / store command having the address extension function described in the first embodiment. As a result, an external memory that has a large capacity different from that of the main memory and that can be accessed with a high bandwidth and low delay comparable to the main memory can be accessed as a disk in terms of the OS.

  In this way, once the external memories 140 to 143 of the memory module 100 can be accessed as a disk from the CPU 11, when the OS is Windows (registered trademark), a page frame is stored in the virtual disk. A virtual memory swap file can be created as a storage area.

  FIG. 6 is a flowchart showing the swapping process in the second embodiment. When a page fault occurs, a general-purpose page fault handler is called (step S130). Next, a dedicated device is further called (step S132). Then, the processing after step S104 is performed by the dedicated device. Here, the dedicated device operates as a page fault control means.

  As described above, in the information processing system 1 according to the second embodiment, similarly to the information processing system 1 according to the first embodiment, in the swapping process, the page frame has the same high bandwidth as the main memory and low delay access. can do.

  Other configurations and processes of the information processing system 1 according to the second embodiment are the same as the configurations and processes of the information processing system 1 according to the first embodiment.

(Embodiment 3)
FIG. 7 is a diagram illustrating an overall configuration of the information processing system 2 according to the third embodiment. As illustrated in FIG. 7, the information processing system 2 is a PC cluster including a plurality of information processing systems 1 described in the first embodiment or the second embodiment. The plurality of information processing systems 1 are connected to each other via a network 5.

  Each information processing system 1 can access an external memory provided on a remote node, that is, another information processing system 1 via the network 5. As described with reference to FIG. 1 in the first embodiment, each information processing system 1 can access an external memory on a remote node via the network control unit 110.

  Thus, in the information processing system 1 according to the third embodiment, part of access to the external memories 140 to 143 included in the information processing system 1 in the first embodiment is extended to access to the external memory on the remote node. And As a result, the external memory existing in the entire PC cluster can be accessed as a virtual disk.

  By storing the page frame in the external memory on the remote node, it is possible to construct a PC cluster that can access the external memory that exists in the entire PC cluster as a virtual main memory.

  FIG. 8 is a flowchart showing the swapping process by the information processing system 1 according to the third embodiment configured as described above. When a page fault occurs (step S300), a page fault handler is called (step S130). Next, the page fault handler performs address expansion corresponding to the external memory on the remote node (step S104).

  Next, a vector store command is issued (step S110). As a result, the page frames of the main memories 14a and 14b are saved in the buffer memory 122 (step S112). Further, the page frame stored in the buffer memory 122 is saved in the external memory on the remote node via the network control unit 110 (step S140).

  Next, the page fault handler issues a vector load command (step S140). As a result, the page frame of the external memory on the remote node is written into the buffer memory 122 (step S142). When the writing of the page frame for the data size is completed (step S124, Yes), the page frame of the buffer memory 122 is written to the main memories 14a and 14b (step S126). This completes the swapping process.

  As described above, each information processing system 1 can perform the swapping process by using the external memory on the remote node in the same manner as its own external memory.

  For example, in the information processing system 2 including 20 information processing systems 1, the total external memory is 160 GB. If each node processor, that is, the CPU 11 of the information processing system 1 is running a 64-bit OS, 20 CPUs 11 can access a 160 GB virtual main memory.

  As described above, in the information processing system 2, the entire data of the medium-sized database can be held on the large-capacity virtual main memory. Therefore, it is possible to greatly speed up processing such as database search processing.

  Tanabe, Hakozaki, Ando, Toi, Nakajo, Miyashiro, Kitamura, Amano: "Effects of Equal Interval Access Consecution on Memory Modules" Information Processing Society of Japan Computer Architecture Study Group (March 2005) According to the memory module with the load / store function, the database search process stored in the main memory can be accelerated up to about 25 times by sequential processing. Therefore, in the information processing system 1 according to the third embodiment, the effect can be exhibited even in a database having a larger capacity.

  By the way, there is a technique for configuring a semiconductor extended memory by gathering the above main memories by using a driver that can regard the main memories in the processing elements of PC clusters and parallel computers as disks over the network. For example, it is implemented in a super technical server SR11000 of Hitachi, Ltd.

  However, it is difficult to provide a large amount of expanded memory as this system because it becomes impossible to use a part of the main memory in the processing element that tends to be short of capacity even as the original main memory. However, there was a drawback that it would cause performance degradation if used incorrectly. In addition, since the frequency of access through the network increases, the burden on the network is large.

  Although the method of setting the main memory on the remote node of the PC cluster or parallel computer as a RAM disk can have a larger capacity than the above method, there is a strict limit on the main memory capacity. It is difficult to provide, and there is a drawback that the performance is deteriorated if the capacity setting is wrong. In addition, the burden on the network is large.

  On the other hand, in the information processing system 2 according to the third embodiment, data transferred via the network is also stored in the buffer memory 122, and data transfer is performed between the buffer memory 122 and the main memories 14a and 14b. Therefore, the processing efficiency can be improved without causing the performance of each part to deteriorate.

1 is a diagram illustrating an overall configuration of an information processing system 1. FIG. 3 is a flowchart showing swapping processing by the information processing system 1 according to the first exemplary embodiment; 3 is a flowchart showing preload processing by the information processing system 1 according to the first exemplary embodiment; It is a figure for demonstrating the process of the external memory control part. It is a figure which shows the whole structure of the information processing system 1 concerning Embodiment 2. FIG. 10 is a flowchart showing swapping processing in the second embodiment. It is a figure which shows the whole structure of the information processing system 2 concerning Embodiment 3. FIG. 10 is a flowchart showing swapping processing by the information processing system 1 according to the third exemplary embodiment.

Explanation of symbols

1, 2 Information processing system 5 Network 11 CPU
DESCRIPTION OF SYMBOLS 12 North bridge 13 South bridge 14a, 14b Main memory 16 Memory bus 100 Memory module 110 Network control part 120 Memory bus interface 122 Buffer memory 124 Buffer memory monitoring part 126 Address expansion register 130 External memory control part 132 Address generation part 140 External memory 150 Information processing device

Claims (12)

Computing means;
A main storage device;
An information processing device connected to the arithmetic means and the main storage device via a memory bus;
The information processing apparatus includes:
A buffer memory connected to the memory bus and assigned an address on a first address space accessible by the computing means;
Transfer means for collectively transferring block data having a block size in units of part or all of the page frame to the buffer memory based on an address in the first address space when a page fault occurs; ,
When the page fault occurs, the external memory connected to the information processing apparatus is accessed based on the address assigned the address in the second address space, and the external memory is connected to the buffer memory. And an external memory control means for transferring page frames. The information processing apparatus further includes address expansion means for writing an upper address for identifying the external memory connected to the external memory control means to the address expansion register when the page fault occurs,
The external memory control means transfers the page frame between the external memory and the buffer memory by accessing the external memory based on the upper address written in the address extension register. The information processing system according to claim 1. The transfer means saves the page frame stored in the main storage device to the buffer memory,
The information processing system according to claim 1, wherein the external memory control unit writes the page frame saved in the buffer memory to the external memory. A vector store command issuing means for issuing a vector store command when the page fault occurs;
The external memory control unit generates an address on the second address space based on the vector store command, and writes the page frame in an area specified by the address in the external memory. The information processing system according to claim 3. The external memory control means reads the page frame stored in the external memory, stores it in the buffer memory,
5. The information processing system according to claim 1, wherein the transfer obtaining unit writes the page frame stored in the buffer memory into the main storage device. 6. A vector load command issuing means for issuing a vector load command when the page fault occurs;
The external memory control unit generates an address on the second address space based on the vector load command, and reads the page frame from an area specified by the address in the external memory. The information processing system according to claim 5.   7. The transfer unit collectively transfers the block data stored in the buffer memory to the arithmetic unit after the page frames for the block size are stored in the buffer memory. Information processing system described in 1. A page fault control unit that is called when the page fault occurs and issues a vector store command and a vector load command for the external memory;
The external memory control means transfers the page frame between the external memory and the buffer memory based on the vector store command and the vector load command issued by the page fault control means. The information processing system according to claim 1. A page fault handler that is called when the page fault occurs;
Page fault control means that is called in the page fault handler and issues a vector store command and a vector load command for the external memory, and
The external memory control means transfers the page frame between the external memory and the buffer memory based on the vector store command and the vector load command issued by the page fault control means. The information processing system according to claim 1. Of the external memory, further comprising an accessible area designating unit for designating a page fault corresponding area accessible when the page fault occurs,
The information processing system according to any one of claims 1 to 9, wherein the external memory control unit accesses the page fault corresponding region specified by the accessible region specifying unit. The accessible area designating unit further designates an area corresponding to a cache miss hit that is accessible when a cache miss occurs in the external memory,
The external memory control means, when a cache miss occurs, reads the data by accessing the cache miss hit corresponding area designated by the accessible area designating means,
11. The information processing system according to claim 10, wherein the transfer unit collectively transfers the data read from the external memory by the external memory control unit via the memory bus. An information processing method in an information processing system comprising a calculation means, a main storage device, and an information processing device connected to the calculation means and the main storage device via a memory bus,
When a page fault occurs, a part of the page frame or the part of the page frame is connected to the memory bus connected to the buffer memory allocated on the first address space and connected to the memory bus. A transfer step of performing batch transfer of block data of a block size in whole to the buffer memory based on an address on the first address space;
When the page fault occurs, the external memory connected to the information processing apparatus is accessed based on the address assigned in the second address space, and a page is set between the external memory and the buffer memory. And an external memory control step for transferring a frame.

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