JP2007037178A5 - - Google Patents

Description

Interleaving method and transmitting apparatus

The present invention relates to an interleaving technique for improving the capability of an error correction code for a burst error, and more particularly to a technique using an interleaving method that improves the interleaving effect by increasing the randomness of data.

The present invention also relates to a technique suitable for use in combination with a data reception method that performs synchronous detection using an interpolated pilot signal.

  In digital transmission of a mobile communication system or the like, the level of a received signal varies greatly in time due to multipath fading due to reflection of a building or the like, thereby causing a code error such as a reburst error. For this reason, various error correction codes are used in the system. In such an error correction code, an interleaving technique is used in order to improve the correction capability for burst errors. The quality of this interleaving technique determines the ability of the error correction code in the presence of burst errors.

  As known to those skilled in the art, the interleaving method is aimed at randomizing the order of bits in the input bit sequence and the order of bits in the output bit sequence. FIG. 1 shows an example of a conventional interleaving method. This figure shows an example in which interleaving processing is performed on one frame of data 101 composed of 1152 bits. The array 110 has a buffer of N × M (N rows and M columns). Interleaving is realized by writing 16 bits in the row direction as in the row vector 115 and reading out 72 bits in the column direction as in the column vector 120 in the hatched portion B.

  By the way, various mobile communication devices are required to multiplex and transmit a plurality of channels. FIG. 2 is a diagram showing an example of a multiplexing apparatus in the prior art. The multiplexing apparatus 30 includes transmission path encoding units 32 and 34, transmission path interleavers 36 and 38, frame segmentation units 40 and 42, A sub-blocking / multiplexing unit 44 and a physical channel mapping unit 46 are provided. The frame has a fixed time length equal to the minimum interleaving span.

  In the figure, a transmission path encoding unit 32, a transmission path interleaver 36, and a frame segmentation unit 40 perform interleaving processing for logical channel A, and a transmission path encoding unit 34, a transmission path interleaver 38, and a frame segment. The conversion unit 42 performs interleaving processing for the logical channel B. The interleaving process is performed by the above-described method, for example.

Here, the logical channel A has an encoded block size L _A and an interleaving span I _A , and the logical channel B has an encoded block size L _B and an interleaving span I _B. The interleaving spans I _A and I _B are not necessarily the same. After error correction and interleaving in each channel, segmentation for multiplexing is performed in each frame segment unit 40, 42. Multiplexing is performed in segment units. By adopting such a configuration, the difference in interleaving span of each channel is absorbed. The sub-blocking / multiplexing unit divides the frame data of each channel into sub-blocks of an appropriate size in advance so that the bits of the two logical channels are distributed as uniformly as possible over the entire frame. Then, each channel data is multiplexed alternately in sub-block units.

  By the way, in the field of mobile communication, since a mobile station moves at a high speed, it is necessary to ensure a stable operation even in an environment with a high fading pitch. For this reason, a pilot signal indicating a modulation reference phase is transmitted in a predetermined cycle. A slot between one pilot signal and the next pilot signal is called a slot, and a data signal is arranged between them. Then, on the receiving side that has received the signal composed of each slot, the reference phase within the slot period is obtained by interpolation based on the pilot signal at the head portion and the pilot signal at the tail portion of the slot, and is interpolated. Synchronous detection is performed based on the reference phase. Such a method for obtaining the reference phase adaptively is often called synchronous detection using an interpolated pilot signal. There are various methods for this, but depending on the time from each pilot signal, the interpolation coefficient The method of determining is general.

  Here, when variable rate data transmission is performed, data is transmitted in bursts. In this case, a technique has been developed for arranging the data signals in one slot so as to be adjacent to the pilot signals (Non-patent Document 1: Rigaku Technical Report RCS 95-166).

  This point will be specifically described with reference to FIG. FIG. 3 is a diagram showing a relationship between a conventional pilot signal and a data signal. In this example, the period of one slot is 1 msec. If the transmission rate of the data signal is 32 kbps, continuous transmission is performed, and a 32-bit data signal is arranged between the pilot signals PS. On the other hand, when the data transmission rate is lower than 32 kbps, burst transmission is performed. For example, if the transmission rate is 16 kbps, 16 bits of data signal are arranged adjacent to the pilot signal PS arranged at the head portion of the slot as shown in the figure.

  However, in the above multiplexing apparatus 30 according to the prior art, each of the transmission line interleavers 36 and 38 must perform different bit interleaving processing on input data of different block sizes and different interleaving spans. Therefore, there is a problem that the processing cannot be performed efficiently.

  In the data transmission / reception method using the above-described interpolated pilot signal, when the S / N of the transmission path is low and the transmission quality is poor, the received pilot signal is superimposed with a large level of noise. For this reason, the phase measurement result by the pilot signal PS includes a large error. As described above, the reference phase in the slot period is adaptively estimated by determining the interpolation coefficient according to the time from the pilot signal PS at the head portion and the tail portion. Accordingly, noise is not averaged in the vicinity of the pilot signal PS, and the estimation error increases. For this reason, when the data signal is arranged adjacent to the pilot signal PS at the head portion, there is a problem that it is greatly affected by noise and transmission quality deteriorates.

  On the other hand, when the noise is sufficiently small or the fading pitch is high, the influence of the phase change due to fading becomes rather larger than the noise. In this case, the transmission quality can be improved by arranging the data signal in the vicinity of the pilot signal PS.

As for the problem relating to the above data transmission / reception method, Japanese Patent Application Laid-Open No. 9-298519 (Japanese Patent Application No. 8-111644) discloses a solution to this problem. However, when interleaving data bits, An interleaving method suitable for flattening the data quality is not shown.
IEICE Technical Report RCS95-166 JP-A-9-298519

The present invention has been made in view of the circumstances described above, and a first object of the present invention is to distribute multiplexed bits by performing an appropriate interleaving process to maximize error correction capability. Te is Rukoto improve the transmission quality of the data, the second object performs interleaving processing suitable for data transmission and reception method using the interpolation pilot signal, placing the data signals to the appropriate location within the slot Thus, the data quality in the frame is flattened to improve the transmission quality.

Furthermore, a third object of the present invention is to combine the above multiplexing method and multiplexing apparatus with the above data signal transmission method and data signal transmission apparatus, to distribute multiplexed bits and to flatten the data quality within a frame. It is to provide a technique having both effects.

  It is a common problem of the present invention to improve data transmission quality.

In order to solve the above-described problem, the invention described in claim 1 multiplexes a plurality of information data, interleaves the multiplexed signals using a matrix structure interleaver, and puts them in a slot. An interleaving method in a transmitting apparatus for transmitting a signal of a frame composed of slots, wherein the number of columns of the matrix is an integer multiple of the number of slots in the one frame (an integer is an integer greater than 1), In the interleaving method, the multiplexed signal is written in the matrix, the written signal is replaced in units of columns based on a predetermined rule, and the signal after the replacement is read from the matrix.

  The invention described in claim 2 multiplexes a plurality of information data, interleaves the multiplexed signals using a matrix structure interleaver, puts them in a slot, and transmits a frame signal composed of a plurality of slots. The number of columns in the matrix is an integer multiple of the number of slots in the one frame (the integer is an integer greater than 1), and the multiplexed signal is stored in the matrix. The written signal is replaced in units of columns based on a predetermined rule, the signal after the replacement is read from the matrix, the read signal is stored in a slot, and a frame signal composed of a plurality of slots is transmitted. , An interleaving method characterized by transmitting a pilot signal.

  The invention described in claim 3 multiplexes a plurality of pieces of information data, interleaves the multiplexed signals using a matrix structure interleaver, puts them in a slot, and transmits a frame signal composed of a plurality of slots. The number of columns in the matrix is an integer multiple of the number of slots in the one frame (the integer is an integer greater than 1), and the multiplexed signal is stored in the matrix. The written signal is replaced in units of columns based on a predetermined rule, the signal after the replacement is read from the matrix, a pilot signal is added to the information data composed of the read signal, and the signal is stored in a slot. This is an interleaving method characterized by transmitting a frame signal composed of slots.

  The invention described in claim 4 multiplexes a plurality of information data, interleaves the multiplexed signals using a matrix structure interleaver, puts them in a slot, and transmits a frame signal composed of a plurality of slots. The number of columns in the matrix is an integer multiple of the number of slots in the one frame (the integer is an integer greater than 1), and the multiplexed signal is stored in the matrix. The written signal is replaced in units of columns based on a predetermined rule, the signal after the replacement is read from the matrix, the read signal is stored in a slot, and a frame signal composed of a plurality of slots is transmitted. The pilot signal is transmitted using a physical channel that is different from the physical channel that transmits the signal of the frame. A interleaving method characterized by.

  According to a fifth aspect of the present invention, in the method according to any one of the first to fourth aspects, the signals read from the matrix are distributed in the slots so as to include at least the ends and the center in the slots. It is characterized by this.

  The invention described in claims 6 to 10 is an invention of a transmitting apparatus corresponding to the method invention described in claims 1 to 5.

  The invention described in claim 11 is a method of interleaving multiplexed symbols and transmitting a frame including a slot holding at least a part of the interleaved symbols, wherein the multiplexed symbols are transmitted. The process of storing in a memory as a plurality of groups and reading symbols from the same predetermined position in each group is repeated until all the symbols stored in the memory are read from the memory, and the read symbols are arranged in a plurality of slots. And the number of symbols of each group in the plurality of groups is an integer multiple of the number of slots constituting one frame (the integer is an integer greater than 1). ).

  The invention described in claim 12 is a method of interleaving multiplexed symbols and transmitting a frame including a slot that holds at least a part of the interleaved symbols, wherein the multiplexed symbols are transmitted. The process of storing in a memory as a plurality of groups and reading symbols from the same predetermined position in each group is repeated until all the symbols stored in the memory are read from the memory, and the read symbols are arranged in a plurality of slots. And transmitting a plurality of slots on a predetermined physical channel and transmitting pilot symbols, wherein the number of symbols of each group in the plurality of groups is an integer multiple of the number of slots constituting one frame (integer) Is an integer greater than 1) It is the law.

  The invention described in claim 13 is a method of interleaving multiplexed symbols and transmitting a frame including a slot holding at least a part of the interleaved symbols, wherein the multiplexed symbols are transmitted. Store in the memory as a plurality of groups, and repeat the step of reading symbols from the same predetermined position in each group until all the symbols stored in the memory are read from the memory, and add the read symbols to the pilot symbols The number of symbols of each group in the plurality of groups is an integer multiple of the number of slots constituting one frame (which is arranged in a plurality of slots and transmits the plurality of slots on a predetermined physical channel). Integer is an integer greater than 1) It is the law.

  The invention described in claim 14 is a method of interleaving multiplexed symbols and transmitting a frame including a slot holding at least a part of the interleaved symbols, wherein the multiplexed symbols are transmitted. The process of storing in a memory as a plurality of groups and reading symbols from the same predetermined position in each group is repeated until all the symbols stored in the memory are read from the memory, and the read symbols are arranged in a plurality of slots. The plurality of slots are transmitted using a physical channel different from a physical channel for transmitting pilot symbols, and the number of symbols in each group in the plurality of groups is an integer of the number of slots constituting one frame. Double (integer is an integer greater than 1) It is a method characterized by.

  The invention described in claim 15 is the method according to any one of claims 11 to 14, wherein the predetermined position is determined by a predetermined rule.

  According to a sixteenth aspect of the present invention, in the step of arranging the read symbols in a plurality of slots, at least a part of the interleaved symbols is distributed in the slots so as to include at least an end and a central part in the slots. 16. A method according to any one of claims 11 to 15, characterized in that it is arranged.

  The invention described in claim 17 is the method according to any one of claims 11 to 16, wherein the symbols in the slot are subjected to spread spectrum modulation.

  The invention described in claims 18 to 24 is an invention of a transmitting apparatus corresponding to the method invention described in claims 11 to 17.

  The present application also discloses the following invention.

The present invention is a method for multiplexing channels, wherein an encoding step of encoding input data for each input channel, a step of multiplexing the encoded data, and the multiplexed data A step of performing an interleaving process, and a step of outputting the data after the interleaving process to a physical channel.

  According to the present invention, a complex multiplexing unit with sub-blocking is simplified, and an interleaver is commonly used for each channel, so that the hardware scale can be reduced.

In the above configuration, the write data interleaving process in the interleaver performs randomizing columns of the interleaver may be configured to read data from said interleaver.

  According to the present invention, since the multiplexed bits are distributed over the entire frame, the error correction capability can be improved.

In the above configuration, the interleaver may have a column number that is an integral multiple of the number of slots of the output data frame.

In the above configuration, the number of columns of the interleaver may be a 16 or 32, or 15 or 30.

  According to these inventions, it is possible to continuously arrange pilot symbols and data bits, and the apparatus can be simplified as compared with other methods.

In the above structure, the pattern for the randomization can be configured to interleave pattern suitable for transmission line interleaver. According to the present invention, it is possible to perform interleaving optimal for data transmission.

In the above configuration, after the encoding step, a step of performing another interleaving process and a step of segmenting the data subjected to the other interleaving process may be included .

  According to the present invention, when the block size of the input data exceeds the frame length, inter-frame interleaving is performed in advance, so that the block size of the interleaver in the interleaving process according to claim 2 can be made the same as the frame size. it can.

The present invention is also a multiplexing device for multiplexing channels, encoding means for encoding input data for each input channel, multiplexing means for multiplexing the encoded data, An interleaver that performs an interleaving process on the multiplexed data and an output unit that outputs the data after the interleaving process to a physical channel are configured.

Further, the present invention is used in combination with a data signal receiving method for reproducing a reference phase at each timing of a modulated data signal based on each pilot signal indicating a modulation reference phase and demodulating the data signal. A data signal transmission method for transmitting the data signal in bursts, arranging the data signal between the pilot signals to form a slot, and transmitting the plurality of slots. The data signal transmission method includes an interleaving step for performing an interleaving process on the data signal, a step of dividing a data signal to be transmitted within one slot period, and a plurality of the data signals. A step of distributing data blocks in the slots, -Up is configured to be a step of performing interleaving processing using the interleaver with the number of columns is twice the number of slots in a frame of the data signal.

  According to the present invention, it is possible to reduce the data transmission error rate and flatten the bit quality in the frame.

Further, the present invention is used in combination with a data signal receiving method for reproducing a reference phase at each timing of a modulated data signal based on each pilot signal indicating a modulation reference phase and demodulating the data signal. A data signal transmission method for transmitting the data signal in bursts, arranging the data signal between the pilot signals to form a slot, and transmitting the plurality of slots. The data signal transmission method includes an encoding step of encoding a data signal for each channel, a step of multiplexing the data signal of each channel, and an interleaving process for the multiplexed data signal An interleaving step and a data signal to be transmitted within one slot period are divided into a plurality of data blocks. And a step of distributing the plurality of data blocks in the slots, wherein the interleaving step sends data to an interleaver having a number of columns twice the number of slots in one frame of a data signal. It comprises a step of writing, a step of randomizing the sequence of the interleaver, and a step of reading data from the interleaver.

  According to the present invention, it is possible to obtain the effect of flattening the bit quality while maintaining the effect of bit dispersion in the multiplexing method of the present invention.

In the above configuration, the number of slots in the one frame may be 15 or 16. According to the present invention, it is possible to obtain the bit distribution effect and the bit quality flattening effect in the multiplexing method of the present invention only by randomizing columns.

The said structure WHEREIN: You may comprise so that the step which partially replaces the row | line | column of the said interleaver after the said randomization may be included .

  According to the present invention, the effect of bit dispersion and the effect of flattening the bit quality can be obtained in the case of various slot numbers.

In the above configuration, the randomization may be performed by an interleaving pattern for performing randomization of columns suitable for transmission path interleaving and partial replacement of columns. By using such an interleaving pattern, it is possible to obtain a bit dispersion effect and a bit quality flattening effect.

Further, the present invention is used in combination with a data signal receiving apparatus that reproduces a reference phase at each timing of a modulated data signal based on each pilot signal indicating a modulation reference phase and demodulates the data signal. A data signal transmission device for transmitting the data signal in bursts, arranging the data signal between the pilot signals to form a slot, and transmitting a plurality of the slots. The data signal transmitting apparatus includes: an interleaving unit that performs an interleaving process on the data signal; a unit that divides a data signal to be transmitted within one slot period into a plurality of data blocks; Means for distributing data blocks in the slots, and the interleaving means Configure to have an interleaver having a row number of 2 times the number of slots in a frame of the data signal.

  According to the present invention, the data transmission error rate can be reduced, and the bit quality in the frame can be flattened.

Further, the present invention is used in combination with a data signal receiving apparatus that reproduces a reference phase at each timing of a modulated data signal based on each pilot signal indicating a modulation reference phase and demodulates the data signal. A data signal transmission device for transmitting the data signal in bursts, arranging the data signal between the pilot signals to form a slot, and transmitting a plurality of the slots. The data signal transmitting apparatus includes: an encoding unit that encodes a data signal for each channel; a multiplexing unit that multiplexes the data signal of each channel; and an interleaving process for the multiplexed data signal And interleaving means for dividing the data signal to be transmitted in one slot period into a plurality of data blocks; Means for distributing and arranging the plurality of data blocks in the slots, and the interleaving means writes data to an interleaver having a number of columns twice the number of slots in one frame of a data signal, The interleaver sequence is randomized and data is read from the interleaver.

  FIG. 4 is a block diagram of the multiplexing apparatus 50 according to the embodiment of the present invention corresponding to the first object. The multiplexing apparatus 50 includes transmission path encoding units 52 and 54, first interleavers 56 and 58, frame segmentation units 60 and 62, a channel multiplexing unit 64, a second interleaver 66, and a physical channel mapping unit 68. Yes.

  In the figure, a transmission path encoding unit 52, a first interleaver 56, and a frame segmentation unit 60 perform an interleaving process for logical channel A, and a transmission path encoding unit 54, a transmission path interleaver 58, and a frame segment. The conversion unit 62 performs the interleaving process for the logical channel B. Next, the operation of the multiplexer 50 will be described using the data flow input from the logical channel A. The following description is the same even if the flow of data input from the logical channel B is used.

  The data input from the logical channel A is subjected to transmission path encoding processing by the transmission path encoding 52, and the first interleaver 56 performs interleaving processing when the block size exceeds one frame. Note that the processing in the first interleaver is referred to as interframe interleaving processing. Next, the frame segmentation unit 60 performs frame segmentation for multiplexing. Then, the channel multiplexing unit 64 multiplexes the data with the logical channel B subjected to the same processing.

  The data multiplexed in this way is subjected to an interleaving process in the second interleaver 66. Here, since inter-frame interleaving is performed by the first interleavers 56 and 58, the block size of the interleaver in the second interleaver 66 may be the same as the frame size of the data. Note that the interleaving process in the second interleaver is referred to as an intra-frame interleaving process. Subsequently, the physical channel mapping unit 68 performs mapping to the physical channel and outputs data to the physical channel.

The interframe interleaving process in the first interleaver described above is performed using, for example, the interleaving method shown in FIG. In the figure, F indicates the number of columns of the interleaver, B indicates the number of rows, and C _m indicates data of m columns. As shown in the figure, the input data shown in (a) is written into a B × F matrix as shown in (b). Subsequently, as shown in (c), the columns are randomized (randomized) and read out for each column to obtain interleaved data as shown in (d).

  The method shown in FIG. 5 differs from the example shown in the above-described conventional technique in that the column is randomized. Thereby, the interleaving performance can be improved. Further randomization may be performed. Such an interleaving method for performing randomization is called multiple interleaving. For details, refer to IEICE Technical Report, A.P97-178, RCS97-216, NW97-161 (1998-02), pp. 11-28. 23-30 (Shibuya, Suda, Adachi) can be referred to.

An example of this embodiment of the above randomization is shown in FIG. As shown in the figure, when the interleaving span is 10 ms, the frame length and the span are the same, so the number of columns is 1, and the randomized pattern is input to C ₀ , that is, the first interleaver. The data is output as it is. For data having an interleaving span of 20 ms or more, a randomization pattern as shown in the figure is used. For example, in the case of 80 ms, the columns are switched in the order of C ₀ , C ₄ , C ₂ , C ₆ , C ₁ , C ₅ , C ₃ , C ₇ . The pattern shown in FIG. 6 is a pattern suitable for data transmission, but other patterns can be used for the randomization pattern.

  Next, intraframe interleaving processing in the second interleaver will be described.

As an example of the intraframe interleaving process, it is possible to use the interleaving method described in the above prior art. However, for example, when the number of bits of the logical channel A is smaller than that of the logical channel B, an event as shown in FIG. 7 occurs. (FIG. 7 shows a case where the number of interleaver columns is 16, which is the same as the number of slots in the frame.)
That is, when the multiplexed data is written to the interleave memory, the logical channel A data is written in the middle of the first row because the logical channel A data is small in one frame, and thereafter the logical channel B Therefore, the output data of the data of the logical channel A is shifted to the first half of the output frame, and the error correction capability by transmission path coding cannot be maximized.

Therefore, in the present embodiment, intraframe interleaving processing is performed using the interleaving method shown in FIG. That is, as shown in FIG. 8, data is output after randomizing the columns. As a result, the bits of logical channel A are scattered throughout the frame, and the above event does not occur. FIG. 8 shows a case where the number of columns is 16. More specifically, the process shown in FIG. 9 is performed. As shown in the figure, the input data series shown in (a) is written in the interleaver with 16 columns shown in (b), and patterns (C ₀ , C ₈ , C ₄ , C ₁₂ , C ₂ , C ₁₀ , C ₆ , C ₁₄ , C ₁ , C ₉ , C ₅ , C ₁₃ , C ₃ , C ₁₁ , C ₇ , C ₁₅ ), column randomization is performed as shown in (c). The data shown in (d) is output. In this example, if 1 frame = 16 slots, the number of bits per slot is 10 bits as shown in FIG. Furthermore, a specific example of a 32-row interleaver is shown in FIG. In this case, the number of bits per slot is 20 bits.

Here, as a pattern for randomizing the columns, patterns suitable for data transmission (C ₀ , C ₁₆ , C ₈ , C ₂₄ , C ₄ , C ₂₀ , C ₁₂ , C ₂₈ , C ₂ , C ₁₈ , C ₁₀ , C ₂₆ , C ₆ , C ₂₂ , C ₁₄ , C ₃₀ , C ₁ , C ₁₇ , C ₉ , C ₂₅ , C ₅ , C ₂₁ , C ₁₃ , C ₂₉ , C ₃ , C ₁₉ , C ₁₁ , _{C 27, C 7, C 23} , C 15, C 31) can be used. This pattern is an example when the number of columns is 32 (= 16 × 2). FIG. 11 shows patterns suitable for the transmission path interleaver according to the number of columns. All the patterns described so far are shown in this figure.

  Here, setting the number of columns to 16 or 16 × K (integer) as the second interleaver is effective when one frame has 16 slots. This will be described with reference to FIGS. Here, a case is considered where the information data to be transmitted is half the number of data bits that can be transmitted and the data is transmitted in the first half of the frame.

  FIG. 12 is a diagram illustrating output data when the number of columns = 16 × K (integer). In this figure, Δ indicates a transmission ON / OFF switching point. As shown in this figure, when the number of columns is 16 × K (integer), the slot section and the read sequence of the interleaver match, and it is possible to continuously arrange pilot symbols and data bits.

  FIG. 13 is a diagram showing output data when the number of columns is not 16 × K (integer). In contrast to the case where the number of columns = 16 × K (integer), in this case, the slot interval and the read sequence of the interleaver do not match, and the pilot symbols and data bits are discontinuous, so transmission ON / OFF is shorter. Locations that occur at intervals appear. Since the transmission amplifier for realizing transmission ON / OFF at a short interval increases in complexity, 16 × K (integer) is effective in reducing the complexity of the transmission amplifier.

  When one frame has 15 slots, the same effect as described above can be obtained by setting the number of columns = 15 × K (integer).

  Here, if the interleave block sizes of the data of logical channel A and the two channels of logical channel B are the same or both do not exceed one frame, the first interleaver in FIG. 4 may be omitted. Therefore, in this case, the configuration shown in FIG. 14 can be adopted. As a result, the apparatus can be simplified.

  Note that a demultiplexer corresponding to the multiplexer described so far can be realized by using a deinterleaver, and its configuration will be apparent to those skilled in the art by referring to this specification.

  Next, an embodiment of the present invention corresponding to the second object will be described. This embodiment is suitable for homogenizing the quality of data signals when transmitting data in bursts.

  The configuration of this embodiment will be described below with reference to FIG. FIG. 15 is a block diagram of a data transmission system using the data signal transmission method according to the present invention. As shown in FIG. 15, this data transmission system has a data transmission device 10 on the base station side and a data transmission device 20 on the mobile station side, and both the data transmission devices 10 and 20 can transmit and receive. And bidirectional simultaneous communication is possible. In this example, it is assumed that data transmission is performed from the base station to the mobile station. Therefore, in the data transmission apparatus 10 shown in FIG. 15, the configuration related to transmission is described as a main part, and in the data transmission apparatus 20, the configuration related to reception is described as a main part. The data transmission apparatus 10 on the base station side includes an error detection coding circuit 11, a frame multiplexing circuit 12, an error correction coding circuit 13, an interleaving circuit 14, a slot multiplexing circuit 15, a radio circuit 16, and an antenna 17 as main parts. Have. In addition, the receiving unit 200 and the antenna 18 are provided.

  The error detection encoding circuit 11 generates an error detection code based on the user data UD and adds this to the user data UD. As the error detection code, for example, a 16-bit CRC code is used. Specifically, the user data UD is divided by a predetermined generator polynomial, and the remainder is added to the user data UD. The frame multiplexing circuit 12 receives user data UD to which an error detection code is added, transmission rate information indicating the transmission rate of the user data UD, and tail bits for convolutional coding. The frame multiplexing circuit 12 constitutes a frame in accordance with a predetermined frame format for these data.

  The error correction coding circuit 13 is connected to the frame multiplexing circuit 12 and performs convolutional coding on the data signal composed of frames. The interleave circuit 14 performs bit interleaving on the convolutionally encoded data signal. Thereby, burst-like continuous errors can be prevented. Details of the processing in the interleave circuit 14 will be described later. The slot multiplexing circuit 15 configures a slot based on the data signal subjected to bit interleaving and the pilot signal PS. In this case, pilot signal PS is arranged at the beginning and end of each slot. In the following description, when the pilot signal PS at the head portion and the pilot signal PS at the tail portion are described separately, the former is referred to as the first pilot signal PS1, and the latter is referred to as the second pilot signal PS2. The radio circuit 16 modulates the signal from the slot multiplexing circuit 15 and transmits it via the antenna 17. As a modulation method, for example, spectrum spread modulation, QPSK, or the like may be used.

  Next, the signal transmitted from the data transmission device 10 is taken into the data transmission device 20 via the antenna 21.

  The data transmission apparatus 20 includes a radio circuit 22, a slot demultiplexing circuit 23, a synchronous detection circuit 24, a deinterleave circuit 25, an error correction decoding circuit 26, a frame demultiplexing circuit 27, and an error determination circuit 28. In addition, the transmitter 100 and the antenna 29 are provided.

  The radio circuit 22 amplifies the received signal to a predetermined level. The slot demultiplexing circuit 23 separates the signals constituting each slot into a data signal and a pilot signal PS. The synchronous detection circuit 24 obtains a reference phase in a period from the first pilot signal PS1 to the second pilot signal PS2 based on the first pilot signal PS1 and the second pilot signal PS2 by interpolation. Then, based on the reference phase obtained by interpolation, the synchronous detection circuit 24 demodulates the signal from the slot demultiplexing circuit 23 to generate a data signal.

  The deinterleave circuit 25 has a complementary relationship with the interleave circuit 14 described above, and deinterleaves the synchronously detected data signal. The error correction decoding circuit 26 performs Viterbi decoding of the deinterleaved data signal. The frame demultiplexing circuit 27 separates the output of the error correction decoding circuit 26 into a Viterbi decoded data signal and transmission rate information. The error determination circuit 28 divides the Viterbi-decoded data signal by the generator polynomial used in the error detection coding circuit 11 described above, deletes the error detection code, and outputs user data UD. In this case, if the remainder of the division is 0, it is determined that there is no error. On the other hand, if the remainder is other than 0, it is determined that there is an error.

  Next, the receiving unit 200 provided in the data transmission apparatus 10 has a configuration from the radio circuit 22 to the error determination circuit 28, while the transmission unit 100 provided in the data transmission apparatus 20 includes an error detection. A configuration from the encoding circuit 11 to the radio circuit 16 is provided. In this case, the transmission city 100 and the reception unit 200 perform communication using a communication frequency different from the communication frequency used between the wireless circuit 16 and the wireless circuit 22. Specifically, a signal from the transmission unit 100 is transmitted to the reception unit 200 via the antennas 29 and 18. As a result, bidirectional simultaneous communication can be performed between the data transmission device 10 and the data transmission device 20.

  Note that the interleave circuit 14 performs bit interleaving across a plurality of slots.

  FIG. 16 is a diagram showing a first example of a slot configuration according to the second embodiment. As described above, the slot multiplexing circuit 15 arranges the data signal between the first pilot signal PS1 and the second pilot signal PS2. For example, if the slot period is 1 msec and the data signal transmission rate is 32 kbps, continuous transmission is performed as shown in FIG. On the other hand, when the transmission rate is lower than 32 kbps, burst transmission as shown in (b) and (c) is performed.

  For example, if the transmission rate of the data signal is 16 kbps, the number of bits of the data signal per slot is 16 bits. The slot multiplexing circuit 15 in this example divides a 16-bit data signal into two to generate an 8-bit unit data block DB. Then, as shown in (b), the first data block DB1 is arranged adjacent to the first pilot signal PS1, and the second data block DB2 is started by the slot multiplexing circuit 15, as shown in (b). Is placed in the center of the slot. As shown in (c), even when the transmission speed of the data signal is 8 kbps, a data block in units of 4 bits is generated, and as in the case of 16 kbps, the first and second data blocks DB1, DB2 are generated. Are arranged at predetermined positions shown in FIG.

  Next, the processing of the interleave circuit 14 in the above example will be described in detail. As an interleaving process in the interleave circuit 14, it is first considered to use an interleaver having the same column as the number of slots per frame. However, in this case, problems as described below using FIG. 17 occur.

  FIG. 17 shows a block interleaver with N columns and output data, and each column read in the reading direction corresponds to each of N slots in one frame. That is, the number of interleaver columns matches the number of slots into which pilots are inserted.

  As described above, there is a difference in quality in units of bits in the slot depending on transmission quality and the like. For example, the quality of the vicinity of the pilot signal deteriorates as indicated by x in each slot of the output data in FIG. This x corresponds to x in the interleaver in FIG. When such data is deinterleaved, the quality distribution in the slot is the same as the quality distribution in the frame after deinterleaving even after error correction decoding. That is, the quality of the bits near the beginning of the frame and the bits near the end of the frame are deteriorated. In digital transmission of audio, etc., it is common to place specific information on specific bits. Therefore, even if the average bit error rate of the entire frame does not change, quality deviation occurs in the frame. Therefore, unexpected deterioration of voice transmission quality due to a particular bit being adversely affected causes a problem in providing a mobile communication service.

  In addition, when the quality near the pilot in the slot is better than that at the center, DB2 in FIG. 16 is affected in the same manner as described above. That is, the bit quality at the center of the frame is degraded.

  In order to avoid the above event, in this embodiment, as shown in FIG. 18, an interleaver having the number of columns twice the number of slots in the frame is used. By doing so, the first half of the first slot is the first row, the second half of the first slot is the second row, the first half of the second slot is the third row, the second half of the second slot is the fourth row, etc. Due to the correspondence between the slot and the interleaver, when deinterleaving, the degraded part and the non-degraded part appear alternately in the frame, and the quality of the bits in the frame after error correction decoding is It becomes uniform. Therefore, the above problems can be avoided.

  In this example, if the quality of the transmission path is inferior, the accuracy of the reference phase is improved in the center portion of the slot, so the quality of the second data block DB2 is compared with that of the first data block DB1. Become higher. On the other hand, when the quality of the transmission path is good and the accuracy of the reference phase is dominated by the fading characteristics, the reference phase in the vicinity of the first and second pilot signals PS1 and PS2 is compared with the central portion of the slot. Accuracy is improved. In this case, the quality of the first data block DB1 is higher than that of the second data block DB2. That is, even if the environment of the transmission path changes, the transmission quality of any one of the first and second data blocks DB1 and DB2 is improved. Further, as described above, bit interleaving is performed over a plurality of slots. Therefore, according to this example, the transmission quality is not significantly shifted, and the average quality can be guaranteed.

  Next, FIG. 19 is a diagram showing a second example of the slot configuration according to the present embodiment. The slot multiplexing circuit 15 according to the present embodiment may generate slots shown in FIG. 19 in addition to the slots shown in FIG. In this case, if the transmission speed of the data signal is 16 kbps, the slot multiplexing circuit 15 divides the 16-bit data signal into 8 to generate 1-bit unit data blocks, and the data blocks are equalized. Distribute at intervals. Even when the transmission rate of the data signal is 8 kbps, a data block in units of 1 bit is generated, and each data block is arranged at a predetermined position shown in FIG. 19 as in the case of 16 kbps.

  Even in this case, the interleaving process of the interleave circuit 14 is performed using an interleaver as shown in FIG. Accordingly, there is no deviation in data quality within the frame after deinterleaving. Even when the slot is configured as shown in FIG. 19, even if the environment of the transmission path is changed, the transmission quality is not significantly deviated and the average quality can be guaranteed, as in the case of FIG. .

  Next, FIG. 20 is a diagram showing a third example of the slot configuration according to the present embodiment. The slot multiplexing circuit 15 according to the present embodiment may generate slots shown in FIG. 20 in addition to the slots shown in FIGS. In this case, if the transmission speed of the data signal is 16 kbps or 8 kbps, the slot multiplexing circuit 15 places the data signal in the central portion of the slot in the first slot, and the data signal in the second slot. Arranged adjacent to one pilot signal PS1. Thereafter, these are alternately repeated to form the entire slot.

  Even in this case, the interleaving process of the interleave circuit 14 is performed using an interleaver as shown in FIG. Accordingly, there is no deviation in data quality within the frame after deinterleaving. Also in this case, since bit interleaving over a plurality of slots is performed, the quality of the data signal can be averaged regardless of whether the quality of the transmission path is high or low. When the transmission rate is 8 kbps, data signals may be sequentially arranged at each position obtained by dividing the slot into four equal parts.

  In the above embodiment, the case where the pilot signal is time-multiplexed has been shown, but as shown in FIG. 21, the pilot is transmitted using a physical channel different from the physical channel for transmitting data. (Transmitted in parallel with data) and channel estimation in the same slot section (estimation of the reference phase used for synchronous detection).

  Next, an example in which the multiplexing method of the present invention is applied to the data signal transmission apparatus shown in FIG. 15 corresponding to the third object of the present invention will be described. For example, in the data signal transmitting apparatus 10 shown in FIG. 15, this can be realized by replacing the circuits of the constituent elements 11 to 14 with the multiplexing apparatus 50 of the present invention and adding necessary circuits. In this case, as the second interleaver, an interleaver whose number of columns is twice the number of slots per frame is used to randomize the columns.

  In this configuration, when the number of transmission data bits is small, there is an effect that the bits are evenly distributed in the frame and the bit quality in the frame is uniform. That is, as shown in FIG. 22, when the number of columns is the same as the number of slots, the transmission bits are always arranged in front of the slots, and the average bit error rate increases, but as shown in FIG. When the number of columns is twice the number of slots, the transmission bits are arranged at the ends of the slots, so that the average bit error rate can be reduced as compared with FIG.

  Also, by performing the interleaving process shown in FIG. 24, the effect of uniformly distributing bits within the frame and making the bit quality within the frame uniform can be obtained regardless of the number of transmission data bits per frame. Can do.

  22 to 24 show the case where 1 frame = 16 slots and the number of columns = 32, the same effect can be obtained when 1 frame = 15 slots and the number of columns = 30.

  Further, when 1 frame = 16 slots and the number of columns = 32, it is possible to further enhance the effect of flattening the bit quality in the frame by performing a partial replacement operation of the columns in the interleaver as shown in FIG. is there.

  More specifically, this operation applies column randomization processing to the 32-column interleaver shown in FIG. 25A, and replaces the column portion shown in the figure with respect to the column in the state of FIG. (C) shows a state in which the data in the interleaver after the randomization processing is mapped to each slot, and the above replacement corresponds to the replacement of the hatched portion shown in (c). Note that ◯ and x in (c) indicate the quality of the corresponding bit position in each slot.

  When such replacement is not performed, the data after deinterleaving becomes the bit string shown in (d) of FIG. 25, and adjacent bits do not alternately become XX, but become XX in units of 15 bits, and error correction is performed. Even after decoding, the effect of flattening the bit quality cannot be obtained.

  On the other hand, when the above replacement operation is executed, the bit string is as shown in (e) of FIG. 25, and O and X appear alternately every two bits. It is possible to obtain an effect very similar to the repetition of 1 and 2 for every 2 bits.

  In the above replacement processing, the location of the replacement operation is selected so that the distribution of the average inter-bit distance does not change. Therefore, error correction by channel coding is performed without shifting the bits of a certain channel within the frame. It is also possible to obtain an effect that maximizes the ability.

Next, a case where the number of slots per frame is 15 will be described. When the number of slots per frame is 15, by setting the number of interleaver columns to 30, it is possible to obtain both the above-described effects of flattening bit quality and distributing bits. In this case, as a method of not performing the replacement operation as described above, a random pattern for 30 columns (C ₀ , C ₁₀ , C ₂₀ , C ₄ , C ₁₄ , C ₂₄ , C ₈ , C ₁₈ , C ₂₈ , C ₂ , C ₁₂ , C ₂₂ , C ₆ , C ₁₆ , C ₂₆ , C ₁ , C ₁₁ , C ₂₁ , C ₅ , C ₁₅ , C ₂₅ , C ₉ , C ₁₉ , C ₂₉ , C ₃ , C ₁₃ , C ₂₃ , C ₇ , C ₁₇ , C ₂₇ ) and the method shown in the example of FIG. In the case of bit quality as shown in FIG. 27 showing a state in which the data after interleaving processing is mapped to each slot by performing the interleaving processing shown in FIG. 26, the data arrangement after deinterleaving is shown in (a). It becomes like this. In other words, XX repeats with 1 to 2 bits. Therefore, both effects described above can be obtained.

  In the case of 1 frame = 15 slots, the method of performing the replacement operation is as shown in FIG.

  First, column randomization processing is performed on the 30 column interleaver shown in FIG. This randomization uses an interleave pattern corresponding to 30 columns shown in FIG. For the columns in the state (b) after randomization, the column portion shown in FIG. (C) shows a state in which the data in the interleaver after the randomization processing is mapped to each slot, and the above replacement corresponds to the replacement of the hatched portion shown in (c). Note that ◯ and x in (c) indicate the quality of the corresponding bit position in each slot.

  When such replacement is not performed, the data after deinterleaving becomes the bit string shown in (d) of FIG. 28, and adjacent bits are not alternately circled, and the bit quality is flat even after error correction decoding. It is not possible to obtain the effect of crystallization.

  On the other hand, when the above replacement operation is executed, the bit string is as shown in (e) of FIG. 28, and it is possible to obtain an effect very close to the repetition for each bit.

The above-described column randomization processing is a pattern after column replacement (C ₀ , C ₂₀ , C ₁₀ , C ₅ , C ₁₅ , C ₂₅ , C ₃ , C ₁₃ , C ₂₃ , C ₈ , C ₁₈ , C _{28, C 1, C 11,} C 21, C 6, C 16, C 26, C 4, C 14, C 24, C 19, C 9, C 29, C 12, C 2, C 7, C 22, C ₂₇ , C ₁₇ ).

  In the above replacement processing, the location of the replacement operation is selected so that the distribution of the average inter-bit distance does not change. Therefore, error correction by channel coding is performed without shifting the bits of a certain channel within the frame. It is also possible to obtain an effect that maximizes the ability.

  When one frame has 16 slots, the number of interleaver columns is set to 32, and both of the above effects can be obtained by performing partial column replacement. When one bit is 15 slots, the number of interleaver columns is set to 30. As is apparent from the fact that both of the above effects are obtained, by performing the partial replacement operation of the columns as necessary according to the number of columns of the interleaver (twice the number of slots) determined from the number of slots in one frame. Both the bit quality flattening and the bit dispersion can be obtained.

  As described above, according to the multiplexing apparatus of the present invention, even when the number of multiplexed channel bits is small, bits are mapped to the entire frame, and the error correction capability by transmission path coding can be maximized. It is possible to obtain a multiplexing device. Moreover, since a common interleaver is used for each channel, the hardware scale can be reduced.

  For the interleaver used in the multiplexing apparatus of the present invention, the first interleaver determines the number of columns if the interleaving span is determined, and for the second interleaver, the number of columns may be the number of slots in the frame or an integer multiple thereof. Once the number of columns is determined, the pattern is determined. Therefore, according to the present invention, the number of patterns to be determined can be reduced. Further, the number of columns of the second interleaver is set to the number of slots of the frame or an integer multiple thereof (15 if the frame is 15 slots, or an integer multiple thereof, or 16 if the frame is 16 slots, or an integer multiple thereof). Therefore, since the pilot symbols and the data bits can be continuously arranged, the apparatus can be simplified as compared with other methods.

  Further, according to the data signal transmission method of the present invention, since data is distributed and arranged in slots and an interleaving method suitable for such arrangement is used, the data transmission error rate can be reduced, and the frame It is possible to flatten the bit quality inside.

  Furthermore, it is possible to provide a device having both effects in the multiplexing method and the data signal transmission method of the present invention by performing column partial replacement operation as necessary depending on the number of columns of the interleaver.

  The present invention is not limited to the above-described embodiments, and it is needless to say that various changes can be made without departing from the scope of the invention.

It is a figure which shows an example of the interleaving method in a prior art. It is a block diagram of the multiplexing apparatus in a prior art. It is a figure which shows the structure of the slot concerning the data signal transmission in a prior art. It is a block diagram of the multiplexing apparatus in the embodiment of the present invention. It is a figure which shows the interleaving method in the multiplexing apparatus in embodiment of this invention. It is a figure which shows the randomization pattern of the column in a 1st interleaver. It is a figure for demonstrating the interleaving method of a 2nd interleaver. (Conventional method) It is a figure for demonstrating the interleaving method of the 2nd interleaver in embodiment of this invention. It is a figure which shows the specific example of the interleaving process in a 2nd interleaver. It is a figure which shows the specific example of the interleaving process in a 2nd interleaver. It is a figure which shows the column randomization pattern suitable for transmission-line interleaving. It is a figure for demonstrating the effect by making the number of columns of a 2nd interleaver into a multiple of 16. It is a figure which shows the case where the column number of a 2nd interleaver is not made a multiple of 16. It is a figure which shows the other example of the multiplexing apparatus in embodiment of this invention. It is a block diagram for demonstrating the data transmission system using the data signal transmission method in embodiment of this invention. It is a figure which shows the 1st example of a structure of the slot concerning embodiment of this invention. It is a figure for demonstrating a problem when the number of slots and the number of columns are the same in the interleaving process of the interleave circuit. It is a figure for demonstrating the interleaving process of the interleaving circuit 14 in embodiment of this invention. It is a figure which shows the 2nd example of a structure of the slot concerning embodiment of this invention. It is a figure which shows the 3rd example of a structure of the slot concerning embodiment of this invention. It is a figure for demonstrating parallel pilot transmission. It is a figure for demonstrating the interleaving method in the case of combining the multiplexing apparatus and data signal transmission apparatus in embodiment of this invention. (Problem when the number of columns is 16) It is a figure for demonstrating the interleaving method in the case of combining the multiplexing apparatus and data signal transmission apparatus in embodiment of this invention. (Effect when the number of columns is 32) It is a figure for demonstrating the interleaving method in the case of combining the multiplexing apparatus and data signal transmission apparatus in embodiment of this invention. It is an interleaving method in the case of combining the multiplexing apparatus and data signal transmission apparatus in embodiment of this invention, Comprising: It is a figure for demonstrating the method of performing partial replacement | exchange operation | movement of a column. (1 frame = 16 slots) It is a figure for demonstrating the interleaving method in the case of combining the multiplexing apparatus and data signal transmission apparatus in embodiment of this invention. (1 frame = 15 slots) It is a figure which shows the state which mapped the data after the interleaving process to each slot in the case of 1 frame = 15 slots. It is a figure for demonstrating the method of performing partial replacement operation of a row | line | column in the case of 1 frame = 15 slots.

Claims (24)

An interleaving method in a transmitting apparatus that multiplexes a plurality of information data, interleaves the multiplexed signals using a matrix-structured interleaver and then stores them in a slot, and transmits a signal of a frame constituted by a plurality of slots,
The number of columns of the matrix is an integer multiple of the number of slots in the one frame (the integer is an integer greater than 1);
Write the multiplexed signal to the matrix;
Replacing the written signal in units of columns based on a predetermined rule,
An interleaving method, wherein the signal after replacement is read from the matrix. An interleaving method in a transmitting apparatus that multiplexes a plurality of information data, interleaves the multiplexed signals using a matrix-structured interleaver and then stores them in a slot, and transmits a signal of a frame constituted by a plurality of slots,
The number of columns of the matrix is an integer multiple of the number of slots in the one frame (the integer is an integer greater than 1);
Write the multiplexed signal to the matrix;
Replacing the written signal in units of columns based on a predetermined rule,
Read the signal after replacement from the matrix,
The read signal is stored in a slot, and a frame signal composed of a plurality of slots is transmitted.
An interleaving method comprising transmitting a pilot signal. An interleaving method in a transmitting apparatus that multiplexes a plurality of information data, interleaves the multiplexed signals using a matrix-structured interleaver and then stores them in a slot, and transmits a signal of a frame constituted by a plurality of slots,
The number of columns of the matrix is an integer multiple of the number of slots in the one frame (the integer is an integer greater than 1);
Write the multiplexed signal to the matrix;
Replacing the written signal in units of columns based on a predetermined rule,
Read the signal after replacement from the matrix,
An interleaving method comprising: adding a pilot signal to information data including the read signal and placing the pilot signal in a slot, and transmitting a frame signal composed of a plurality of slots. An interleaving method in a transmitting apparatus that multiplexes a plurality of information data, interleaves the multiplexed signal using a matrix-structured interleaver and then stores the multiplexed signal in a slot, and transmits a frame signal composed of a plurality of slots,
The number of columns of the matrix is an integer multiple of the number of slots in the one frame (the integer is an integer greater than 1);
Write the multiplexed signal to the matrix;
Replacing the written signal in units of columns based on a predetermined rule,
Read the signal after replacement from the matrix,
The read signal is stored in a slot, and a frame signal composed of a plurality of slots is transmitted.
A pilot signal is transmitted using a physical channel different from a physical channel for transmitting a signal of the frame.   5. The interleaving method according to claim 1, wherein the signals read from the matrix are distributed in the slots so as to include at least an end and a center in the slots. A transmission device that includes information data in a slot and transmits the information data using a frame composed of a plurality of the slots,
A plurality of transmission path encoders that respectively encode a plurality of input information data;
A channel multiplexer that multiplexes a plurality of transmission-line encoded signals;
A matrix interleaver for interleaving the multiplexed signals;
The interleaver has a function of exchanging bit positions of written signals in units of columns, and is a matrix of columns of integer multiples (integers are integers greater than 1) of the number of slots constituting one frame. A transmitting device characterized by being. A transmission device that includes information data in a slot and transmits the information data using a frame composed of a plurality of the slots,
A plurality of transmission path encoders that respectively encode a plurality of input information data;
A channel multiplexer that multiplexes a plurality of transmission-line encoded signals;
An interleaver having a matrix structure for interleaving multiplexed signals;
Including the interleaved signal and the radio circuit that modulates the pilot signal,
The interleaver has a function of exchanging bit positions of written signals in units of columns, and is a matrix of columns of integer multiples (integers are integers greater than 1) of the number of slots constituting one frame. A transmitting device characterized by being. A transmission device that includes information data in a slot and transmits the information data using a frame composed of a plurality of the slots,
A plurality of transmission path encoders that respectively encode a plurality of input information data;
A channel multiplexer that multiplexes a plurality of transmission-line encoded signals;
An interleaver having a matrix structure for interleaving multiplexed signals;
A slot multiplexing circuit that inserts a pilot signal indicating a reference phase of modulation into each slot including the interleaved signal,
The interleaver has a function of exchanging bit positions of written signals in units of columns, and is a matrix of columns of integer multiples (integers are integers greater than 1) of the number of slots constituting one frame. A transmitting device characterized by being. A transmission device that includes information data in a slot and transmits the information data using a frame composed of a plurality of the slots,
A plurality of transmission path encoders that respectively encode a plurality of input information data;
A channel multiplexer that multiplexes a plurality of transmission-line encoded signals;
An interleaver having a matrix structure for interleaving multiplexed signals;
A radio circuit that modulates a pilot signal transmitted using a physical channel different from a physical channel that modulates the interleaved signal and transmits the interleaved signal;
The interleaver has a function of exchanging bit positions of written signals in units of columns, and is a matrix of columns of integer multiples (integers are integers greater than 1) of the number of slots constituting one frame. A transmitting device characterized by being.   10. The transmitter according to claim 6, wherein the transmitter has a function of distributing and interleaving the interleaved signal in the slot so as to include at least an end and a central portion in the slot. A method of interleaving multiplexed symbols and transmitting a frame including a slot that holds at least a portion of the interleaved symbols,
Storing the multiplexed symbols as a plurality of groups in a memory;
The step of reading the symbols from the same predetermined position in each group is repeated until all the symbols stored in the memory are read from the memory, and the read symbols are arranged in a plurality of slots.
A method of transmitting the plurality of slots on a predetermined physical channel;
The number of symbols of each group in the plurality of groups is an integral multiple of the number of slots constituting one frame (the integer is an integer greater than 1). A method of interleaving multiplexed symbols and transmitting a frame including a slot that holds at least a portion of the interleaved symbols,
Storing the multiplexed symbols as a plurality of groups in a memory;
The step of reading the symbols from the same predetermined position in each group is repeated until all the symbols stored in the memory are read from the memory, and the read symbols are arranged in a plurality of slots.
Transmitting the plurality of slots on a predetermined physical channel;
A method of transmitting pilot symbols,
The number of symbols of each group in the plurality of groups is an integral multiple of the number of slots constituting one frame (the integer is an integer greater than 1). A method of interleaving multiplexed symbols and transmitting a frame including a slot that holds at least a portion of the interleaved symbols,
Storing the multiplexed symbols as a plurality of groups in a memory;
The step of reading the symbols from the same predetermined position in each group is repeated until all the symbols stored in the memory are read from the memory, and the read symbols are added to pilot symbols and arranged in a plurality of slots.
A method of transmitting the plurality of slots on a predetermined physical channel;
The number of symbols of each group in the plurality of groups is an integral multiple of the number of slots constituting one frame (the integer is an integer greater than 1). A method of interleaving multiplexed symbols and transmitting a frame including a slot that holds at least a portion of the interleaved symbols,
Storing the multiplexed symbols as a plurality of groups in a memory;
The step of reading the symbols from the same predetermined position in each group is repeated until all the symbols stored in the memory are read from the memory, and the read symbols are arranged in a plurality of slots.
A method of transmitting the plurality of slots using a physical channel different from a physical channel for transmitting pilot symbols,
The number of symbols of each group in the plurality of groups is an integral multiple of the number of slots constituting one frame (the integer is an integer greater than 1).   The method according to claim 11, wherein the predetermined position is determined by a predetermined rule.   12. The step of arranging the read symbols in a plurality of slots, wherein at least some of the interleaved symbols are distributed and arranged in the slots so as to include at least an end and a central portion in the slots. 16. The method according to any one of 15 to 15.   17. A method as claimed in any one of claims 11 to 16, wherein the symbols in the slot are spread spectrum modulated. A transmission device for transmitting an interleaved multiplexed signal as a frame including a plurality of slots,
An encoder that encodes content data into multiplexed symbols;
A memory for storing the multiplexed symbols as a plurality of groups;
Repeating a step of reading symbols from the same predetermined position in each group until all the symbols stored in the memory are read from the memory, and arranging the read symbols in a plurality of slots;
A circuit for modulating the symbols arranged in the plurality of slots,
The number of symbols in each group in the plurality of groups is an integral multiple of the number of slots constituting one frame (the integer is an integer greater than 1). A transmission device for transmitting an interleaved multiplexed signal as a frame including a plurality of slots,
An encoder that encodes content data into multiplexed symbols;
A memory for storing the multiplexed symbols as a plurality of groups;
Repeating a step of reading symbols from the same predetermined position in each group until all the symbols stored in the memory are read from the memory, and arranging the read symbols in a plurality of slots;
A circuit for modulating a symbol arranged in the plurality of slots and modulating a pilot symbol,
The number of symbols in each group in the plurality of groups is an integral multiple of the number of slots constituting one frame (the integer is an integer greater than 1). A transmission device for transmitting an interleaved multiplexed signal as a frame including a plurality of slots,
An encoder that encodes content data into multiplexed symbols;
A memory for storing the multiplexed symbols as a plurality of groups;
A mechanism of repeating the step of reading symbols from the same predetermined position in each group until all the symbols stored in the memory are read from the memory, and arranging the read symbols in a plurality of slots by adding pilot symbols When,
A circuit for modulating the symbols arranged in the plurality of slots,
The number of symbols in each group in the plurality of groups is an integral multiple of the number of slots constituting one frame (the integer is an integer greater than 1). A transmission device for transmitting an interleaved multiplexed signal as a frame including a plurality of slots,
An encoder that encodes content data into multiplexed symbols;
A memory for storing the multiplexed symbols as a plurality of groups;
Repeating a step of reading symbols from the same predetermined position in each group until all the symbols stored in the memory are read from the memory, and arranging the read symbols in a plurality of slots;
A circuit that modulates symbols arranged in the plurality of slots and modulates pilot symbols transmitted using a physical channel different from a physical channel that transmits the plurality of slots;
The number of symbols in each group in the plurality of groups is an integral multiple of the number of slots constituting one frame (the integer is an integer greater than 1).   The transmission apparatus according to any one of claims 18 to 21, further comprising an interleaving mechanism that determines the predetermined position according to a predetermined rule.   The mechanism for arranging the read symbols in a plurality of slots distributes and arranges at least a part of the interleaved symbols in the slots so as to include at least an end and a central part in the slots. 23. The transmission device according to any one of items 22 to 22.   24. The transmission apparatus according to claim 18, wherein the circuit performs spread spectrum modulation on a symbol in the slot.