JP2007035213A - Semiconductor storage device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device enhancing the miniaturization while preventing extension of a write period. <P>SOLUTION: The semiconductor storage device is formed with a sidewall memories and furnished with memory cells wherein bit lines are connected by a virtual grounding method. Input data stored in a shift register 102 are converted by a data conversion circuit 104. By the data conversion circuit 104, the input data are converted to conversion data having no existence of "0" data between "1" data and "1" data included in a data row, or having existence of even pieces of "0" data. By write voltage control circuit 109, voltages of the bit lines are set based on the conversion data successively input by latch circuits 105 and on array edge voltages output from an array terminal voltage control circuit 108. Voltages are applied to each bit line by write voltage applying circuits 110. For the adjacent memory cells, the write is alternately carried out to first accumulation nodes and second accumulation nodes. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device that is connected to a bit line by a virtual ground method and includes a nonvolatile asymmetric memory cell, for example, a semiconductor memory device that includes a sidewall memory.

  Recently, an electronic device having a function of storing a still image or a moving image and long-time audio information is increasing. Examples of such electronic devices include a digital camera, a car navigation system, a mobile phone, an electronic notebook, a home game device, and a silicon audio player. These electronic devices use semiconductor storage devices for data storage and code storage applications, and in particular, non-volatile memories such as flash memories that do not lose data even when the power is turned off or the batteries are consumed. Many are used.

  As a semiconductor memory device of this type, there has heretofore been a device in which input / output terminals of memory cells constituting a memory cell array are connected to a bit line by a virtual ground method in order to increase the capacity. However, in the virtual ground system, adjacent memory cells whose control terminals are connected to the same word line share the same bit line, so when writing to one of the adjacent memory cells, There is a problem that a so-called drain disturb occurs in which charges are accumulated in the other memory cell that does not require writing.

  In order to solve this problem, conventionally, the memory cell array is divided into several in the direction in which the word lines extend, and the number of memory cells connected to each other by the virtual ground bit lines is limited to a predetermined number. A semiconductor memory device has been proposed in which one memory cell is selected and data is written simultaneously. As such a semiconductor memory device, there is one in which a memory cell array is electrically divided using transistors to form a plurality of regions (see, for example, JP-A-2002-279789: Patent Document 1).

  In these semiconductor memory devices, when the memory cell array is divided into z memory cells in the word line direction, the bit line of the semiconductor memory device is larger than that of the fixed ground type semiconductor memory device in which one memory cell shares one bit line. The number can be 2 (z + 1) / 3z. By reducing the number of bit lines, the area of the memory cell array can be reduced and the semiconductor memory device can be downsized. FIG. 20 is a diagram illustrating a result of comparing the areas of the memory cell arrays between the virtual ground semiconductor memory device and the fixed ground semiconductor memory device. In FIG. 20, the vertical axis represents the ratio (%) of the memory cell array area of the virtual ground type semiconductor memory device to the memory cell array area of the fixed ground type semiconductor memory device, and the horizontal axis represents one region of the memory cell array. The number z (number) of memory cells in the word line direction included. As shown in FIG. 20, when the memory cell array is divided into 16 memory cells (in the case of z = 16), the area can be reduced to about 70% as compared with the fixed ground type semiconductor memory device. The device can be effectively downsized.

  However, in the conventional semiconductor memory device, when the memory cell array is divided into z memory cells in the word line direction, the write operation needs to be performed z times (16 times when z = 16). There is a problem that the time is significantly increased. FIG. 20 is a graph showing the magnification of the write time of the virtual ground type semiconductor memory device with respect to the write time of the fixed ground type semiconductor memory device. As apparent from FIG. 20, the write time increases in proportion to the number of memory cells included in one region.

Further, the conventional semiconductor memory device that electrically divides the memory cell array using the above-described transistors requires a region for forming the transistors in the memory cell array, and thus has a problem that the effect of reducing the chip area is small.
JP 2002-279789 A

  Accordingly, an object of the present invention is to provide a semiconductor that can be reduced in size while preventing an increase in writing time despite being connected to a bit line by a virtual ground method and including a nonvolatile asymmetric memory cell. To provide a storage device.

In order to solve the above problems, a semiconductor memory device of the present invention includes a memory cell array in which a plurality of nonvolatile asymmetric memory cells are aligned,
A bit line connected by virtual grounding to the input / output terminals of the plurality of memory cells;
A word line connected to the control terminal of the memory cell;
A word line selection circuit for selecting the word line;
A data conversion circuit that converts input data into conversion data that can be simultaneously written in a plurality or all of the memory cells connected to the word line selected by the word line selection circuit;
An array end voltage setting for setting an array end voltage to be applied to an end bit line of the plurality of bit lines connected to the plurality or all of the memory cells based on the conversion data converted by the data conversion circuit. Circuit,
Based on the conversion data converted by the data conversion circuit, the array end voltage set by the array end voltage setting circuit is applied to the bit line at the end, and the memory cell to be written to A plurality of or all of the plurality of or all of the bit lines are applied such that different voltages are applied to the two connected bit lines, while the same voltage is applied to the two bit lines connected to the memory cells that are not programmed. An applied voltage setting circuit for setting a voltage to be applied to the bit line connected to the memory cell;
And a voltage application circuit for applying the voltage set by the applied voltage setting circuit to the bit lines connected to the plurality or all of the memory cells.

  According to the above configuration, the input data is converted by the data conversion circuit into conversion data that can be simultaneously written in a plurality or all of the memory cells connected to the word line selected by the word line selection circuit. The Based on the converted data, the array end voltage is set by the array end voltage setting circuit. The array end voltage is applied to the bit line at the end, and different voltages are applied to the two bit lines connected to the memory cell to be written, while the write is not performed. The applied voltage setting circuit sets the voltage to be applied to the bit lines connected to the plurality or all of the memory cells so that the same voltage is applied to the two bit lines connected to the memory cells. The The voltage set by the applied voltage setting circuit is applied to the bit lines connected to the plurality or all of the memory cells by the voltage applying circuit. Although the memory cell is connected to the bit line by a virtual ground method and is an asymmetric type nonvolatile memory cell, drain disturbance may occur between the memory cells connected to the same bit line. Is prevented. Therefore, the memory cell array does not need to be divided into a plurality of regions as in the conventional case, so that an increase in writing speed can be prevented, and a chip area can be effectively reduced because a transistor for dividing the region is unnecessary. it can.

  Note that an asymmetric type memory cell has a terminal for applying a high voltage and a terminal for applying a low voltage among two input / output terminals when information is written. When high voltage and low voltage are exchanged between two terminals and applied, information to be written is not written.

In one embodiment, the semiconductor memory device stores the input data, and when receiving a signal indicating completion of writing to the memory cell to be written, an input for resetting the input data corresponding to the memory cell in which the writing is completed A data storage circuit;
An input data reset detection circuit for detecting whether or not the input data of the input data storage circuit is reset;
The input data reset detection circuit includes an input data update circuit that updates input data stored in the input data storage circuit when it is detected that all the input data is reset.

  According to the embodiment, the input data is stored in the input data storage circuit, and the input data storage circuit receives the input data when receiving a signal indicating completion of writing to the memory cell to be written. Reset. Whether or not the input data of the input data storage circuit is reset is detected by the input data reset detection circuit. When the input data reset detection circuit detects that all input data has been reset, the input data update circuit determines that the input data update circuit has completed writing all the input data that needs to be written to the memory cell. The input data stored in the data storage circuit is updated. As a result, the input data is quickly and reliably written to the memory cell array in accordance with the amount of data written to the memory cell.

The semiconductor memory device according to one embodiment stores the conversion data, and when receiving a signal indicating completion of writing to the memory cell to be written, the conversion that resets the conversion data corresponding to the memory cell that has been written A data storage circuit;
A conversion data reset detection circuit for detecting whether or not the conversion data of the conversion data storage circuit is reset;
When the conversion data reset detection circuit detects that all of the conversion data has been reset, the conversion data reset detection circuit includes a conversion data update circuit that updates the conversion data stored in the conversion data storage circuit.

  According to the embodiment, the conversion data obtained by converting the input data by the data conversion circuit is stored in the conversion data storage circuit. The conversion data storage circuit resets the conversion data upon receiving a signal indicating completion of writing to the memory cell to be written. Whether or not the conversion data in the conversion data storage circuit has been reset is detected by the conversion data reset detection circuit. When the conversion data reset detection circuit detects that all of the conversion data is reset, the conversion data update circuit determines that writing of all the conversion data that needs to be written to the memory cell is completed. The conversion data stored in the conversion data storage circuit is updated. Thereby, when the conversion data obtained by converting the input data is composed of a plurality of data strings, all of the plurality of data strings are surely written in the memory cell array.

  In one embodiment, the memory cell is formed of a side wall memory.

  According to the embodiment, the sidewall memory has two storage units in one memory cell, so that the degree of integration of the semiconductor storage device can be effectively increased. The sidewall memory is formed on each of two source / drain regions, a channel region formed between the two source / drain regions, a gate formed on the channel region, and both sides of the gate. Charge holding regions, and by controlling the potentials of the two source / drain regions and the gate, respectively, the charge holding states of the two charge holding regions are controlled separately, so that information of two or more values can be obtained. A memory that can be stored. Here, when paying attention to one of the charge holding regions, it is specified which of the two source / drain regions the high voltage and the low voltage should be applied, and the high voltage and the low voltage are not interchangeable. This sidewall memory is asymmetric.

A semiconductor memory device according to an embodiment includes a memory cell selection circuit that selects every predetermined number of memory cells in the word line direction among the memory cells of the memory cell array,
The conversion data is written into the memory cell connected to the word line selected by the word line selection circuit and selected by the memory cell selection circuit.

  According to the embodiment, since the memory cell is connected to the bit line by the virtual ground method, only a predetermined number of memory cells can be read simultaneously. In accordance with the number of memory cells that can be read simultaneously, the memory cell selection circuit selects the predetermined memory cells, and writes the conversion data into the selected memory cells. As a result, the data write operation and the data read operation can be executed using a circuit having a similar configuration. For example, the read circuit and the verify circuit can be shared. Thereby, the circuit of the semiconductor memory device can be simplified.

  In the semiconductor memory device according to one embodiment, the conversion data has no value between the value for writing to the memory cell and the value for not writing to the memory cell, or the value to the memory cell. This data is an even number of values that are not written.

  According to the embodiment, conversion data that can be simultaneously written in a plurality of asymmetrical memory cells of the virtual ground system can be obtained.

  An electronic apparatus according to the present invention includes the semiconductor memory device.

  According to the above configuration, since the semiconductor memory device having a relatively high information writing speed and a relatively small chip area is provided, relatively large-scale input information can be stored at a high speed, and a small electronic device can be provided. can get.

  As described above, the semiconductor memory device of the present invention converts the input data into conversion data that can be simultaneously written in a plurality or all of the memory cells connected to the word line selected by the word line selection circuit. Based on the circuit and the conversion data converted by this data conversion circuit, the array end voltage set by the array end voltage setting circuit is applied to the bit line at the end, and the memory cell to be written to Different voltages are applied to the two connected bit lines, while the same voltage is applied to the two bit lines connected to the memory cells that are not to be programmed. Since an application voltage setting circuit that sets a voltage to be applied to the connected bit line is provided, an asymmetrical memory cell connected to the bit line by a virtual ground method is provided. For multiple connected or all memory cells in serial word lines, it can be simultaneously written to the conversion data. Further, it is possible to prevent drain disturbance from occurring between memory cells connected to the same bit line. Therefore, the memory cell array does not need to be divided into a plurality of regions as in the conventional case, so that an increase in writing speed can be prevented, and a chip area can be effectively reduced because a transistor for dividing the region is unnecessary. it can.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a block diagram showing a semiconductor memory device according to the first embodiment of the present invention. 2A to 5B are circuit diagrams illustrating examples of circuits included in the semiconductor memory device.

  As shown in FIG. 1, this semiconductor memory device has a plurality of nonvolatile memory cells MC11, MC12,... MCm (k−1), MCmk arranged in a matrix of m rows × k columns. A memory cell array 100 is provided. The memory cells MC11,... MCmk are constituted by side wall memories to be described later. In the memory cell array 100, a plurality of word lines WL1 to WLm that are connected to control gates of memory cells arranged in the same row and extend in the row direction are arranged in the column direction. In the memory cell array 100, input / output terminals of memory cells arranged in the same column, that is, a plurality of bit lines BL0 to BLk extending in the column direction by connecting the source and drain to each other are arranged in the row direction. . The bit lines BL0 to BLk are connected to the memory cells MC11 to MCmk by a virtual ground method. The word lines WL1 to WLm are selected by a row decoder 101 as a word line selection circuit. In addition, the input data is latched under the control of the input control circuit 111, and the shift as an input data storage circuit that outputs the input data to be written to each memory cell ("0" and "1" if binary) is output. A register 102 (an example of a circuit diagram in FIG. 2A) is provided. A write end detection circuit 103 (an example of a circuit diagram shown in FIG. 2B) is provided for detecting the completion of writing of all the input data based on the input data stored in the shift register 102. Input data from the shift register 102 is converted into conversion data that can be simultaneously written in a plurality of memory cells by a data conversion circuit 104 (FIG. 3 is an example of a circuit diagram). The conversion data is held in a latch circuit 105 (an example of a circuit diagram in FIG. 4A) as a conversion data storage circuit under the control of the latch circuit control unit 107. Based on the conversion data stored in the latch circuit 105, a divisional write end detection circuit 106 (an example of a circuit diagram shown in FIG. 4B) that detects completion of writing of all the conversion data is provided. In addition, an array end voltage control circuit 108 (an example of a circuit diagram is shown in FIG. 4C) for setting the voltage of the bit line BL0 at the end of the memory cell array is provided. Further, a write voltage control as an applied voltage setting circuit for setting a voltage to be applied to each bit line BL1, BL1,... BLk based on the data from the latch circuit 105 and the voltage of the bit line BL0 at the end. A circuit 109 (an example of a circuit diagram is FIG. 5A) is provided. The voltage set by the write voltage control circuit 109 is applied to the bit lines BL0, BL1,..., BL (k−1), by a write voltage application circuit 110 (an example of a circuit diagram is FIG. 5B) as a voltage application circuit. The voltage is applied to BLk. Note that the shift register 102 may be replaced with a general latch circuit. In this embodiment, the row to which the memory cell of interest belongs is i, and the column to which it belongs is j. That is, i = 1 to m and j = 0 to k.

  FIG. 2A is a circuit diagram showing an example of the components of the shift register 102. FIG. 2A shows a one-stage SR of the shift register 102 that holds one digit of input data corresponding to a memory cell to be written. In FIG. 2A, reference numeral 201 denotes a CMOS transmission gate that is turned on at the rising edge of the φshift pulse, and reference numeral 202 denotes a CMOS transmission gate that is turned on at the falling edge of the φshift pulse. 203 is an inverter. The two inverters 203 on the output side of the CMOS transmission gate 201 constitute an inverter pair when the CMOS transmission gate 202 is turned on. Reference numeral 207 denotes a transistor that resets retained data by grounding the output side when the signal SFRST input to the control gate is High. Reference numeral 208 denotes a transistor that resets retained data by grounding the output side when the signal RDATj input to the control gate is High.

  FIG. 2B is a circuit diagram showing an example of the write end detection circuit 103. In FIG. 2B, 211 is a NOR gate, and 212 is an inverter. The output of the previous stage and the output from the shift register 102 are sequentially input to each NOR gate 211, and the PRG_END signal is output when the outputs of all the stages of the shift register 102 are Low. That is, the input data held in the shift register 102 functions as an input data reset detection circuit that detects reset of the input data.

  FIG. 3 is a circuit diagram showing an example of the data conversion circuit 104. In FIG. 3, 301 is a NOR gate, 302 is a NAND gate, 303 is an EX-NOR gate, and 304 is an inverter. The operation of the data conversion circuit 104 in FIG. 3 will be described later.

  FIG. 4A is a circuit diagram showing an example of the latch circuit 105. In FIG. 4A, 401 is a CMOS transmission gate that is turned on at the rising edge of the φlatch pulse, and 402 is a CMOS transmission gate that is turned on at the falling edge of the φlatch pulse. Reference numeral 403 denotes an inverter. The two inverters 403 on the output side of the CMOS transmission gate 401 constitute an inverter pair when the CMOS transmission gate 402 is turned on. Reference numeral 407 denotes a transistor that resets retained data by grounding the output side when the signal LARST input to the control gate is High. Reference numeral 408 denotes a transistor that resets retained data by grounding the output side when the signal RDATj input to the control gate is High.

  FIG. 4B is a circuit diagram showing an example of the divided write end detection circuit 106. In FIG. 4B, 411 is a NOR gate, and 412 is an inverter. The output of the previous stage and the output from the latch circuit 105 are sequentially input to each NOR gate 411, and the DP_END signal is output when the outputs of all the stages of the latch circuit 105 are Low. That is, the conversion data held in the latch circuit 105 functions as a conversion data reset detection circuit that detects reset of the conversion data.

  FIG. 4C is a circuit diagram showing an example of the array end voltage control circuit 108. In FIG. 4C, 421 is a NOR gate, 422 is an inverter, and 423 is an EX-NOR gate. The operation of the array end voltage control circuit 108 will be described later.

  5A is a circuit diagram illustrating an example of the write voltage control circuit 109. In FIG. 5A, reference numeral 501 denotes a CMOS transmission gate that is turned on at the rising edge of the φload pulse, and 502 is turned on at the falling edge of the φload pulse. This is a CMOS transmission gate. Reference numeral 503 denotes an inverter. The two inverters 503 on the output side of the CMOS transmission gate 501 form an inverter pair when the CMOS transmission gate 502 is turned on. Reference numeral 505 denotes an EX-NOR gate to which the conversion data DDj from the latch circuit 105 and the previous-stage output SWj-1 are input. Reference numeral 507 denotes a transistor that resets retained data by grounding the output side when the signal SWRST input to the control gate is High. The write voltage control circuit 109 outputs a high output SWj when the conversion data DDj from the latch circuit 105 and the output SWj-1 at all stages are different from each other.

  FIG. 5B is a circuit diagram showing an example of the write voltage application circuit 110. In FIG. 5B, reference numeral 511 denotes an inverter that inverts a signal from the write voltage control circuit 109. A transistor 512 is turned on by a Low signal to the control gate, and the output value BLj becomes the VP potential when the transistor 512 is turned on. A transistor 513 is turned on by a high signal to the control gate. When the transistor 512 is turned on, the output value BLj becomes V0 potential.

  FIG. 6 is a cross-sectional view showing a side wall memory constituting the memory cells MC11,... MCmk. The sidewall memory 600 functions as a first and a second storage node by storing charges in each of the two silicon nitride films 603a and 603b, and stores 2-bit information. In the sidewall memory 600, a word line 605 functioning as a control gate is formed on a substrate 601 via a gate insulating film 602, and the word line 605 is formed on both sides via a silicon oxide film 606. First and second silicon nitride films 603a and 603b are formed. The first and second silicon nitride films 603a and 603b are connected to the vertical portion extending substantially parallel to the side wall of the word line 605, the lower end of the vertical portion, and substantially parallel to the surface of the substrate 601 and the word line 605. And a lateral portion extending to the side away from the main body, and has a substantially L shape. Silicon oxide films 607 and 607 are provided on the far side of the first and second silicon nitride films 603a and 603b from the word line 605. Thus, by sandwiching the first and second silicon nitride films 603a and 603b between the silicon oxide films 606 and 607, the charge injection efficiency at the time of rewrite operation is increased and a high-speed operation is possible. Two diffusion regions are formed in the substrate 601 in the vicinity of the first and second silicon nitride films 603a and 603b. Specifically, the first diffusion layer is formed so as to overlap a part of the lateral part of the first silicon nitride film 603a and to overlap a part of the lateral part of the silicon nitride film included in the adjacent memory cell. 609. Further, the second diffusion layer 612 is formed so as to overlap a part of the lateral part of the second silicon nitride film 603b and to overlap a part of the lateral part of the silicon nitride film included in the adjacent memory cell. Have The first diffusion layer 609 and the second diffusion layer 612 function as a source region or a drain region, respectively. A channel region is defined between the first and second diffusion layers 609 and 612 functioning as the source region or the drain region. The first diffusion layer 609 is connected to a first bit line 611 formed above the memory cell. On the other hand, the second diffusion layer 612 is connected to a second bit line (not shown).

  The voltage applied to the bit line at the time of writing to the sidewall memory is as shown in Table 1 below.

  As shown in Table 1, when data 0 is written, VP (for example, 5 V) or V0 (for example, 0 V) is applied to both of the two bit lines connected to the memory cell. On the other hand, when data 1 is written, when writing to the first storage node 603a, VP is applied to the first bit line 611 and V0 is applied to the second bit line. In addition, when data 1 is written to the second accumulation node 603b, V0 is applied to the first bit line 611 and VP is applied to the second bit line. In general, the data to be written may be defined as “0” or “1”, but in this specification, the data to be written is defined as “1”. That is, a state in which data is erased from the storage node and no charge is stored in the storage node is called data “0”, and a state in which charge is stored in the storage node and data is stored is “1”. " Further, the charge stored in the storage node and representing data may be a negative charge or a positive charge.

  In a write operation, it is common to hold the word line at the voltage VWL and apply a pulse of the voltage VP to the bit line, but conversely hold the voltage VP of the bit line and apply a pulse of the voltage VWL to the word line. Even with the technique given, writing can be performed. What is important here is that, when data 0 is written, if the voltages of two bit lines connected to the memory cell are the same potential, regardless of the voltage value (as shown in Table 1, VP and Data 0 is written at any point (V0). In general, when data 0 is written, the memory cell remains in the erased state, no charge is taken in or out of the charge accumulation portion of the memory cell, and there is no write disturb. On the other hand, when data 1 is written, if different voltages are applied to the two bit lines connected to the memory cell, data 1 is written regardless of which of the two bit lines has a high potential. is important.

  Regarding writing to a memory cell, depending on the type of flash memory, there is a type in which either of two bit lines may have a high potential, such as an ETOX type memory. The target is an asymmetric memory in which a bit line to which a high potential is to be applied is specified. Such an asymmetric type memory includes a split type memory and a side wall memory. In the side wall memory, as in the present embodiment, one storage cell has two storage nodes, and the storage node to which writing is performed differs depending on which bit line is applied with a high potential. Have

In the semiconductor memory device of FIG. 1 of the present embodiment, a case where data is written to the memory cell connected to the word line WL1 will be described. In the present embodiment, simultaneous writing is performed on one of the two storage nodes for all the k memory cells MC11 to MC1k connected to one word line WL1. When writing to all the memory cells MC11 to MC1k, the voltage values applied to all the bit lines BL0 to BLk are determined so as to satisfy the conditions in Table 1 based on the data to be written to the memory cells MC11 to MC1k. To do. FIG. 7 is a diagram showing the voltage applied to the bit line when data “11100001...” Is written and the storage node where data is written in each of the memory cells MC11, MC12,. It is. As shown in FIG. 7, this data “100100001...” Can be simultaneously written in the memory cells MC 11, MC 12,..., And therefore, the bit lines BL 0, BL 1, etc. generated by the write voltage application circuit 110. The voltage application operation to. As described above, in order to simultaneously write to all the memory cells MC11, MC12,... Connected to the selected bit line BL0, the following two conditions must be satisfied.
(1) There is no “0” data or an even number of “0” data between “1” data and “1” data included in the data string.
(2) The first storage node and the second storage node are alternately selected and sequentially written into adjacent memory cells MC11, MC12,... (Refer to the dotted circles in FIG. 7). .

  The above (1) is a condition to be satisfied by the data to be written, and (2) is a condition to be satisfied when controlling the application to the bit line. The condition (1) can be satisfied by converting the input data by the data conversion circuit 103. The condition (2) can be satisfied by setting the applied voltage by the array end voltage control circuit 108 and the write voltage control circuit 109 based on the data satisfying the condition (1).

  The operation of the semiconductor memory device of FIG. 1 will be specifically described below.

  First, input data DIN is input to the shift register 102 under the control of the input control circuit 111. Specifically, in each stage SR of the shift register of FIG. 2A, SFRST is lowered to release the reset, and the input data is transferred to each stage by giving a pulse-like φshift, so that each digit of the input data Data is stored in each stage SR of the shift register corresponding to the memory cell to be written.

  When the storage of the input data in the shift register 102 is completed, the input data DAj (j = 1 to k: the same applies hereinafter) of each digit is input to the data conversion circuit 104, and the data conversion circuit 104 converts the input data DAj. Execute.

  FIG. 8 is a diagram schematically showing the processing executed by the data conversion circuit 104. First, each digit data constituting the input data Dj is divided into even-numbered data and odd-numbered data from the digit corresponding to the memory cell MC11 (hereinafter referred to as the most significant digit). And odd-numbered data are written in different columns. At this time, even-numbered data and odd-numbered data are written at the same position as the digit position in the input data of each data. Then, in order from the most significant digit side, data constituting the conversion data is selected and extracted from an even-numbered data string (hereinafter referred to as an even-numbered column) or an odd-numbered data string (hereinafter referred to as an odd-numbered column).

  First, attention is focused on data “1” that is closest to the most significant digit. Values from the most significant digit to the data “1” are selected as conversion data as they are. When the data “1” closest to the most significant digit is present in the odd number column, the next lower digit side data is selected from the even number column. When the data on the next lower digit side of the even column is “0”, this data “0” is selected and attention is paid to the data on the lower digit side of the same even column. If the lower digit data is “1”, the data “1” is selected, and the next lower digit data is selected from the odd number column. Thus, paying attention to one lower digit side of the even-numbered column and odd-numbered column in sequence, data “1” is selected, and when data “1” is selected, the data moves to the other column and further lower-order digit data is selected. . Data “0” is replenished in blank digits between the selected values. Thereby, conversion data satisfying the condition (1) is obtained.

  In FIG. 8, the first conversion data thus obtained is “01001001...”. Of the input data “1”, “1” other than “1” of the first conversion data is extracted as “1” of the second conversion data. As a result, the second conversion data becomes “00010010...”. Such processing is executed by the data conversion circuit 104 as shown in FIG.

  When there are a plurality of pieces of conversion data obtained by the data conversion circuit 104 as shown in FIG. 8, the plurality of pieces of conversion data are sequentially written into the memory cells MC11,... MC1k. Specifically, the first and second conversion data in FIG. 8 are written into the memory cells MC11,... MC1k by two write operations.

  The conversion data DCj converted by the data conversion circuit 104 is stored in the latch circuit 105 under the control of the latch circuit control unit 107. Specifically, in the latch circuit 105 shown in FIG. 4A, the reset of the latch circuit 105 is released by the fall of LARST by the latch circuit control unit 107, and the pulse signal φlatch from the latch circuit control unit 107 is released. Therefore, the conversion data DCj is input to each latch circuit 105 and held.

  Data DDj held in each latch circuit 105 is input to the array end voltage control circuit 108 and the write voltage control circuit 109.

  The array end voltage control circuit 108 determines whether the voltage of the bit line at the array end should be VP or V0. Specifically, first, depending on whether the lowest column address CA0 of the address selection signal and the data “1” of the converted data are even-numbered or odd-numbered from the most significant digit, A voltage (VP or V0) to be applied to the bit line BL0 is specified, and a signal AT indicating the value of this voltage is output.

  The write voltage control circuit 109 applies voltages to the other bit lines BL1, BL2,... Based on the signal AT from the array end voltage control circuit 108 and the data DDj from the latch circuit 105. decide. Since the data DDj from the latch circuit 105 satisfies the condition (1), the bit line is set so that adjacent memory cells MC are alternately written into the first storage node and the second storage node. The applied voltage of BL1, BL2,... Can be set. Specifically, in the write voltage control circuit 109 of FIG. 5A, the reset is released by the fall of SWRST from the latch circuit control unit 107, and the data DDj is input by the pulse signal φload from the latch circuit control unit 107. Is done. Based on the output SWj-1 in the previous stage and the data DDj, a signal SWj indicating which voltage VP or V0 is applied to the bit line is output. However, the output AT from the array end voltage control circuit 108 is used as the signal SW0 indicating the voltage at the array end. The write voltage application circuit 110 receives the signals SWj and AT and applies a voltage of VP or V0 to the bit line BLj based on these signals.

  This semiconductor memory device performs a write verify operation in a write operation. Specifically, every time a pulse voltage is applied to the bit lines BL0 to BLk a predetermined number of times, a read circuit (not shown) reads the memory cells MC11 to MC1k and detects a memory cell in which writing has been completed. When any one of the memory cells MC11 to MC1k changes the write data from “0” to “1” and detects that the write is completed, it corresponds to the memory cell for which the write has been completed. RDATj is output from the reading circuit to the shift register 102 and the latch circuit 105. As a result, the predetermined stages of the shift register 102 and the latch circuit 105 are reset, and the data DAj held in the predetermined stage of the shift register 102 and the data DDj held in the predetermined stage of the latch circuit 105 are reset. Here, the data DAj stored in the shift register 102 is detected by the write end detection circuit 103, and the data DDj stored in the latch circuit 105 is detected by the divided write end detection circuit 106.

  The divisional write end detection circuit 106 has a circuit configuration as shown in FIG. 4B, and raises the signal DP_END when all the data DDj held in the latch circuit 105 becomes “0”. When the latch circuit control unit 107 receives the rise of DP_END, it outputs a φlatch pulse to the latch circuit 105. Thus, the second conversion data is input from the data conversion circuit 104 to the latch circuit 105 as new data DCj and held. Here, the latch control circuit 107 functions as a change data update circuit. When the latch circuit control unit 107 receives the rising edge of DP_END, it outputs a φload pulse to the write voltage control circuit 109. As a result, data corresponding to the second conversion data is input from the latch circuit 105 to the write voltage control circuit 109 as new data DDj and held therein. Thus, after the writing of all the first conversion data is completed, the writing of the second conversion data can be started.

  In addition to the circuit configuration as shown in FIG. 4B, the divisional write end detection circuit 106 inputs the stored data DD1 to DDk of each stage of the latch circuit 105 to the NOR gate 901 every predetermined number as shown in FIG. It may be detected whether each of the data DD1 to DDk is “0” by inverting the outputs from the plurality of NOR gates 901 by the inverter 902 and inputting them to the NOR gate 903. However, considering the wiring load and layout shape, the circuit configuration as shown in FIG. 4B is preferable.

  The write end detection circuit 103 has a circuit configuration as shown in FIG. 2B, and raises the signal PRG_END when the data DAj held in each stage of the shift register 102 becomes “0”. . The data DAj of the shift register 102 becomes “0” when writing of all the conversion data (here, the first and second conversion data) converted by the data conversion circuit 104 is completed. When the input control circuit 111 receives the rising edge of the signal PRG_END, it raises SFRST to reset the shift register 102, and then lowers SFRST to release the reset and gives a pulsed φshift to store the input data. To do. Thereby, after the writing of all the conversion data to the memory cell is completed, new input data is stored in the shift register 102, and writing of the new input data can be started. Thus, the input control circuit 111 functions as an input data update circuit.

  In addition to the circuit configuration as shown in FIG. 2B, the write end detection circuit 103 inputs the storage data DA1 to DAk of each stage of the shift register 102 to the NOR gate every predetermined number as in FIG. The output from the NOR gate may be inverted by an inverter and input to the NOR gate. However, considering the wiring load and layout shape, the circuit configuration as shown in FIG. 2B is preferable.

  Note that a known sense amplifier or the like can be used for the reading circuit.

(Second Embodiment)
FIG. 10 is a diagram showing a semiconductor memory device according to the second embodiment of the present invention.

  The semiconductor memory device of the second embodiment has a function of preventing overwriting, and does not have the latch circuit 105, the latch circuit control unit 107, and the divided write end detection circuit 106 of the first embodiment, and performs data conversion. The difference from the semiconductor memory device of the first embodiment is that the output DCj of the circuit 104 is directly input to the array end voltage control circuit 1108 and the write voltage control circuit 1109. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 11A is a circuit diagram of the array end voltage control circuit 1108. In FIG. 11A, 1121 is a NOR gate, 1122 is an inverter, and 1123 is an EX-NOR gate. As shown in FIG. 11A, in the array end voltage control circuit 1108, the output DCj of the data conversion circuit 104 is input to the first stage inverter 1122 and the NOR gate 1121 of each stage.

  FIG. 11B is a circuit diagram of the write voltage control circuit 1109. In FIG. 11B, 1131 is an EX-NOR gate, and 1132 is an inverter. As shown in FIG. 11B, the write voltage control circuit 1109 outputs High SWj when the output SWj-1 at the previous stage and the output DCj of the data conversion circuit 104 are different from each other.

  In the semiconductor memory device of this embodiment, converted data obtained by converting input data by the data conversion circuit 104 is written to the memory cells MCi1 to MCik by one write operation. A signal RDATj is input to a predetermined stage of the shift register 102 from a read circuit (not shown) corresponding to the memory cell MCij for which writing has been completed. Thereby, in the shift register 102, the input data corresponding to the memory cell MCij for which writing has been completed is reset. Thereby, it is possible to prevent the write voltage from being applied again to the memory cell in which writing has been completed through the bit line, thereby preventing excessive writing to the memory cell.

(Third embodiment)
FIG. 12 is a block diagram showing a semiconductor memory device according to the third embodiment of the present invention.

  In the semiconductor memory device of the third embodiment, the number of memory cells to be simultaneously written corresponding to the conversion data is converted to two or less for the conversion data converted by the data conversion circuit 1304. As a result, the conversion data has the condition (1) “0” data does not exist between “1” data and “1” data included in the data string, or an even number of “0” data. Even if “existence” is not satisfied, writing into the memory cell becomes possible.

  The semiconductor memory device of this embodiment is different from the semiconductor memory device of the first embodiment in circuit configurations of a data conversion circuit 1304, a latch circuit control unit 1307, and a write voltage control circuit 1309. In the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 13A is a circuit diagram of the data conversion circuit 1304. The data conversion circuit 1304 converts the input data DA1 to DAk into conversion data DCj in which the number of write data (data “1” in the present embodiment) output at the same time is two or less. The two or less pieces of data DCj need to be set so that there is no “0” between the write data “1” or an even number of “0” as in the data conversion circuit of FIG. Therefore, the circuit configuration is simple. In FIG. 13A, 1311 is a NOR gate, 1312 is an inverter, and 1313 is a NAND gate.

  FIG. 13B is a circuit diagram of the write voltage control circuit 1309. Since the write voltage control circuit 1309 includes two or less data to be simultaneously written included in the conversion data DCj, only the comparison between the conversion data DDj output from the latch circuit 105 and the output SWj-1 of the previous stage is performed. The bit line voltage can be set by. Therefore, the input of φload and SWRST as in the write voltage control circuit 109 in FIG. 5A is not necessary, and a simple circuit configuration can be achieved. In FIG. 13B, 1315 is an EX-NOR gate, and 1316 is an inverter.

  Further, the latch circuit control unit 1307 does not need to output φload and SWRST to the write voltage control circuit 109 as in the first embodiment.

  In the semiconductor memory device of this embodiment, the data conversion circuit 1304 outputs conversion data DCj having two or less write data, and the conversion data DCj is supplied as data DDj via the latch circuit 105 to the write voltage control circuit 1309. Is input. The write voltage control circuit 1309 sets a voltage to be applied to the bit line BLj based on the output AT (SW0) from the array end voltage control circuit 108 and the data DDj. Here, since the same conversion data DCj as the data DDj has two or less write data, the write completion time to the memory cell is different from the case where the conversion data DCj includes three or more write data. There is no need to further convert the remaining write data due to the shift. That is, for example, when writing of one write data to a memory cell out of two pieces of write data is completed, the remaining one write data is stored at any position of the memory cell where writing is performed. You can continue writing. Therefore, input data can be written by the data conversion circuit 1304, the latch circuit control unit 1307, and the write voltage control circuit 1309 having a simple configuration. When the writing of the two or less pieces of write data is completed, DP_END is raised by the divided write end detection circuit 106, φlatch and LARST are output from the latch circuit control unit 1307 to the latch circuit 105, and other conversion data is transferred. Data from the data conversion circuit 1304 is stored in the latch circuit 105.

  In the semiconductor memory device of this embodiment, the number of data included in the conversion data and simultaneously written is two or less. However, even if the number of write data included in the conversion data is two (2 bits), FIG. As shown, the number of times of writing can be reduced to about one third compared with a conventional semiconductor memory device in which input data is written bit by bit. Accordingly, the input data writing time can be effectively reduced. Note that the vertical axis in FIG. 14 represents the average number of writings required for writing the input data, and the horizontal axis represents the number of bits of the input data.

(Fourth embodiment)
FIG. 15 is a block diagram showing a semiconductor memory device according to the fourth embodiment.

  The semiconductor memory device of this embodiment does not write to all the memory cells connected to the selected word line WLi in the semiconductor memory device of the first embodiment, but every nth memory cell. The difference is that writing is performed. In the virtual ground type semiconductor memory device, reading from all the memory cells connected to one word line cannot be performed at the same time, and reading operation is performed simultaneously from at most one memory cell at a time. I can't. Therefore, in this embodiment, the control of the operation is simplified by matching the number of memory cells that are simultaneously written to the number of memory cells that can be simultaneously read. In the verify operation at the time of writing, when the read operation is performed many times to read all the data of the necessary memory cells, a configuration in which data is simultaneously written to all the memory cells as in the first embodiment may be adopted.

  In the fourth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 15, in this semiconductor memory device, a memory cell array 1600 is divided into k areas including n memory cells MCihj in the word line direction. Here, i = 1 to m, h = 1 to k, and j = 1 to n. One write voltage control circuit 1609 is provided for one region of the memory cell array. For the n memory cells MCihj belonging to one of the regions and connected to the same word line WLi, the write voltage control circuit 1609 has two bit lines BLh (j−1) connected to the memory cell MCihj. , BLhj are sequentially set for each memory cell MCihj.

  In addition, in this semiconductor memory device, it is necessary to select an address of the memory cell MCihj in order to perform writing to one n cells (that is, one memory cell MCihj). Therefore, a selection circuit 1611 having a circuit diagram as shown in FIG. 16 is provided. The selection circuit 1611 gives addresses CA1 to CAp (2p = n) in advance, and by raising φsel, the selection signals SEL1 to SELn are output to the write voltage control circuit 1609 to perform the selection operation. . The write voltage control circuit 1609 that has received the selection signals SEL1 to SELn, for the memory cells MCihj corresponding to the selection signals SEL1 to SELn, as shown in the circuit diagram of FIG. 17, bit lines BLh (j−1), BLhj. The voltage value to be applied to is output. In FIG. 16, 1621 and 1622 are NAND gates, and 1623 is an inverter. In FIG. 17, reference numeral 1701 denotes a NAND gate to which selection signals SEL1 to SELn and conversion data DDj are input, and 1702 denotes an inverter. The functions of the other components are the same as those of the write voltage control circuit 109 of the first embodiment.

  The memory cell array 1600, the write voltage control circuit 1609, and the selection circuit 1611 of this embodiment may be used in the semiconductor memory devices of the second and third embodiments. That is, in the second and third embodiments, every n memory cells MCihj may be written.

  Further, in the present embodiment, the number of memory cells MCihj that write simultaneously and the number of memory cells MCihj that read simultaneously do not have to match, for example, the number of memory cells MCihj that write simultaneously, It may be an integral multiple of the number of memory cells MCihj that are simultaneously read.

(Fifth embodiment)
FIG. 18 is a block diagram showing a semiconductor memory device according to the fifth embodiment.

  In the semiconductor memory device of this embodiment, a split gate type memory cell is used for the memory array 1800 as an asymmetric type memory cell. A split gate type memory cell has two gates, a control gate and a floating gate, on a channel between the source and drain of a transistor, and a terminal to which a high voltage is applied and a terminal to which a low voltage is applied during writing. Is a specified asymmetric type memory cell. This embodiment is different from the first embodiment in that the GND level is input as CA0 to the array end voltage control circuit 108. Note that when the level of the write voltage applied to the two terminals of the memory cell is opposite to that in FIG. 18, the VCC level may be input to the array end voltage control circuit 108 as CA0. This embodiment can be applied to the second to fourth embodiments.

(Sixth embodiment)
FIG. 19 is a block diagram showing a digital camera as an electronic apparatus according to the sixth embodiment of the present invention. This digital camera includes the semiconductor memory device according to the first embodiment of the present invention as a flash memory, and stores a photographed image in the flash memory.

  As shown in FIG. 19, in this digital camera, when the power switch 1901 is turned on by the operator, the power supplied from the battery 1902 is transformed to a predetermined voltage by the DC / DC converter 1903 and supplied to each component. The Light entering from the lens 1916 is converted into current by the CCD 1918, converted into a digital signal by the A / D converter 1920, and input to the data buffer 1911 of the video processing unit 1910. The signal input to the data buffer 1911 is subjected to moving image processing by the MPEG processing unit 1913, passes through the video encoder 1914, becomes a video signal, and is displayed on the liquid crystal panel 1922. When the shutter 1904 is pressed by the operator, information in the data buffer 1911 is processed as a still image through the JPEG processing unit 1912 and recorded in the flash memory 1908. In the flash memory 1908, the system program and the like are recorded in addition to the captured image information. The DRAM 1907 is used for temporary storage of data generated in various processing processes of the CPU 1906 and the video processing unit 1910.

  Since the flash memory 1908 records video information, audio information, and the like having a large amount of information, a large amount of data is written, read, and erased. Here, the flash memory 1908 is the semiconductor memory device according to the first embodiment of the present invention, and includes a memory cell array composed of sidewall memories. Therefore, the flash memory 1908 has two storage units in one memory cell, has a high degree of integration, and can employ a virtual grounding method, so that it can be manufactured at low cost. Further, although the flash memory 1908 is a virtual ground system, it can write simultaneously to all the memory cells connected to the same word line while preventing overwriting, so that high-speed writing is possible. It can be performed. Accordingly, the chip area is small and inexpensive, and a high-speed writing flash memory 1908 can be obtained. As a result, a small and inexpensive digital camera capable of storing captured images at high speed can be obtained.

  In this embodiment, a digital camera as an example of an electronic device has been described. However, the flash memory is not limited to a digital camera, and may be a digital recorder, a mobile phone, a car navigation system, an electronic notebook, a home game device, or the like. It can be used for other electronic devices.

1 is a block diagram showing a semiconductor memory device according to a first embodiment of the present invention. It is a circuit diagram which shows a shift register. It is a circuit diagram which shows a write end detection circuit. It is a circuit diagram which shows a data conversion circuit. It is a circuit diagram which shows a latch circuit. It is a circuit diagram which shows the division | segmentation write completion detection circuit. It is a circuit diagram which shows an array terminal voltage control circuit. It is a circuit diagram which shows a write voltage control circuit. It is a circuit diagram which shows a write voltage application circuit. It is sectional drawing which shows the side wall memory which comprises a memory cell. FIG. 10 is a diagram illustrating a state in which data “11100001...” Is written to a series of memory cells. It is the figure which showed typically the process which a data conversion circuit performs. It is a figure which shows the other circuit structure of a division | segmentation write completion detection circuit. It is a figure which shows the semiconductor memory device of 2nd Embodiment. It is a circuit diagram which shows the array terminal voltage control circuit in 2nd Embodiment. It is a circuit diagram which shows the write-voltage control circuit in 2nd Embodiment. It is a figure which shows the semiconductor memory device of 3rd Embodiment. It is a circuit diagram which shows the data conversion circuit in 3rd Embodiment. It is a circuit diagram which shows the write-voltage control circuit in 3rd Embodiment. It is the figure which compared the frequency | count of writing required for writing of input data about the semiconductor memory device of 3rd Embodiment, and the conventional semiconductor memory device. It is a block diagram which shows the semiconductor memory device of 4th Embodiment. It is a circuit diagram which shows the selection circuit in 4th Embodiment. It is a circuit diagram which shows the write-voltage control circuit in 4th Embodiment. It is a block diagram which shows the semiconductor memory device of 5th Embodiment. It is a block diagram which shows the digital camera as an electronic device of 6th Embodiment. FIG. 3 is a diagram in which the comparison of the area of the memory cell array and the comparison of the write time are performed between the virtual ground type semiconductor memory device and the fixed ground type semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory cell array 101 Row decoder 102 Shift register 104 Data conversion circuit 105 Latch circuit 106 Divided write end detection circuit 107 Latch circuit control part 108 Array edge voltage control circuit 109 Write voltage control circuit 110 Write voltage application circuit 111 Input control circuit MC11, MC12 , ..., MC1 (k-1), MC1k, ..., MCm (k-1), MCmk memory cells WL1, ..., WLm word lines BL0, BL1, ..., BLk bit lines

Claims (7)

A memory cell array in which a plurality of nonvolatile asymmetric memory cells are aligned;
A bit line connected by virtual grounding to the input / output terminals of the plurality of memory cells;
A word line connected to the control terminal of the memory cell;
A word line selection circuit for selecting the word line;
A data conversion circuit that converts input data into conversion data that can be simultaneously written in a plurality or all of the memory cells connected to the word line selected by the word line selection circuit;
An array end voltage setting for setting an array end voltage to be applied to an end bit line of the plurality of bit lines connected to the plurality or all of the memory cells based on the conversion data converted by the data conversion circuit. Circuit,
Based on the conversion data converted by the data conversion circuit, the array end voltage set by the array end voltage setting circuit is applied to the bit line at the end, and the memory cell to be written to A plurality of or all of the plurality of or all of the bit lines are applied such that different voltages are applied to the two connected bit lines, while the same voltage is applied to the two bit lines connected to the memory cells that are not programmed. An applied voltage setting circuit for setting a voltage to be applied to the bit line connected to the memory cell;
A semiconductor memory device comprising: a voltage application circuit that applies a voltage set by the application voltage setting circuit to a bit line connected to the plurality or all of the memory cells. The semiconductor memory device according to claim 1,
An input data storage circuit that stores the input data and resets the input data corresponding to the memory cell for which writing has been completed when receiving a signal indicating completion of writing to the memory cell to be written,
An input data reset detection circuit for detecting whether or not the input data of the input data storage circuit is reset;
A semiconductor comprising: an input data update detection circuit for updating input data stored in the input data storage circuit when the input data reset detection circuit detects that all of the input data has been reset. Storage device. The semiconductor memory device according to claim 1,
A conversion data storage circuit that stores the conversion data and resets the conversion data corresponding to the memory cell for which writing has been completed when receiving a signal indicating completion of writing to the memory cell to be written,
A conversion data reset detection circuit for detecting whether or not the conversion data of the conversion data storage circuit is reset;
A semiconductor comprising: a conversion data update circuit for updating conversion data stored in the conversion data storage circuit when the conversion data reset detection circuit detects that all of the conversion data has been reset Storage device. The semiconductor memory device according to claim 1,
A semiconductor memory device, wherein the memory cell is formed of a sidewall memory. The semiconductor memory device according to claim 1,
A memory cell selection circuit for selecting every predetermined number of memory cells in the word line direction among the memory cells of the memory cell array;
A semiconductor memory device, wherein the conversion data is written into a memory cell connected to a word line selected by the word line selection circuit and selected by the memory cell selection circuit. The semiconductor memory device according to claim 1,
In the conversion data, there is no value that does not write to the memory cell between the values that write to the memory cell, or the value that does not write to the memory cell is an even number. A semiconductor memory device characterized in that there is data that exists. An electronic apparatus comprising the semiconductor memory device according to claim 1.

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