JP2007027489A - Method for manufacturing wiring board - Google Patents

Method for manufacturing wiring board Download PDF

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JP2007027489A
JP2007027489A JP2005208747A JP2005208747A JP2007027489A JP 2007027489 A JP2007027489 A JP 2007027489A JP 2005208747 A JP2005208747 A JP 2005208747A JP 2005208747 A JP2005208747 A JP 2005208747A JP 2007027489 A JP2007027489 A JP 2007027489A
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conductive pattern
substrate
electroplating
pattern
wiring board
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JP4544070B2 (en
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Goro Komatsu
吾郎 小松
Kenji Wada
健嗣 和田
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Seiko Epson Corp
Eastern Co Ltd
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Seiko Epson Corp
Eastern Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board capable of easily forming and removing a conductive pattern for an electroplating, and capable of simplifying a manufacturing process for the wiring board. <P>SOLUTION: When metal films 26 composed of a desired metal are formed on the predetermined surfaces of conductor patterns 12, 12... formed on the board surface of the board 10 by the electroplating, the conductive patterns 16 for the electroplating are formed on one surface side of the board 10 with the formed conductor patterns 12 by an ink jet printing method. The metal films 26 are formed on the predetermined surfaces of the conductor patterns 12 containing the conductive patterns 16 for the electroplating by the electroplating using the conductive patterns 16 for the electroplating in this case. The conductive patterns 16 for the electroplating formed on the surfaces of the metal films 26 are peeled in this case. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は配線基板の製造方法に関し、更に詳細には基板の少なくとも一面側に形成した導体パターンの所定表面に、電解めっきによって所望の金属から成る金属膜を形成する配線基板の製造方法に関する。   The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board in which a metal film made of a desired metal is formed by electrolytic plating on a predetermined surface of a conductor pattern formed on at least one side of the board.

配線基板を製造する際に、樹脂基板等の基板の少なくとも一面側に形成した導体パターンの所定表面に、電解めっきによって所望の金属から成る金属膜を形成することが行なわれている。かかる電解めっきは、通常、導体パターンを形成した基板の一面側の所定箇所に形成された電解めっき用導電パターンを介してなされている（例えば下記特許文献１参照）。
この電解めっき用導電パターンを図５（ａ）（ｂ）に示す。図５（ａ）は基板１００の断面図であり、図５（ｂ）は基板１００の部分正面図である。
図５（ａ）（ｂ）に示す樹脂製の基板１００の両面には、導体パターン１０２，１０２・・が形成され、その一部はスルーホールヴィア１０４に接続されている。
かかる基板１００の一面側の端縁近傍には、端縁に沿って電解めっき用導電パターン１０６を構成するバスライン１０６ａが形成され、バスライン１０６ａから各導体パターン１０２に分岐パターン１０６ｂが延出されている。
特開２００３−１０１１９５号公報 When manufacturing a wiring substrate, a metal film made of a desired metal is formed on a predetermined surface of a conductor pattern formed on at least one surface side of a substrate such as a resin substrate by electrolytic plating. Such electrolytic plating is usually performed through a conductive pattern for electrolytic plating formed at a predetermined location on one surface side of a substrate on which a conductor pattern is formed (see, for example, Patent Document 1 below).
This electroplating conductive pattern is shown in FIGS. FIG. 5A is a cross-sectional view of the substrate 100, and FIG. 5B is a partial front view of the substrate 100.
.. Are formed on both surfaces of a resin substrate 100 shown in FIGS. 5A and 5B, and a part of them is connected to the through-hole via 104.
In the vicinity of the edge on the one surface side of the substrate 100, a bus line 106a constituting the electroplating conductive pattern 106 is formed along the edge, and a branch pattern 106b is extended from the bus line 106a to each conductor pattern 102. ing.
JP 2003-101195 A

電解めっき用導電パターン１０６（以下、めっきパターン１０６と称することがある）を用いて電解めっきを施すには、図６（ａ）に示す様に、導体パターン１０２，１０２・・の電解めっきを施す所定箇所が露出するように、電解めっきを施さない箇所をソルダレジスト層１０８によって覆うと共に、めっきパターン１０６をマスク板１１０で覆う（このマスク板１１０に代えて、テープやドライフィルムが用いられることがある）。
次いで、めっきパターン１０６から給電する電解めっきによって、図６（ｂ）に示す様に、導体パターン１０２，１０２・・の各露出面に所望の金属から成る金属層１１２を形成した後、図６（ｃ）に示す様に、めっきパターン１０６を覆うマスク板１１０を除去する。
その後、図６（ｄ）に示す様に、ソルダレジスト層１０８及び金属層１１２をマスクとするエッチングによってめっきパターン１０６を除去する。めっきパターン１０６を除去した基板１００の一面側の部分正面図を図７に示す。図７に示す様に、めっきパターン１０６を除去することによって、導体パターン１０２，１０２・・の各々は隣接する導体パターン１０２と電気的に絶縁される。 In order to perform electroplating using the electroplating conductive pattern 106 (hereinafter also referred to as the plating pattern 106), as shown in FIG. 6A, electroplating of the conductor patterns 102, 102,. A portion not subjected to electroplating is covered with a solder resist layer 108 so that a predetermined portion is exposed, and the plating pattern 106 is covered with a mask plate 110 (in place of the mask plate 110, a tape or a dry film may be used. is there).
Next, as shown in FIG. 6B, a metal layer 112 made of a desired metal is formed on each exposed surface of the conductor patterns 102, 102,. As shown in c), the mask plate 110 covering the plating pattern 106 is removed.
Thereafter, as shown in FIG. 6D, the plating pattern 106 is removed by etching using the solder resist layer 108 and the metal layer 112 as a mask. A partial front view of one side of the substrate 100 from which the plating pattern 106 has been removed is shown in FIG. As shown in FIG. 7, by removing the plating pattern 106, each of the conductor patterns 102, 102... Is electrically insulated from the adjacent conductor pattern 102.

図５〜図６に示す配線基板の製造方法によれば、基板１００に形成した導体パターン１０２，１０２・・の各々の所定表面に所望金属の金属膜１１２を形成できる。
しかし、基板１００の一面側の所定箇所にめっきパターン１０６を、導体パターン１０２と同時に形成しておくことは、導体パターン１０２の設計の自由度を制限し、且つその除去のためのエッチング工程が必要なため、配線基板の製造工程を複雑化する。
そこで、本発明の課題は、電解めっき用導電パターンの形成及び除去を容易に行なうことができ、配線基板の製造工程を簡略化し得る配線基板の製造方法を提供することにある。 5 to 6, a metal film 112 of a desired metal can be formed on a predetermined surface of each of the conductor patterns 102, 102... Formed on the substrate 100.
However, forming the plating pattern 106 at a predetermined position on one surface side of the substrate 100 simultaneously with the conductor pattern 102 limits the degree of freedom in designing the conductor pattern 102 and requires an etching process for removing the plating pattern 106. Therefore, the manufacturing process of the wiring board is complicated.
Accordingly, an object of the present invention is to provide a method of manufacturing a wiring board that can easily form and remove a conductive pattern for electrolytic plating and can simplify the manufacturing process of the wiring board.

本発明者等は、前記課題を解決すべく種々検討した結果、インクジェット印刷法によって電解めっき用導電パターンを形成することによって、電解めっき用導電パターンを任意の時期に形成できること、インクジェット印刷法で形成した電解めっき用導電パターンは基板面から剥離し易いことを見出し、本発明に到達した。
すなわち、本発明は、基板の少なくとも一面側に形成した導体パターンの所定表面に、電解めっきによって所望の金属から成る金属膜を形成する際に、該導体パターンが形成された基板の一面側に電解めっき用導電パターンをインクジェット印刷法で形成した後、前記電解めっき用導電パターンを用いた電解めっきによって、前記電解めっき用導電パターンを含む導電パターンの所定表面に所望の金属から成る金属膜を形成し、次いで、前記金属膜が表面に形成された電解めっき用導電パターンを剥離することを特徴とする配線基板の製造方法にある。 As a result of various studies by the present inventors to solve the above-mentioned problems, it is possible to form a conductive pattern for electrolytic plating at an arbitrary time by forming a conductive pattern for electrolytic plating by an inkjet printing method. It was found that the electroplating conductive pattern easily peeled off from the substrate surface, and the present invention has been achieved.
That is, according to the present invention, when a metal film made of a desired metal is formed on a predetermined surface of a conductor pattern formed on at least one surface side of the substrate by electrolytic plating, electrolysis is performed on one surface side of the substrate on which the conductor pattern is formed. After forming the conductive pattern for plating by an ink jet printing method, a metal film made of a desired metal is formed on a predetermined surface of the conductive pattern including the conductive pattern for electrolytic plating by electrolytic plating using the conductive pattern for electrolytic plating. Then, the method for producing a wiring board is characterized in that the conductive pattern for electrolytic plating formed on the surface of the metal film is peeled off.

かかる本発明において、電解めっき用導電パターンを基板面から引き剥がすことによって剥離することが最も簡単である。このためには、電解めっき用導電パターンを形成する基板の一面側の所定面を、前記電解めっき用導電パターンを基板面から容易に引き剥がすことができるように平滑面に形成することが好ましい。
また、電解めっき用導電パターンは、粒径が１００ｎｍ以下の微細金属粒子が有機物層によって覆われた微細粒子を分散させたインクをインクジェットノズルから吐出し、基板の一面側の所定箇所に所望パターンを直接描画した後、焼成して前記有機物層を除去して形成される。 In the present invention, it is simplest to peel the electroplating conductive pattern by peeling it from the substrate surface. For this purpose, it is preferable to form a predetermined surface on one side of the substrate on which the electroplating conductive pattern is formed on a smooth surface so that the electroplating conductive pattern can be easily peeled off from the substrate surface.
In addition, the conductive pattern for electrolytic plating is a method in which ink in which fine particles in which fine metal particles having a particle size of 100 nm or less are covered with an organic layer is dispersed is ejected from an ink jet nozzle, and a desired pattern is formed at a predetermined position on one side of the substrate. After the direct drawing, the organic layer is formed by baking.

本発明においては、最終的に除去する電解めっき用導電パターンを、配線基板に必要な導体パターンとは別に、必要な時期にインクジェット印刷法によって簡易に形成できるため、導体パターンの設計の自由度を向上できる。更に、インクジェット印刷法によれば、形成面に段差が形成されていても、形成面の形状に倣って電解めっき用導電パターンを形成できるため、基板の任意の箇所に形成できる。
また、インクジェット印刷法によって形成した電解めっき用導電パターンは、電解めっき中には剥離しないものの、他の導体パターンと比較して基板面から剥離され易いものである。このため、電解めっき用導電パターンの除去は、電解めっき用導電パターンに貼り付けた粘着テープを剥離する等の手段によって容易に行なうことができる結果、電解めっき用導電パターンの形成及び除去の工程を短縮できる。 In the present invention, the electroplating conductive pattern to be finally removed can be easily formed by the ink jet printing method at a necessary time separately from the conductive pattern necessary for the wiring board. It can be improved. Furthermore, according to the ink jet printing method, even if a step is formed on the formation surface, the electroplating conductive pattern can be formed following the shape of the formation surface, so that it can be formed at any location on the substrate.
Moreover, although the electroplating conductive pattern formed by the ink-jet printing method does not peel off during electroplating, it is more easily peeled off from the substrate surface than other conductor patterns. For this reason, the removal of the electroplating conductive pattern can be easily performed by means such as peeling the adhesive tape attached to the electroplating conductive pattern. Can be shortened.

本発明において用いる基板の一例を図１に示す。図１に示す基板１０は、図１（ａ）に示す様に、ポリイミド等の樹脂製基板１０（以下、基板１０と称することがある）の両面に銅から成る導体パターン１２，１２・・が形成され、基板１０の両面の導体パターン１２，１２・・を電気的に接続するスルーホールヴィア１４が形成されている。この導体パターン１２，１２・・の基板１０側の各端部は、図１（ａ）に示す基板１０の部分正面図である図１（ｂ）に示す様に、基板１０の端縁近傍まで延出されている。
かかる図１（ａ）（ｂ）に示す導体パターン１２，１２・・は、回路形成方法として公知のサブトラクティブ法やアディティブ法によって形成できる。
また、特開２００２−３２４９６６号公報等に提案されているインクジェット印刷法によって、導体パターン１２，１２・・を形成してもよい。この場合、基板１０の導体パターン形成面のうち、電解めっき用導電パターンを形成する部分を除いて粗面化加工を施すことによって、形成された導体パターン１２，１２・・と基板１０との密着性を向上できる。 An example of the substrate used in the present invention is shown in FIG. As shown in FIG. 1A, the substrate 10 shown in FIG. 1 has conductor patterns 12, 12,... Made of copper on both surfaces of a resin substrate 10 such as polyimide (hereinafter sometimes referred to as the substrate 10). The through-hole vias 14 that are formed and electrically connect the conductor patterns 12, 12... On both sides of the substrate 10 are formed. Each end of the conductor patterns 12, 12,... On the substrate 10 side extends to the vicinity of the edge of the substrate 10 as shown in FIG. 1 (b) which is a partial front view of the substrate 10 shown in FIG. It has been extended.
1A and 1B can be formed by a known subtractive method or additive method as a circuit forming method.
Moreover, you may form the conductor patterns 12, 12, ... by the inkjet printing method proposed by Unexamined-Japanese-Patent No. 2002-324966 etc. In this case, the surface of the conductor pattern forming surface of the substrate 10 is roughened except for the portion where the electroplating conductive pattern is to be formed, so that the formed conductor patterns 12, 12,. Can be improved.

次いで、図２（ａ）に示す様に、形成した導体パターン１２，１２・・の電解めっきを施す所定箇所が露出するように、電解めっきを施さない箇所をソルダレジスト層１８によって覆うと共に、基板１０の一面側の端縁近傍に電解めっき用導電パターン１６をインクジェット印刷法で形成する。
形成した電解めっき用導電パターン１６は、図２（ａ）に示す基板１０の部分正面図である図３（ａ）に示す様に、基板１０の端縁に沿って電解めっき用導電パターン１６を構成するバスライン１６ａが形成され、バスライン１６ａから各導体パターン１２に分岐パターン１６ｂが延出されている。かかる分岐パターン１６ｂの先端部は、図２（ａ）に示す様に、導体パターン１２の端部と接続されている。 Next, as shown in FIG. 2 (a), a portion not subjected to electrolytic plating is covered with a solder resist layer 18 so that a predetermined portion where electrolytic plating of the formed conductor patterns 12, 12,. The electroplating conductive pattern 16 is formed in the vicinity of the edge on the one surface side 10 by an ink jet printing method.
As shown in FIG. 3A, which is a partial front view of the substrate 10 shown in FIG. 2A, the formed electroplating conductive pattern 16 is formed along the edge of the substrate 10. A bus line 16 a is formed, and a branch pattern 16 b extends from the bus line 16 a to each conductor pattern 12. The tip of the branch pattern 16b is connected to the end of the conductor pattern 12 as shown in FIG.

図２（ａ）及び図３（ａ）に示す電解めっき用導電パターン１６をインクジェット印刷法によって形成するには、粒径が１００ｎｍ以下の微細金属粒子が有機物層によって覆われた微細粒子を分散させたインクをインクジェットノズルから吐出し、基板１０の一面側の所定箇所に所望パターンを直接描画した後、焼成して有機物層を除去して形成できる。
かかるインクジェット印刷法によれば、電解めっき用導電パターン１６を、導体パターン１２とは別に必要な時期に簡易に形成でき、且つ形成面に段差が形成されていても、形成面の形状に倣って形成できるため、基板の任意の箇所に形成できる。
このインクジェット印刷法に用いる微細金属粒子としては、１５０〜２００℃の焼成温度で焼成できる金属、具体的には金、銀、銅、ニッケル又はマンガンから成る、平均粒径が２〜５０ｎｍの微細金属粒子を好適に用いることができる。かかる微細金属粒子を覆う有機物層は、インク中での微細粒子の分散性を向上するためのものである。
この様な微細金属粒子が分散されたインクを吐出するインクジェットノズルとしては、ピエゾ素子を利用する圧縮により液滴を吐出するピエゾ方式を採用したインクジェットノズルを用いることが、使用するインクの制約が少なく好ましい。 In order to form the electroplating conductive pattern 16 shown in FIGS. 2 (a) and 3 (a) by the ink jet printing method, fine metal particles having a particle diameter of 100 nm or less are dispersed by an organic material layer. The ink can be ejected from an inkjet nozzle, and a desired pattern can be directly drawn at a predetermined location on one side of the substrate 10 and then baked to remove the organic layer.
According to such an ink jet printing method, the electroplating conductive pattern 16 can be easily formed at a necessary time separately from the conductor pattern 12, and even if a step is formed on the forming surface, it follows the shape of the forming surface. Since it can be formed, it can be formed at any location on the substrate.
The fine metal particles used in this ink-jet printing method are metals that can be fired at a firing temperature of 150 to 200 ° C., specifically, fine metals having an average particle diameter of 2 to 50 nm made of gold, silver, copper, nickel, or manganese. Particles can be suitably used. The organic layer covering the fine metal particles is for improving the dispersibility of the fine particles in the ink.
As an inkjet nozzle that ejects ink in which such fine metal particles are dispersed, an inkjet nozzle that employs a piezo method that ejects droplets by compression using a piezo element is used, and there are few restrictions on the ink to be used. preferable.

インクジェットノズルから吐出し、基板１０の一面側の所定箇所に直接描画したパターンは、図４に示す様に、微細金属粒子２２が有機物層２４によって覆われた微細粒子２０，２０・・が積層されており、導電性は発現していない。かかる微細粒子２０，２０・・が積層された状態で焼成することによって、有機物層２４が除去された微細金属粒子２２，２２・・が焼成されて導電性を呈する電解めっき用導電パターン１６を形成できる。この場合の焼成温度は、金、銀、ニッケル又はマンガンから成る微細金属粒子２２では、１５０〜２００℃とすることが好ましい。
また、この焼成は、ソルダレジスト層１８を形成する際に施すキュア処理と同時に施してもよく、或いはソルダレジスト層１８のキュア処理とは別に施してもよい。 As shown in FIG. 4, the pattern discharged from the ink jet nozzle and directly drawn on a predetermined portion on one side of the substrate 10 is formed by stacking fine particles 20, 20,... In which fine metal particles 22 are covered with an organic material layer 24. Therefore, conductivity is not expressed. The fine metal particles 22, 22... From which the organic layer 24 has been removed are fired to form the electroplating conductive pattern 16 that exhibits conductivity by firing in a state where the fine particles 20, 20. it can. In this case, the firing temperature is preferably 150 to 200 ° C. for the fine metal particles 22 made of gold, silver, nickel or manganese.
Further, this baking may be performed simultaneously with the curing process performed when the solder resist layer 18 is formed, or may be performed separately from the curing process of the solder resist layer 18.

この様にして形成した電解めっき用導電パターン１６を用いた電解めっきによって、図２（ｂ）に示す様に、導電パターン１２，１２・・の露出箇所に金属膜２６を形成する。
かかる電解めっきによって形成する金属膜２６としては、所望の金属から成る金属膜２６を形成できるが、金やニッケルから成る金属膜２６を形成することが好ましい。
この電解めっきを、図２（ｂ）に示す様に、電解めっき用導電パターン１６を露出状態として施してもよい。電解めっき用導電パターン１６上に形成された金属膜２６は、後述する様に、電解めっき用導電パターン１６と共に回収再利用できるからである。 As shown in FIG. 2B, a metal film 26 is formed on the exposed portions of the conductive patterns 12, 12,... By electrolytic plating using the conductive pattern 16 for electrolytic plating thus formed.
As the metal film 26 formed by such electrolytic plating, a metal film 26 made of a desired metal can be formed, but it is preferable to form a metal film 26 made of gold or nickel.
As shown in FIG. 2B, this electrolytic plating may be performed with the electroplating conductive pattern 16 exposed. This is because the metal film 26 formed on the electroplating conductive pattern 16 can be recovered and reused together with the electroplating conductive pattern 16 as described later.

ところで、インクジェット印刷法によって基板１０の一面側に直接描画した後、焼成して形成した電解めっき用導電パターン１６の基板１０との接合面は、図４に示す様に、基板１０の平滑面に対して凹凸面となっている。このため、電解めっき用導電パターン１６の剥離は、図２（ｃ）に示す様に、その上面に形成された金属膜２６と共に基板面から引き剥がすことによって容易に行なうことができる。
かかる電解めっき用導電パターン１６の剥離手段としては、電解めっき用導電パターン１６に貼り付けた粘着テープを剥離する手段を好適に用いることができる。粘着テープを剥離する際に、粘着テープに付着して金属膜２２が上面に形成された電解めっき用導電パターン１６が剥離される。
剥離された金属膜２６が上面に形成された電解めっき用導電パターン１６は、粘着テープに付着しているため、回収して再利用を図ることができる。 By the way, the joint surface with the substrate 10 of the electroplating conductive pattern 16 formed by direct drawing on the one surface side of the substrate 10 by the ink jet printing method is formed on the smooth surface of the substrate 10 as shown in FIG. On the other hand, it has an uneven surface. Therefore, the electroplating conductive pattern 16 can be easily peeled off from the substrate surface together with the metal film 26 formed on the upper surface thereof, as shown in FIG.
As the peeling means for the electroplating conductive pattern 16, a means for peeling the adhesive tape attached to the electroplating conductive pattern 16 can be suitably used. When the adhesive tape is peeled off, the electroplating conductive pattern 16 having the metal film 22 formed on the upper surface and attached to the adhesive tape is peeled off.
Since the electroplating conductive pattern 16 having the peeled metal film 26 formed on the upper surface is attached to the adhesive tape, it can be recovered and reused.

かかる電解めっき用導電パターン１６の剥離は、電解めっき用導電パターン１６を形成した基板１０の基板面を平滑面とすることによって容易に行なうことができる。このため、基板１０の基板面を、導体パターン１２，１２・・との密着性を向上すべく粗面加工する場合には、電解めっき用導電パターン１６を形成する部分の基板面を、保護フィルム等で保護して粗面化することを防止し、その平滑面状態を保持することが好ましい。
電解めっき用導電パターン１６を剥離した基板面の部分正面図を図３（ｂ）に示す。導体パターン１２の端部に電解めっき用導電パターン１６の一部が残留しているが、配線基板の導体パターンとしては問題にならない程度のものである。 The peeling of the electroplating conductive pattern 16 can be easily performed by making the substrate surface of the substrate 10 on which the electroplating conductive pattern 16 is formed a smooth surface. Therefore, when the substrate surface of the substrate 10 is roughened so as to improve the adhesion with the conductor patterns 12, 12,..., The portion of the substrate surface on which the electroplating conductive pattern 16 is formed is protected with a protective film. It is preferable to prevent the surface from being roughened by protecting with, for example, a smooth surface state.
FIG. 3B shows a partial front view of the substrate surface from which the electroplating conductive pattern 16 has been peeled off. Although a part of the electroplating conductive pattern 16 remains at the end of the conductor pattern 12, it does not cause a problem as a conductor pattern of the wiring board.

この様にして得られた配線基板は、必要に応じて更に加工が施されて最終製品を得ることができる。
かかる配線基板の製造工程では、インクジェット印刷法によって電解めっき用導電パターン１６を形成するため、その形成及び除去を容易に行なうことができ、従来の配線基板の製造工程よりも、その工程数を減少できる。
また、導体パターン１２と電解めっき用導電パターン１６とを同時に形成することを要しないため、導体パターン１２の設計の自由度を向上できる。
以上、説明してきた図１〜４では、基板１０として樹脂基板について説明してきたが、シリコン基板やセラミック基板を基板１０として用いることができる。
また、図１〜４では、両面側に導体パターン１２，１２・・が形成された基板１０を用いたが、本発明では、一面側のみに導体パターン１２，１２・・が形成された基板であっても用いることができる。 The wiring board thus obtained can be further processed as necessary to obtain a final product.
In such a wiring board manufacturing process, since the electroplating conductive pattern 16 is formed by the ink jet printing method, it can be easily formed and removed, and the number of processes is reduced compared to the conventional wiring board manufacturing process. it can.
Moreover, since it is not necessary to form the conductor pattern 12 and the electroplating conductive pattern 16 at the same time, the degree of freedom in designing the conductor pattern 12 can be improved.
1 to 4 described above, the resin substrate has been described as the substrate 10, but a silicon substrate or a ceramic substrate can be used as the substrate 10.
1 to 4, the substrate 10 having the conductor patterns 12, 12... Formed on both sides is used. However, in the present invention, the substrate having the conductor patterns 12, 12. Even if it exists, it can be used.

本発明に係る配線基板の製造工程の前期工程を説明するための横断面図及び部分正面図である。It is the cross-sectional view and the partial front view for demonstrating the first stage process of the manufacturing process of the wiring board based on this invention. 本発明に係る配線基板の製造工程の後期工程を説明するための横断面図である。It is a cross-sectional view for demonstrating the latter process of the manufacturing process of the wiring board which concerns on this invention. 図２（ａ）に示す配線基板に対応する部分正面図及び図２（ｃ）に示す配線基板に対応する部分正面図である。FIG. 3 is a partial front view corresponding to the wiring board shown in FIG. 2A and a partial front view corresponding to the wiring board shown in FIG. 本発明で採用するインクジェット印刷法で用いるインク中の微細粒子について説明する説明図である。It is explanatory drawing explaining the fine particle in the ink used with the inkjet printing method employ | adopted by this invention. 従来の配線基板の製造工程の前期工程を説明するための横断面図及び部分正面図である。It is the cross-sectional view and partial front view for demonstrating the previous process of the manufacturing process of the conventional wiring board. 従来の配線基板の製造工程の後期工程を説明するための横断面図である。It is a cross-sectional view for demonstrating the latter process of the manufacturing process of the conventional wiring board. 従来の配線基板の製造工程の後期工程で形成された配線基板の部分正面図である。It is a partial front view of the wiring board formed in the latter process of the manufacturing process of the conventional wiring board.

符号の説明Explanation of symbols

１０ 基板
１２ 導体パターン
１４ スルーホールヴィア
１６ 電解めっき用導電パターン
１６ａ バスライン
１６ｂ 分岐パターン
１８ ソルダレジスト層
２０ 微細粒子
２２ 微細金属粒子
２４ 有機物層
２６ 金属膜
２８ 金属膜 DESCRIPTION OF SYMBOLS 10 Board | substrate 12 Conductor pattern 14 Through-hole via 16 Electroconductive pattern 16a for electroplating Bus line 16b Branch pattern 18 Solder resist layer 20 Fine particle 22 Fine metal particle 24 Organic substance layer 26 Metal film 28 Metal film

Claims (4)

基板の少なくとも一面側に形成した導体パターンの所定表面に、電解めっきによって所望の金属から成る金属膜を形成する際に、
該導体パターンが形成された基板の一面側に電解めっき用導電パターンをインクジェット印刷法で形成した後、
前記電解めっき用導電パターンを用いた電解めっきによって、前記電解めっき用導電パターンを含む導電パターンの所定表面に所望の金属から成る金属膜を形成し、
次いで、前記金属膜が表面に形成された電解めっき用導電パターンを剥離することを特徴とする配線基板の製造方法。 When a metal film made of a desired metal is formed by electrolytic plating on a predetermined surface of a conductor pattern formed on at least one side of a substrate,
After forming a conductive pattern for electroplating on one side of the substrate on which the conductor pattern is formed by an inkjet printing method,
Forming a metal film made of a desired metal on a predetermined surface of the conductive pattern including the conductive pattern for electrolytic plating by electrolytic plating using the conductive pattern for electrolytic plating,
Next, a method for manufacturing a wiring board, comprising peeling off a conductive pattern for electrolytic plating on which the metal film is formed. 電解めっき用導電パターンを基板面から引き剥がすことによって剥離する請求項１記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 1, wherein the electroplating conductive pattern is peeled off from the board surface. 電解めっき用導電パターンを形成する基板の一面側の所定面を、前記電解めっき用導電パターンを基板面から容易に引き剥がすことができるように平滑面に形成する請求項１又は請求項２記載の配線基板の製造方法。   The predetermined surface on one surface side of the substrate on which the electroplating conductive pattern is formed is formed on a smooth surface so that the electroplating electroconductive pattern can be easily peeled off from the substrate surface. A method for manufacturing a wiring board. 電解めっき用導電パターンを、粒径が１００ｎｍ以下の微細金属粒子が有機物層によって覆われた微細粒子を分散させたインクをインクジェットノズルから吐出し、基板の一面側の所定箇所に所望パターンを直接描画した後、焼成して前記有機物層を除去して形成する請求項１〜３のいずれか一項記載の配線基板の製造方法。   A conductive pattern for electroplating is ejected from an inkjet nozzle with ink in which fine metal particles with a particle size of 100 nm or less and covered with an organic layer are dispersed, and a desired pattern is directly drawn at a predetermined location on one side of the substrate. The method for manufacturing a wiring board according to claim 1, wherein the organic layer is formed by firing and removing the organic layer.
JP2005208747A 2005-07-19 2005-07-19 Wiring board manufacturing method Expired - Fee Related JP4544070B2 (en)

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KR101055468B1 (en) 2008-10-28 2011-08-08 삼성전기주식회사 Manufacturing method of multilayer printed circuit board
WO2013122347A1 (en) * 2012-02-16 2013-08-22 주식회사 아모그린텍 Method for plating printed circuit boards and method for manufacturing flexible printed circuit boards using same
JP2021174860A (en) * 2020-04-24 2021-11-01 Ｎｅｃプラットフォームズ株式会社 Substrate and manufacturing method thereof

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JPS6056073A (en) * 1983-09-05 1985-04-01 Hitachi Ltd Method for coating ceramic substrate with partially thick gold film
JP2002057463A (en) * 2000-08-10 2002-02-22 Dainippon Printing Co Ltd Method for forming wirings, and printed circuit board
JP2002324966A (en) * 2001-04-24 2002-11-08 Harima Chem Inc Method for forming circuit pattern utilizing ink-jet printing method

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JPS6056073A (en) * 1983-09-05 1985-04-01 Hitachi Ltd Method for coating ceramic substrate with partially thick gold film
JP2002057463A (en) * 2000-08-10 2002-02-22 Dainippon Printing Co Ltd Method for forming wirings, and printed circuit board
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Publication number Priority date Publication date Assignee Title
KR101055468B1 (en) 2008-10-28 2011-08-08 삼성전기주식회사 Manufacturing method of multilayer printed circuit board
WO2013122347A1 (en) * 2012-02-16 2013-08-22 주식회사 아모그린텍 Method for plating printed circuit boards and method for manufacturing flexible printed circuit boards using same
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JP2021174860A (en) * 2020-04-24 2021-11-01 Ｎｅｃプラットフォームズ株式会社 Substrate and manufacturing method thereof

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