JP2007027200A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2007027200A
JP2007027200A JP2005203321A JP2005203321A JP2007027200A JP 2007027200 A JP2007027200 A JP 2007027200A JP 2005203321 A JP2005203321 A JP 2005203321A JP 2005203321 A JP2005203321 A JP 2005203321A JP 2007027200 A JP2007027200 A JP 2007027200A
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manufacturing
insulating film
semiconductor device
transistor
channel
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JP4987259B2 (en
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Shishiyo Minami
志昌 南
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Seiko Instruments Inc
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Seiko Instruments Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a full depletion type SOI transistor, which can suppress SOI layer film thickness dependency of a threshold, even if the threshold is controlled at concentration of impurities to be doped into a channel forming portion while preventing a parasitic channel, in the full depletion type SOI transistor, especially, an NMOS transistor. <P>SOLUTION: In a channel forming process in the method of manufacturing the full depletion type SOI transistor, especially, the NMOS transistor, ion implantation for threshold control for the channel forming portion is executed for an interface between an SOI layer and a buried insulation film at plurality of times while changing acceleration energy and dividing a dose quantity. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関し、特にＳＯＩ基板における半導体薄膜の膜厚のばらつきに起因する閾値変動を抑制する完全空乏型ＳＯＩトランジスタの製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a fully depleted SOI transistor that suppresses threshold fluctuation caused by variations in the thickness of a semiconductor thin film on an SOI substrate.

従来のＳＯＩ構造をもつ半導体装置の製造方法の模式的断面図を図５から図７に示す。図５（a）のように支持基板２０１上に埋め込み絶縁膜２０２が形成されており、埋め込み絶縁膜２０２上に半導体薄膜(ＳＯＩ層)２０３が形成されているＳＯＩ構造基板のＳＯＩ層２０３にＬＯＣＯＳ法によりフィールド絶縁膜２０４、例えば膜厚数千Åの熱酸化膜を形成した後、ＭＯＳトランジスタを形成する領域の絶縁膜を除去し、チャネル形成部１０６を形成する。その後、図５（ｂ）に示すように、犠牲酸化膜２１３をＳＯＩ層１０３上に例えば1５ｎｍ成長させた後、チャネル形成部２０６へ閾値調整するためのイオン注入を行う。次に、図６（ａ）に示すように、犠牲酸化膜２１３をフッ酸（ＨＦ）系の溶液にてエッチングした後、ゲート絶縁膜２０５を例えば数十ｎｍ成長させ、ゲート絶縁膜２０５上に多結晶シリコンを堆積し、プリデポあるいはイオン注入により不純物を導入し、パターニングを行うことによりゲート電極となる多結晶シリコンゲート２０７が形成される。続いて、図６（ｂ）に示すように多結晶シリコンゲート２０７の両端にドレインおよびソース高濃度領域２０８、２０９に、例えばＡｓを、シート抵抗を低減するため、好ましくは１×１０14〜１×１０16atoms／cm2の濃度でイオン注入する。図７において、続いて、層間絶縁膜２１０を２００ｎｍ〜８００ｎｍ程度の膜厚を堆積させ、ソース高濃度領域２０９およびドレイン高濃度領域２０８領域と配線の接続をとるためのコンタクトホール２１1を形成する。次に、配線メタルをスパッタ等で形成、パターニングを行うと、メタル２１２とドレインおよびソース高濃度領域２０８、２０９表面がコンタクトホール２１１を通して接続される。 5 to 7 are schematic cross-sectional views of a conventional method for manufacturing a semiconductor device having an SOI structure. As shown in FIG. 5A, a buried insulating film 202 is formed on a support substrate 201, and a semiconductor thin film (SOI layer) 203 is formed on the buried insulating film 202. After forming a field insulating film 204, for example, a thermal oxide film having a thickness of several thousand Å by the method, the insulating film in a region where a MOS transistor is to be formed is removed, and a channel forming portion 106 is formed. Thereafter, as shown in FIG. 5B, after the sacrificial oxide film 213 is grown on the SOI layer 103 by, for example, 15 nm, ion implantation for adjusting the threshold value is performed on the channel forming portion 206. Next, as shown in FIG. 6A, after the sacrificial oxide film 213 is etched with a hydrofluoric acid (HF) -based solution, a gate insulating film 205 is grown to, for example, several tens of nanometers, and is formed on the gate insulating film 205. A polycrystalline silicon gate 207 to be a gate electrode is formed by depositing polycrystalline silicon, introducing impurities by pre-deposition or ion implantation, and performing patterning. Subsequently, as shown in FIG. 6B, for example, As is added to the drain and source high-concentration regions 208 and 209 at both ends of the polycrystalline silicon gate 207, and preferably 1 × 10 14 to 1 to reduce the sheet resistance. Ions are implanted at a concentration of × 10 16 atoms / cm 2 . In FIG. 7, subsequently, an interlayer insulating film 210 having a thickness of about 200 nm to 800 nm is deposited to form a contact hole 21 1 for connecting wirings to the source high concentration region 209 and the drain high concentration region 208 region. Next, when a wiring metal is formed by sputtering or the like and patterned, the metal 212 and the surface of the drain and source high concentration regions 208 and 209 are connected through the contact hole 211.

上記の製造方法において、ＳＯＩ構造を用いることによって素子間同士の完全分離が容易となり、またソフトエラーやＣＭＯＳトランジスタに特有なラッチアップの抑制が可能である。またＳＯＩ層２０３をさらに１００ｎｍ程度にまで薄くし、チャネルの不純物濃度も比較的低い状態に制御して、ほぼＳＯＩ層２０３全体が空乏化するような条件にすることによって、完全空乏型ＳＯＩトランジスタとなり、拡散層容量の低減のみならず、サブスレショルド領域での急峻なドレイン電流の立ち上がり等のさらに優れた特性を有することを可能とした。   In the above manufacturing method, by using the SOI structure, complete isolation between elements can be facilitated, and soft errors and latch-up peculiar to CMOS transistors can be suppressed. Further, the SOI layer 203 is further thinned to about 100 nm, the impurity concentration of the channel is controlled to be relatively low, and the conditions are set so that the entire SOI layer 203 is almost depleted, whereby a fully depleted SOI transistor is obtained. In addition to reducing the diffusion layer capacitance, it is possible to have more excellent characteristics such as a steep rise in drain current in the subthreshold region.

さらに、従来のＳＯＩ技術では、埋め込み絶縁膜２０２界面付近において寄生チャネルがオンするのを防止する為にＳＯＩ層２０３／埋め込み絶縁膜２０２界面付近にチャネル形成部２０６に導入される不純物の濃度のピークをもってきている(例えば、特開平１１−０２６７６９を参照)。また、さらに埋め込み酸化膜２０２を厚くしたりすることで寄生チャネルがオンし、リーク電流が増大するのを抑制している。
特開平１１−０２６７６９ Further, in the conventional SOI technology, in order to prevent the parasitic channel from being turned on in the vicinity of the buried insulating film 202 interface, the peak of the concentration of impurities introduced into the channel forming portion 206 in the vicinity of the SOI layer 203 / buried insulating film 202 interface. (See, for example, JP-A-11-026769). Further, by increasing the thickness of the buried oxide film 202, the parasitic channel is turned on, and an increase in leakage current is suppressed.
JP-A-11-026769

ところが、チャネルへ導入する不純物の濃度によって、完全空乏型ＳＯＩトランジスタの閾値を制御しようとした場合、閾値は導入された不純物の総量によって決定されることになる。その結果、次の問題が生じる。すなわち、従来の技術では、寄生チャネルがオンするのを防止する為にＳＯＩ層／埋め込み酸化膜界面付近にチャネル形成部に導入される不純物の濃度のピークをもってきている。そのため、工程ばらつきによりＳＯＩ層膜厚がばらつくと、チャネル形成部に導入される不純物総量と埋め込み絶縁膜に導入される不純物総量の割合が大きく変化してしまい、閾値およびリーク電流に影響を及ぼす課題を有していた。これは特に完全空乏型ＳＯＩＮＭＯＳトランジスタで起こり易い。本発明は、以上のような点に着目してなされたもので、本発明は、完全空乏型ＳＯＩトランジスタ、特にＮＭＯＳトランジスタにおいて、寄生チャネルを防止しつつ、閾値をチャネル形成部へ導入する不純物濃度で制御しようとした場合にも、閾値のＳＯＩ層膜厚依存性が抑制される完全空乏型ＳＯＩトランジスタの製造方法を提供することを目的とする。   However, when the threshold value of the fully depleted SOI transistor is controlled by the concentration of the impurity introduced into the channel, the threshold value is determined by the total amount of the introduced impurity. As a result, the following problem occurs. In other words, the conventional technique has a peak concentration of impurities introduced into the channel forming portion in the vicinity of the SOI layer / buried oxide film interface in order to prevent the parasitic channel from being turned on. Therefore, if the SOI layer thickness varies due to process variations, the ratio between the total amount of impurities introduced into the channel formation portion and the total amount of impurities introduced into the buried insulating film changes greatly, and this affects the threshold and leakage current. Had. This is particularly likely to occur with fully depleted SOI NMOS transistors. The present invention has been made paying attention to the above points. The present invention relates to an impurity concentration for introducing a threshold value into a channel forming portion in a fully depleted SOI transistor, particularly an NMOS transistor, while preventing a parasitic channel. It is an object of the present invention to provide a method for manufacturing a fully depleted SOI transistor in which the dependence of the threshold value on the SOI layer thickness is suppressed even when the control is attempted.

上記課題を解決するために、本発明は次の手段を用いた。
１．半導体支持基板上に形成された絶縁膜と絶縁膜上に形成された半導体薄膜層から構成されるＳＯＩ(Silicon On Insulator)基板の半導体薄膜層上に形成された完全空乏型ＳＯＩトランジスタを有する半導体装置の製造方法のチャネルを形成する工程において半導体薄膜層と絶縁膜との界面に加速エネルギーを変えて不純物濃度量を分割して第１導電型の不純物注入を複数回行うことを特徴とする完全空乏型ＳＯＩトランジスタの製造方法とした。
２．第１導電型の不純物注入を、犠牲酸化膜を介して行う製造方法した。
３．第１導電型の不純物注入を、ゲート絶縁膜を介して行う製造方法とした。
４．第１導電型の不純物注入を、トランジスタのゲート電極を介して行う製造方法とした。 In order to solve the above problems, the present invention uses the following means.
1. A semiconductor support substrate on the formed insulating film fully depleted SOI transistor formed on the SOI (S ilicon O n I nsulator ) substrate of a semiconductor thin film layer composed of a semiconductor thin film layer formed on the insulating film In the step of forming a channel of the method for manufacturing a semiconductor device having the method, the first conductivity type impurity implantation is performed a plurality of times by dividing the impurity concentration by changing the acceleration energy at the interface between the semiconductor thin film layer and the insulating film. This is a method for manufacturing a fully depleted SOI transistor.
2. A manufacturing method is performed in which the first conductivity type impurity is implanted through a sacrificial oxide film.
3. In the manufacturing method, the first conductivity type impurity is implanted through the gate insulating film.
4). In the manufacturing method, the first conductivity type impurity is implanted through the gate electrode of the transistor.

以上述べたように本発明は、完全空乏型ＳＯＩトランジスタ、特にＮＭＯＳトランジスタの製造方法におけるチャネル形成工程において、チャネル形成部へ閾値調整のためのイオン注入をＳＯＩ層/埋め込み絶縁膜との界面に、加速エネルギーを変えてドーズ量を分割して複数回行うことで、以下の効果を得ることができる。
１．閾値は、ＳＯＩ層膜厚のばらつきがあってもほぼ一定に揃えられる。
２．寄生チャネルを防止することが可能である。 As described above, according to the present invention, in the channel formation step in the manufacturing method of a fully depleted SOI transistor, in particular, an NMOS transistor, ion implantation for threshold adjustment is performed on the interface between the SOI layer and the buried insulating film in the channel formation portion. By changing the acceleration energy and dividing the dose amount a plurality of times, the following effects can be obtained.
1. The threshold values are almost constant even if the SOI layer thickness varies.
2. It is possible to prevent parasitic channels.

以下、本発明の実施の形態を図に基づいて説明する。先ず、本実施形態に係る完全空乏型ＳＯＩＮＭＯＳトランジスタの製造方法の概要を図１に基づいて説明する。図１（ａ）に示すように、例えばＳＯＩ層１０３の厚さ１００〜４００ｎｍ、埋め込み酸化膜１０２の厚さ１００〜４００ｎｍ、支持基板１０１の抵抗率ｐ型２０〜３０Ω・ｃｍのＳＯＩ構造基板のＳＯＩ層１０３上にＬＯＣＯＳ法によりフィールド絶縁膜１０４、例えば膜厚数千Åの熱酸化膜を形成して、ＳＯＩ層１０３を素子間分離して、その後ＭＯＳトランジスタを形成する領域の絶縁膜を除去し、チャネル形成部１０６を形成する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, an outline of a method for manufacturing a fully depleted SOI NMOS transistor according to the present embodiment will be described with reference to FIG. As shown in FIG. 1A, for example, an SOI structure substrate having an SOI layer 103 having a thickness of 100 to 400 nm, a buried oxide film 102 having a thickness of 100 to 400 nm, and a support substrate 101 having a p-type resistivity of 20 to 30 Ω · cm. A field insulating film 104, for example, a thermal oxide film having a thickness of several thousand Å, for example, is formed on the SOI layer 103 by the LOCOS method, the SOI layer 103 is separated between elements, and then the insulating film in a region for forming a MOS transistor is removed. Then, the channel forming portion 106 is formed.

その後、図１（ｂ）に示すように、犠牲酸化膜１１３をＳＯＩ層１０３上に例えば1５ｎｍ成長させた後、チャネル形成部１０６へ閾値調整のためのイオン注入をＳＯＩ層１０３/埋め込み絶縁膜１０２との界面に、通常１回で例えばイオン種：ボロンイオン（Ｂ+）、加速エネルギー：３０ｋｅＶ、注入角度：７°、ドーズ量：１.８×１０12 atom/ｃｍ-2で行うところ、加速エネルギーを変えてドーズ量を分割して複数回、例えば以下の条件にて行う。ただし、２回目、３回目のドーズ量は微調整のため、１回目のドーズ量よりも少なくすることが好ましい。
1回目：イオン種：Ｂ+、加速エネルギー：３０ｋｅＶ、注入角度：７°、ドーズ量：通常の１０〜２０％減
２回目：イオン種：Ｂ+、加速エネルギー：１回目の３〜１０％減、注入角度：７°、ドーズ量：通常の８０〜９０％減
３回目：イオン種：Ｂ+、加速エネルギー：１回目の３〜１０％増、注入角度：７°、ドーズ量：通常の８０〜９０％減
このように上記の様な条件にてイオン注入をＳＯＩ層１０３／埋め込み絶縁膜１０２界面付近に行うことによって、図４に示すようにチャネルに導入される不純物濃度のピーク幅を幅広くすることができるので、ＳＯＩ層膜厚１０３のばらつきによるチャネル形成部１０６に導入される不純物総量と埋め込み絶縁膜１０３に導入される不純物総量の割合の変化を緩和することができる。つまりＮＭＯＳトランジスタの閾値は、ＳＯＩ層膜厚２０３のばらつきがあってもほぼ一定に揃えられることになる。 Thereafter, as shown in FIG. 1B, after a sacrificial oxide film 113 is grown on the SOI layer 103, for example, by 15 nm, ion implantation for adjusting a threshold value is performed on the channel forming unit 106 by the SOI layer 103 / the buried insulating film 102. Acceleration is usually carried out at one interface, for example, with ion species: boron ion (B + ), acceleration energy: 30 keV, implantation angle: 7 °, dose amount: 1.8 × 10 12 atom / cm −2. The dose is divided by changing the energy, and the process is performed a plurality of times, for example, under the following conditions. However, the second and third doses are preferably adjusted to be smaller than the first dose for fine adjustment.
1st time: ion species: B + , acceleration energy: 30 keV, implantation angle: 7 °, dose amount: normal 10-20% decrease Second time: ion species: B + , acceleration energy: 1st time decrease of 3-10% , Implantation angle: 7 °, dose amount: normal 80 to 90% decrease Third time: ion species: B + , acceleration energy: first time increase of 3 to 10%, implantation angle: 7 °, dose amount: normal 80 ~ 90% reduction As described above, by performing ion implantation near the interface between the SOI layer 103 and the buried insulating film 102 under the conditions as described above, the peak width of the impurity concentration introduced into the channel is widened as shown in FIG. Therefore, a change in the ratio between the total amount of impurities introduced into the channel formation portion 106 and the total amount of impurities introduced into the buried insulating film 103 due to variations in the SOI layer thickness 103 can be reduced. That is, the threshold value of the NMOS transistor is almost constant even if the SOI layer film thickness 203 varies.

さらにチャネル形成のためのイオン注入はＳＯＩ層１０３／埋め込み絶縁膜１０２界面付近にチャネル形成部に導入される不純物濃度のピークをもってきているため従来どおり寄生チャネルがオンするのを防止することができる。ここでは、例としてイオン注入回数を３回としたが加速エネルギーおよびドーズ量を調整して行えば、注入回数は変更可能である。   Further, since ion implantation for channel formation has a peak of the impurity concentration introduced into the channel formation portion in the vicinity of the SOI layer 103 / buried insulating film 102 interface, it is possible to prevent the parasitic channel from being turned on as usual. . Here, the number of ion implantations is three as an example, but the number of implantations can be changed by adjusting the acceleration energy and the dose amount.

次に、図２（ａ）に示すように、犠牲酸化膜１１３をフッ酸（ＨＦ）系の溶液にてエッチングした後、ゲート絶縁膜１０５を例えば数十ｎｍ成長させ、続いて多結晶シリコンゲート１０７となるＰｏｌｙＳｉを例えば１５０ｎｍ堆積、多結晶シリコンゲート１０７に不純物（リン等）を導入した後、パターニングする。   Next, as shown in FIG. 2A, after the sacrificial oxide film 113 is etched with a hydrofluoric acid (HF) -based solution, a gate insulating film 105 is grown, for example, several tens of nanometers, followed by a polycrystalline silicon gate. PolySi to be 107 is deposited by, for example, 150 nm, an impurity (phosphorus or the like) is introduced into the polycrystalline silicon gate 107, and then patterned.

次に、図２（ｂ）に示すように、ドレインおよびソース高濃度領域１０８、１０９となる拡散層に不純物として、例えばＡｓを、シート抵抗を低減するため、好ましくは１×１０14〜１×１０16atoms／cm2の濃度でイオン注入した後、不純物の活性化のための熱処理を例えば以下の条件にて行う。 Next, as shown in FIG. 2B, for example, As is used as an impurity in the diffusion layer that becomes the drain and source high-concentration regions 108 and 109 to reduce the sheet resistance, preferably 1 × 10 14 to 1 ×. after ion implantation at a concentration of 10 16 atoms / cm 2, performing heat treatment for activating the impurity, for example, by the following conditions.

９５０℃、１０秒、Ｎ2雰囲気中、ＲＴＡ処理
その後は、通常の半導体装置の製造工程によって、２００ｎｍ〜８００ｎｍ程度の層間絶縁膜１１０の堆積とコンタクトホール１１１の形成、スパッタ法によりメタル１１２形成を順次行い、図３に示すような完全空乏型ＳＯＩＮＭＯＳトランジスタ１を構成する。 950 ° C., 10 seconds, N 2 atmosphere, RTA treatment After that, by a normal manufacturing process of a semiconductor device, deposition of an interlayer insulating film 110 of about 200 nm to 800 nm, formation of a contact hole 111, and formation of a metal 112 by a sputtering method This is performed sequentially to form a fully depleted SOI NMOS transistor 1 as shown in FIG.

このような製造方法により、完全空乏型ＳＯＩトランジスタ１が形成され、各全空乏型ＳＯＩトランジスタ１の閾値は、ＳＯＩ層膜厚のばらつきがあってもほぼ一定に揃えられることになる。   By such a manufacturing method, the fully depleted SOI transistor 1 is formed, and the threshold value of each fully depleted SOI transistor 1 is made substantially constant even if the SOI layer thickness varies.

本実施形態では、犠牲酸化膜１１３を通して、イオン注入を複数回行い、不純物の総量の変化を抑制しているが、犠牲酸化膜を堆積させずにゲート絶縁膜１０５を用いて行っても良いし、その後の多結晶シリコンゲート１０７を堆積させ、多結晶シリコンゲート１０７のパターニング前後で行っても良い。   In this embodiment, ion implantation is performed a plurality of times through the sacrificial oxide film 113 to suppress changes in the total amount of impurities. However, the gate insulating film 105 may be used without depositing the sacrificial oxide film. Thereafter, the polycrystalline silicon gate 107 may be deposited, and the process may be performed before and after the patterning of the polycrystalline silicon gate 107.

本発明による半導体装置の製造方法の第一の実施例を示す工程順模式的断面図Sectional schematic cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention. 本発明による半導体装置の製造方法の第一の実施例を示す工程順模式的断面図(続き)Sectional schematic cross-sectional view showing a first embodiment of a semiconductor device manufacturing method according to the present invention (continued) 本発明による半導体装置の製造方法の第一の実施例を示す工程順模式的断面図(続き)Sectional schematic cross-sectional view showing a first embodiment of a semiconductor device manufacturing method according to the present invention (continued) 本発明と従来のチャネル形成における不純物の濃度プロファイルの比較図Comparison diagram of impurity concentration profiles in the present invention and conventional channel formation 従来の半導体装置の製造方法の工程順模式的断面図Schematic cross-sectional view in order of processes in a conventional semiconductor device manufacturing method 従来の半導体装置の製造方法の工程順模式的断面図(続き)Sectional schematic cross-sectional view of conventional semiconductor device manufacturing method (continued) 従来の半導体装置の製造方法の工程順模式的断面図(続き)Sectional schematic cross-sectional view of conventional semiconductor device manufacturing method (continued)

符号の説明Explanation of symbols

１０１、２０１ 支持基板
１０２、２０２ 埋め込み絶縁膜
１０３、２０３ ＳＯＩ層
１０４、２０４ フィールド絶縁膜
１０５、２０５ ゲート絶縁膜
１０６、２０６ チャネル形成部
１０７、２０７ 多結晶シリコンゲート(ゲート電極)
１０８、２０８ ドレイン高濃度領域
１０９、２０９ ソース高濃度領域
１１０、２１０ 層間絶縁膜
１１１、２１１ コンタクトホール
１１２、２１２ メタル
１１３、２１３ 犠牲酸化膜 101, 201 Support substrate 102, 202 Embedded insulating film 103, 203 SOI layer 104, 204 Field insulating film 105, 205 Gate insulating film 106, 206 Channel forming portion 107, 207 Polycrystalline silicon gate (gate electrode)
108, 208 Drain high concentration region 109, 209 Source high concentration region 110, 210 Interlayer insulating film 111, 211 Contact hole 112, 212 Metal 113, 213 Sacrificial oxide film

Claims (6)

半導体支持基板上に形成された絶縁膜と前記絶縁膜上に形成された半導体薄膜層から構成されるＳＯＩ(Silicon On Insulator)基板の前記半導体薄膜層上に形成された完全空乏型ＳＯＩトランジスタを有する半導体装置の製造方法におけるチャネルを形成する工程において前記半導体薄膜層と前記絶縁膜との界面に、不純物量を分割して加速エネルギーを変え、第１導電型の不純物の注入を複数回行う工程を有することを特徴とする半導体装置の製造方法。   A fully depleted SOI transistor formed on the semiconductor thin film layer of an SOI (Silicon On Insulator) substrate comprising an insulating film formed on a semiconductor supporting substrate and a semiconductor thin film layer formed on the insulating film; A step of dividing the amount of impurities at the interface between the semiconductor thin film layer and the insulating film to change the acceleration energy and injecting the first conductivity type impurities a plurality of times in the step of forming a channel in the method of manufacturing a semiconductor device; A method for manufacturing a semiconductor device, comprising: 前記第１導電型の不純物の注入を、犠牲酸化膜を介して行うことを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity of the first conductivity type is implanted through a sacrificial oxide film. 前記第１導電型の不純物の注入を、ゲート絶縁膜を介して行うことを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity is implanted through a gate insulating film. 前記第１導電型の不純物の注入を、トランジスタのゲート電極を介して行うことを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity is implanted through a gate electrode of a transistor. 前記チャネルはＮ型トランジスタのチャネルであり、前記第１導電型の不純物はボロンであることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the channel is a channel of an N-type transistor, and the impurity of the first conductivity type is boron. 注入された前記第１導電型の不純物は前記半導体薄膜層と前記絶縁膜との界面付近に濃度のピークを有することを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the implanted impurity of the first conductivity type has a concentration peak near an interface between the semiconductor thin film layer and the insulating film.
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JPH02306665A (en) * 1989-05-20 1990-12-20 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH08111511A (en) * 1994-10-06 1996-04-30 Sony Corp Fabrication of semiconductor device
JPH09831A (en) * 1995-06-23 1997-01-07 Janome Sewing Mach Co Ltd 24 hour bath water purifying and circulating apparatus
JP2001274403A (en) * 2000-03-23 2001-10-05 Fujitsu Ltd Thin-film transistor and method of manufacturing the same
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