JP2007020362A - Parallel operation method of inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem, wherein when an abnormality occurs in an inverter device of a power supply system, the total input power value of the power supply system and the output power value fed from a DC power supply do not substantially match each other, thus resulting in the deterioration of conversion efficiency. <P>SOLUTION: A plurality of the inverter devices, having identical capacities are connected to the DC power supply in parallel therewith, the inverter device comprises an MPPT-control master inverter device and a constant power-control slave inverter device, the master device sums a measurement value of own share input power value and a command value of a share input power value of the slave device in starting, and calculates the total input power value fed from the DC power supply; and the inverter device selects the number of starting units of the slave devices in the next cycle, on the basis of the calculated value, the command value, and a next-cycle starting candidate. In the parallel operation method for the inverter devices, the master device monitors the operating state of each slave device during starting, the slave device in an abnormal state is excluded from the calculation of the total input power value and are also excluded from the frame of the next-cycle starting candidate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply system that converts DC power from a DC power source such as a solar cell or a fuel cell into AC power by an inverter device connected in parallel and supplies it to a system power source. It is about technology.

  FIG. 7 is a block diagram of a power supply system in which a plurality of inverter devices in the prior art are connected in parallel. In the figure, a DC power supply SC is composed of a solar cell, a fuel cell, etc., and the power supply system converts the DC power from the DC power supply SC into an AC output by an inverter circuit and outputs the AC output in parallel. PI1 thru | or the nth inverter apparatus PIn, and the input power detection circuit DS which measures the shared input power value of the said 1st inverter apparatus PI1, and outputs it as the shared input power value Ds are formed.

  In FIG. 7, the first inverter device PI1 is formed of a first inverter control circuit CW1 and a first inverter circuit PC1, and the first inverter device PI1 is a master inverter device, and the second inverter device PI2 is a second inverter. The control circuit CW2 and the second inverter circuit PC2 are formed. The nth inverter device PIn is formed of the nth inverter control circuit CWn and the nth inverter circuit PCn, and the second inverter device PI2 to the nth inverter device PIn are connected to each other. A slave inverter device is used.

  The first inverter control circuit CW1 is formed by the power calculation circuit CO, the control circuit MS, and the transmission / reception circuit TC shown in FIG. 8, and the second inverter control circuit CW2 to the nth inverter control circuit CWn are also formed by the same circuit as described above. The

  The power calculation circuit CO of the first inverter device PI1, which is the master inverter device, calculates the shared input power value Ds detected by the input power detection circuit DS for each predetermined period, and controls the control circuit MS as the input power value Ci. To enter.

  The control circuit MS of the master inverter device adds the input power value Ci and the command value of the shared input power value Ms of each active slave inverter device for each predetermined period, and is supplied from a DC power supply. A total input power value is calculated, Mi of the first inverter circuit PC1 of the master inverter device in the current cycle is determined based on the total input power value of the previous cycle, and the next based on the total input power value of the current cycle. The command value Ms of each slave inverter device in the cycle is determined. The transmission / reception circuit TC converts the command value Ms of the shared input power value of the next cycle into a transmission / reception signal Tc, and transmits the transmission / reception signal Tc to the second inverter device PI2 to the nth inverter device PIn which are slave inverter devices.

  Next, the operation of the above-described prior art will be described using the flowchart shown in FIG.

  In Step 10 shown in FIG. 9, the first inverter device PI1 which is the master inverter device measures the shared input power value Ds of the master inverter device.

  In step 20, the control circuit MS of the master inverter device adds up the command value Ms of the shared input power value of each slave inverter device that is being activated and the measured shared input power value Ds of the master inverter device, and Calculate the total input power value.

  In step 30, the control circuit MS of the master inverter device determines the number of slave inverter devices to be activated and the command value for the next period and also selects the slave inverter device to be activated based on the total input power value.

  In step 40, the control circuit MS of the master inverter device transmits the command value Ms of the shared input power value of the next cycle to each selected slave inverter device via the transmission / reception circuit TC.

  In step 50, the control circuit MS of each slave inverter device receives the command value Ms of the shared input power value transmitted from the first inverter device PS1 that is the master inverter device.

  In step 60, the control circuit MS of each selected slave inverter device sets the received command value Ms of the shared input power value as the target output power value, and in the next cycle based on the target output power value, each slave inverter circuit The constant power control. Thereafter, the process returns to step 10 to repeat the same operation as described above.

  As described above, even if the second inverter device PI2 to the nth inverter device PIn, which are slave inverter devices, are operated in parallel, the constant power control is performed so that the output power values of the slave inverter devices are substantially the same.

  Patent Document 1 discloses a parallel operation technique in which the output power values of the above-described inverter devices are substantially the same and output control is performed.

JP 2004-236394 A

  According to the above-described prior art, in a parallel operation method in which a plurality of inverter devices having the same capacity are connected in parallel, a predetermined inverter device is a master inverter device, and the master inverter device measures its own shared input power value. The total input power value is calculated by adding the value and the command value of the shared input power value of each active slave inverter device, and the command value of each slave inverter device is determined based on the total input power value, Since constant power control is performed based on the command value, when the slave inverter is operating normally, the calculated total input power value is substantially the same as the output power value supplied from the DC power supply to the power supply system. However, in the above, since the master inverter device does not sequentially monitor the operating state of the slave inverter device that is being activated, even if an abnormal stop state occurs in the slave inverter device, any slave inverter device has an abnormal stop state. It cannot be determined whether it has occurred, and the slave inverter device in the abnormally stopped state cannot be excluded from the start frame. Therefore, the total input power value calculated when the abnormal stop state occurs is that the master inverter device is also starting the slave inverter device in the abnormal stop state, and the command value of the shared input power value is added to the total input power value. As a result, the total input power value of the power supply system and the output power value supplied from the DC power supply to the power supply system are not substantially the same, resulting in a large difference.

  Then, in this invention, it is providing the parallel operation method of the inverter apparatus which solves the subject mentioned above.

  In order to solve the above-described problem, the first invention is that a plurality of inverter devices of the same capacity are connected in parallel to a DC power source, and the inverter device includes a master inverter device of MPPT control and a slave inverter device of constant power control The master inverter device is configured to add the measured value of the shared input power value of the master inverter device and the command value of the shared input power value of each of the slave inverter devices that are being activated for each predetermined period. Calculate the total input power value supplied from the DC power supply, and based on the total input power value, start the number of slave inverter devices in the next cycle, command value of the shared input power value, and start the next cycle of the slave inverter device In the parallel operation method of the inverter device for selecting candidates, the master inverter device is The operation state of each slave inverter device is monitored, and the slave inverter device whose operation state is in an abnormally stopped state is excluded from the calculation of the total input power value and also excluded from the next period start candidate frame. This is a parallel operation method of inverter devices.

  According to a second aspect of the invention, the master inverter device monitors the operation state of each of the slave inverter devices, and returns to the next cycle start candidate frame when the abnormal stop state of the slave inverter device is released. The parallel operation method of the inverter device according to claim 1.

  According to the first invention, the master inverter device sequentially monitors the operation state of each slave inverter device, and when an abnormal stop state occurs, determines which slave inverter device among the slave inverter devices is in an abnormal stop state. Since the abnormally stopped slave inverter device is excluded from the starting frame and the command value of the shared input power value of the abnormally stopped slave inverter device is excluded from the calculation of the total input power value, The total input power value calculated when the abnormality occurs and the output power value supplied to the power supply system from the DC power supply are substantially the same value, and even if an abnormal stop state occurs in the slave inverter device, the conversion efficiency is not lowered. Stable operation is possible.

  According to the second invention, when the abnormality of the slave inverter device in the abnormally stopped state is released, the slave inverter device returns to the next cycle start frame after the release, so that the load on each slave inverter device can be reduced and the service life is improved. Can do.

[Embodiment 1]
FIG. 1 is a block diagram of a power supply system according to Embodiment 1 of the present invention. In the figure, the same reference numerals as those in the block diagram of the conventional power supply system shown in FIG.

  In FIG. 1, a power supply system includes a first inverter device PI1 to an nth inverter device PIn that are connected in parallel to the DC power supply SC and that converts DC power into AC power by an inverter and outputs it, and the first inverter device PI1. An input power detection circuit DS that measures a shared input power value and a first switch SW1 to an nth switch SWn that are connected in parallel to the DC power supply SC and open and close each of the inverter devices.

  The first inverter device PI1 is an MPPT-controlled master inverter device. The master inverter device PI1 is formed by a master inverter main control circuit CM1 and a master inverter circuit PM1, and the second inverter device PI2 is a constant power control slave. The inverter device is formed of a slave inverter main control circuit CS2 and a slave inverter circuit PS2, and the nth inverter device PIn is also a slave inverter device of constant power control, and the nth slave inverter main control circuit CSn and the nth slave inverter. The circuit PSn is formed.

  The master inverter main control circuit CM1 shown in FIG. 1 is formed by the power calculation circuit CO, the main control circuit MA, and the transmission / reception circuit TC shown in FIG. 2, and the slave inverter main control circuit CS2 to the nth slave inverter control circuit CSn are also included. It is formed by the same circuit as above.

  The power calculation circuit CO of the master inverter main control circuit CM1 shown in FIG. 2 calculates a shared input power value Ds detected by the input power detection circuit DS for each predetermined period and sets it as an input power value Ci. Input to MA. The main control circuit MA calculates the total input power value supplied from the DC power source by adding the input power value Ci for each cycle and the command value Mas of the shared input power value of each activated slave inverter device. Then, based on the total input power value, the number of slave inverter devices to be activated, the command value, and the activation candidate for the next cycle are determined.

  The transmission / reception circuit TC of the master inverter main control circuit CM1 transmits the command value Mas of the shared input power value to each slave inverter device selected by the main control circuit MA, and the main control circuit MA of each slave inverter device receives it. Each slave inverter circuit is controlled at a constant power based on the command value Mas.

  Next, the operation of the present invention will be described using the flowchart shown in FIG. 3 and the timing chart shown in FIG.

  In step 10 shown in FIG. 3, the first inverter device PI1, which is the master inverter device, confirms the number of slave inverter devices activated during the time t = t1 to t2 shown in FIG. The shared input power value Ds of the master inverter device at the time is measured.

  In step 20, the main control circuit MA of the master inverter device determines the command value Mas of the shared input power value of each slave inverter device being activated from time t = t1 to t2, and the master inverter measured at time t = t2. The total input power value Tp2 of the power supply system at time t = t2 shown in FIG. 6 is calculated by adding together the shared input power value Ds of the apparatus.

  In step 30, the main control circuit MA of the master inverter device, based on the total input power value Tp2 at time t = t2, determines the number of slave inverter devices activated and the command during the time t = t2 to t3 of the next cycle. The slave inverter device that determines and activates the value is also selected.

  In step 40, the main control circuit MA of the master inverter device sends the command value Mas of the shared input power value during the period t = t2 to t3 of the next cycle to the selected slave inverter devices via the transmission / reception circuit TC. Send.

  In step 50, the main control circuit MA of each slave inverter device receives the command value Mas of the shared input power value transmitted from the first inverter device PS1, which is the master inverter device, via the transmission / reception circuit TC.

  In step 60, the main control circuit MA of each selected slave inverter device sets the received command value Mas of the shared input power value as the target output power value, and at the next cycle time t = t2 based on the target output power value. During the period of t3, constant power control is performed on each slave inverter circuit.

  In step 70, the main control circuit MA of the master inverter device confirms the operating state of each slave inverter that is being activated at time t = t2 to t3.

  In step 80, an abnormality is determined, and when each slave inverter device is not in an abnormally stopped state, the process proceeds to step 110. In step 110, the selected slave inverter device is connected to the master inverter device via the transmission / reception circuit TC. Then, it transmits that it is operating normally, and thereafter returns to Step 10.

  In step 10 shown in FIG. 3, the first inverter device PI1, which is the master inverter device, confirms the number of slave inverter devices activated during the period from time t = t2 to t3 shown in FIG. 6, and when time t = t3. The shared input power value Ds of the master inverter device is measured. Thereafter, the same operation as described above is repeated.

  In step 80, an abnormality is determined, and if there is an abnormal stop state in each of the slave inverter devices, the process proceeds to step 90.

  In step 90, the main control circuit MA of the master inverter device determines the slave inverter device in the abnormally stopped state. For example, when the second inverter device PI2 that is the slave inverter device is in the abnormally stopped state, the main inverter circuit MA Then, the start / stop command is transmitted, and the second switch SW2 connected to the second inverter device PI2 is input to the second switch SW2 to be opened and excluded from the next cycle start candidate frame.

  In Step 100, the second inverter device PI2 in the abnormally stopped state receives the start / stop command, and the slave inverter circuit stops starting.

  In step 110, each of the normally activated slave inverter devices, excluding the abnormal slave inverter device, transmits an operation state to the master inverter device via the transmission / reception circuit TC. Thereafter, the process returns to step 10.

[Embodiment 2]
The operation of the second embodiment of the present invention will be described with reference to the flowchart shown in FIG. 4 and the timing chart shown in FIG.

  The flowchart shown in FIG. 4 is the same as the flowchart shown in FIG. 3 except that only the steps 101 and 102 are added to the flowchart of the first embodiment shown in FIG.

  In step 80, an abnormality is determined, and if there is no abnormal stop state in each of the slave inverter devices, the process proceeds to step 110.

  In step 80, an abnormality is determined, and if there is an abnormal stop state in each of the slave inverter devices, the process proceeds to step 90.

In step 90, the main control circuit MA of the master inverter device discriminates the slave inverter device in the abnormally stopped state, transmits a start / stop command via the transmission / reception circuit TC, and is connected to the abnormal slave inverter device. And is excluded from the next cycle activation candidate frame.

  In step 100, the slave inverter device in the abnormally stopped state receives the start / stop command, and the slave inverter circuit stops starting.

  In step 101, it is determined whether or not an abnormality has been resolved. If the abnormal stop state continues, the process proceeds to step 110. In step 110, the operating state is transmitted to the master inverter device from the slave inverter devices that have been normally started without any abnormality via the transmission / reception circuit TC. Thereafter, the process returns to step 10 of the next cycle, and the same operation as described above is repeated.

  In step 101, it is determined whether or not an abnormality has been resolved. In step 102, the slave inverter device that has been released from the abnormality is returned to the next cycle activation candidate frame, and the switch connected to the slave inverter device from which the abnormality has been removed is closed, and the process proceeds to step 110.

[Embodiment 3]
FIG. 5 is a block diagram of a power supply system according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in the block diagram of the power supply system according to the first embodiment shown in FIG.

  In FIG. 5, the power supply system includes a first inverter device PI1 to an nth inverter device PIn that is connected in parallel to the DC power supply SC and converts DC power to AC power by an inverter and outputs the first inverter device PI1. The output power detection circuit AS that measures the shared output power value As of the inverter device PI1 and the switches SW1 to SWn that are connected in parallel to the DC power supply SC and open and close the inverter devices.

  The power calculation circuit CO of the master inverter main control circuit CM1 shown in FIG. 5 calculates the shared output power value As detected by the output power detection circuit AS every predetermined period, and outputs it as the output power value Co. Input to MA. The main control circuit MA adds the output power value Co and the command value Mas of the shared output power value of the activated slave inverter device to calculate the total output power value supplied from the power supply system to the system power supply AC. Based on the total output power value, the number of start of the slave inverter device in the next cycle, the command value, and the next cycle start candidate of the slave inverter device are selected.

1 is a block diagram of a power supply system according to Embodiment 1 of the present invention. FIG. 2 is a detailed diagram of a master inverter main control circuit shown in FIG. 1. It is a flowchart explaining the operation | movement of Embodiment 1 of this invention. It is a flowchart explaining the operation | movement of Embodiment 2 of this invention. It is a block diagram of the power supply system which concerns on Embodiment 3 of this invention. It is a timing diagram explaining operation | movement of embodiment of this invention. It is a block diagram of a power supply system in which a plurality of inverter devices in the prior art are connected in parallel. FIG. 8 is a detailed diagram of a first inverter main control circuit shown in FIG. 7. It is a flowchart explaining operation | movement of a prior art.

Explanation of symbols

AC power supply AS output power detection circuit CO power calculation circuit CM1 master inverter main control circuit CS2 slave inverter main control circuit CSn nth slave inverter main control circuit CW1 first inverter control circuit CW2 second inverter control circuit CWn nth inverter control circuit DS input power detection circuit MA main control circuit MS control circuit PC1 first inverter circuit PC2 second inverter circuit PCn nth inverter circuit PM1 master inverter circuit PS2 slave inverter circuit PSn nth slave inverter circuit PI1 first inverter device PI2 second inverter Device PIn nth inverter device SC DC power supply (solar cell, fuel cell, etc.)
SW1 1st switch SW2 2nd switch SWn nth switch TC Transmission / reception circuit

As shared output power value Ci input power value Co output power value Ds shared input power value Mi control signal Ms command value of shared input power value Mas command value of shared input power value (or start monitoring signal)
Sw1 First open / close signal Sw2 Second open / close signal Sw3 Third open / close signal Tc Transmission / reception signal

Claims (2)

  A plurality of inverter devices of the same capacity are connected in parallel to a DC power source, and the inverter device comprises an MPPT-controlled master inverter device and a constant-power control slave inverter device, and the master inverter device is set at predetermined intervals. The total input power value supplied from the DC power source is calculated by adding the measured value of the shared input power value of the master inverter device and the command value of the shared input power value of each of the slave inverter devices being activated, In the parallel operation method of an inverter device that selects the number of slave inverter devices activated in the next cycle based on the total input power value, the command value of the shared input power value, and the next cycle activation candidate of the slave inverter device, the master The inverter device monitors the operating status of each slave inverter device that is running , Is the slave inverter device operation state is in an abnormal stop state also eliminates from excluded and the next cycle start candidate frame from the calculation of the total input power value, parallel operation method of an inverter apparatus, characterized in that. The said master inverter apparatus monitors the operation state of each said slave inverter apparatus, and will return to the said next period starting candidate frame, if the abnormal stop state of the said slave inverter apparatus is cancelled | released. Method for parallel operation of inverter devices.

Images