JP2007011947A - Power source regulator circuit - Google Patents

Power source regulator circuit Download PDF

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JP2007011947A
JP2007011947A JP2005194884A JP2005194884A JP2007011947A JP 2007011947 A JP2007011947 A JP 2007011947A JP 2005194884 A JP2005194884 A JP 2005194884A JP 2005194884 A JP2005194884 A JP 2005194884A JP 2007011947 A JP2007011947 A JP 2007011947A
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voltage
type mosfet
terminal
power supply
output
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Emiko Yoshida
絵美子 吉田
Koichi Notoya
晃一 能登谷
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Toshiba Corp
Toshiba Electronic Device Solutions Corp
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Toshiba Corp
Toshiba Microelectronics Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a power source regulator circuit wherein fluctuation of an output voltage is small even without adding a capacitor to an output terminal. <P>SOLUTION: This power source regulator circuit has: a P-type MOSFET 1 connected to between an input power source terminal 10 and the output terminal 20; resistors R1, R2 connected to between the output terminal 20 and a ground terminal 30; a comparator 3 comparing a feedback voltage Vfb obtained by dividing the output voltage Vout of the output terminal 20 by the resistors R1, R2 and a reference voltage Vref generated by a reference voltage generation circuit 2, and changing a voltage inputted to a gate terminal of the P-type MOSFET 1 such that the feedback voltage Vfb accords with the reference voltage Vref; an N-type MOSFET 4 connected to the P-type MOSFET 1 in parallel, turning off when the output voltage Vout is a prescribed voltage, and turning on when the output voltage Vout falls; and a constant voltage generation circuit 5A generating a gate voltage of the N-type MOSFET 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電源レギュレータ回路に関し、特に入力電源電圧を降圧して所定の出力電圧を発生する電源レギュレータ回路に関する。   The present invention relates to a power supply regulator circuit, and more particularly to a power supply regulator circuit that generates a predetermined output voltage by stepping down an input power supply voltage.

CMOS型LSIの素子数の増加に伴い、CMOS型LSIの発熱が大きな問題となっている。その対策の1つとして、CMOS型LSI内部の動作電圧を下げることが有効である。一方、CMOS型LSIの入出力部は、外部とのインターフェースの仕様上、従来の動作電圧を使用しなければならない場合がある。そこで、CMOS型LSIの入出力部へは、従来の高い電圧で供給される電源電圧をそのまま与え、CMOS型LSI内部回路へは、この電源電圧を降圧して低い電圧を与えることが行われる。そのため、CMOS型LSIの内部に、入力電源電圧を降圧して所定の出力電圧を発生する電源レギュレータ回路を組み込むことがある。   With the increase in the number of elements of a CMOS LSI, heat generation of the CMOS LSI has become a big problem. As one of the countermeasures, it is effective to lower the operating voltage inside the CMOS LSI. On the other hand, the input / output unit of the CMOS LSI may need to use a conventional operating voltage due to the specifications of the interface with the outside. Therefore, a conventional power supply voltage supplied at a high voltage is directly applied to the input / output section of the CMOS LSI, and a low voltage is applied to the CMOS LSI internal circuit by stepping down the power supply voltage. Therefore, a power supply regulator circuit that steps down the input power supply voltage and generates a predetermined output voltage may be incorporated in the CMOS LSI.

CMOS型LSIに組み込まれる電源レギュレータ回路として、P型MOSFETのソース端子を入力電源端子に接続し、ドレイン端子に抵抗負荷を接続して、このドレイン端子の電圧を出力電圧Voutとする回路が用いられる。   As a power supply regulator circuit incorporated in a CMOS type LSI, a circuit is used in which a source terminal of a P-type MOSFET is connected to an input power supply terminal, a resistance load is connected to the drain terminal, and the voltage at the drain terminal is used as the output voltage Vout. .

この電源レギュレータ回路では、上述の負荷抵抗をP型MOSFETのドレイン端子と接地端子との間に直列に接続した2つの抵抗R1、R2とし、この抵抗R1、R2で出力電圧Voutを分圧した電圧を帰還電圧Vfbとして、基準電圧Vrefと比較する比較器を設け、この比較器の出力をP型MOSFETのゲート端子に入力する回路構成がとられる。   In this power supply regulator circuit, the load resistor described above is two resistors R1 and R2 connected in series between the drain terminal and the ground terminal of the P-type MOSFET, and a voltage obtained by dividing the output voltage Vout by the resistors R1 and R2. Is provided as a feedback voltage Vfb, and a comparator for comparing with the reference voltage Vref is provided, and the output of this comparator is input to the gate terminal of the P-type MOSFET.

このような構成の電源レギュレータ回路において、比較器がVfb=VrefとなるようにP型MOSFETのゲート電圧を変化させることにより出力電圧Voutを制御することが行われる。このような帰還制御を行うことにより、P型MOSFETのドレイン端子からVout=Vref×(1+R1/R2)となる一定の出力電圧が得られる。   In the power supply regulator circuit having such a configuration, the output voltage Vout is controlled by changing the gate voltage of the P-type MOSFET so that the comparator satisfies Vfb = Vref. By performing such feedback control, a constant output voltage Vout = Vref × (1 + R1 / R2) is obtained from the drain terminal of the P-type MOSFET.

ただし、このような帰還制御には次のような問題がある。それは、帰還経路に抵抗R1、R2が存在するため、その抵抗値が帰還速度を決定する1つの要因になることである。   However, such feedback control has the following problems. That is, since the resistors R1 and R2 exist in the feedback path, the resistance value is one factor that determines the feedback speed.

例えば、モバイル用途のLSIでは低消費電力が要求されるので、抵抗に流れる電流を少なくするため、抵抗R1、R2の抵抗値を1MΩ以上にすることがある。このような場合、電源レギュレータ回路の負荷電流が急激に増加して出力電圧Voutが急激に低下すると、電源レギュレータ回路の比較器が出力電圧Voutを元に戻そうとするが、抵抗R1、R2と寄生容量のために帰還電圧Vfbの変化が遅く、また、比較器が所望の電圧を出力するまでの時間が長い場合もあり、出力電圧Voutの回復に長い時間を要する。   For example, since low power consumption is required in an LSI for mobile use, the resistance values of the resistors R1 and R2 may be set to 1 MΩ or more in order to reduce the current flowing through the resistors. In such a case, when the load current of the power supply regulator circuit increases rapidly and the output voltage Vout decreases rapidly, the comparator of the power supply regulator circuit tries to restore the output voltage Vout, but the resistors R1 and R2 Due to the parasitic capacitance, the change in the feedback voltage Vfb is slow, and it may take a long time for the comparator to output a desired voltage, and it takes a long time to recover the output voltage Vout.

そこで、電源レギュレータ回路の負荷電流が急激に変化しても出力電圧Voutが急激に変化しないように、電源レギュレータ回路の出力端子、すなわちP型MOSFETのドレイン端子にコンデンサを付加することが行われる(例えば、特許文献1参照。)
このコンデンサの付加により、出力電圧Voutの変動を小さくすることができるが、抵抗R1、R2の抵抗値が1MΩ以上であるような場合や、Voutの負荷電流が数十μAである場合、十分な出力電圧変動抑制効果を得るには、コンデンサの容量を1μF程度の大容量にしなければならない。
Therefore, a capacitor is added to the output terminal of the power supply regulator circuit, that is, the drain terminal of the P-type MOSFET so that the output voltage Vout does not change suddenly even if the load current of the power supply regulator circuit changes suddenly ( For example, see Patent Document 1.)
By adding this capacitor, the fluctuation of the output voltage Vout can be reduced. However, when the resistance values of the resistors R1 and R2 are 1 MΩ or more, or when the load current of Vout is several tens of μA, it is sufficient. In order to obtain the output voltage fluctuation suppressing effect, the capacitance of the capacitor must be as large as about 1 μF.

しかし、このような大容量のコンデンサをLSIの内部に形成するには膨大な面積を必要とし、LSIのチップサイズを考慮すると、現実的には、LSIの内部にこのコンデンサを形成することができないという問題があった。また、このコンデンサを外付け部品としてLSIの外部端子に接続するようにすると、LSIを搭載する基板の部品点数の増加、基板作成工程の増加を招くという問題があった。
特開2004−341877号公報 (第9ページ、図4)
However, in order to form such a large-capacity capacitor inside the LSI, an enormous area is required, and considering the chip size of the LSI, it is practically impossible to form this capacitor inside the LSI. There was a problem. Further, if this capacitor is connected as an external component to the external terminal of the LSI, there is a problem that the number of parts of the board on which the LSI is mounted is increased and the board production process is increased.
JP 2004-341877 A (9th page, FIG. 4)

そこで、本発明の目的は、出力端子にコンデンサを付加しなくても出力電圧の変動が小さい電源レギュレータ回路を提供することにある。   Accordingly, an object of the present invention is to provide a power supply regulator circuit in which fluctuation of the output voltage is small without adding a capacitor to the output terminal.

本発明の一態様によれば、入力電源端子にソース端子が接続され、出力端子にドレイン端子が接続されるP型MOSFETと、前記出力端子と接地端子との間に接続される第1および第2の抵抗と、前記出力端子の出力電圧を前記第1および第2の抵抗で分圧した帰還電圧と基準電圧とを比較し、前記帰還電圧が前記基準電圧と一致するよう前記P型MOSFETのゲート端子へ入力する電圧を変化させる比較器とを備え、前記P型MOSFETに並列に接続され、前記出力電圧が所定の電圧のときはオフしていて、前記出力電圧が低下したときにオンするN型MOSFETを有することを特徴とする電源レギュレータ回路が提供される。   According to one aspect of the present invention, a P-type MOSFET having a source terminal connected to the input power supply terminal and a drain terminal connected to the output terminal, and the first and second terminals connected between the output terminal and the ground terminal. 2 and a feedback voltage obtained by dividing the output voltage of the output terminal by the first and second resistors, and a reference voltage, and the P-type MOSFET of the P-type MOSFET is matched so that the feedback voltage matches the reference voltage. A comparator for changing a voltage input to the gate terminal, connected in parallel to the P-type MOSFET, and turned off when the output voltage is a predetermined voltage and turned on when the output voltage is lowered. A power supply regulator circuit comprising an N-type MOSFET is provided.

本発明によれば、負荷電流が急激に増加して出力電圧が下がるとN型MOSFETが速やかに導通して負荷電流を供給するので、出力電圧の変動を小さくすることができる。   According to the present invention, when the load current suddenly increases and the output voltage decreases, the N-type MOSFET quickly conducts and supplies the load current, so that fluctuations in the output voltage can be reduced.

以下、本発明の実施例を図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図1は、本発明の実施例1に係る電源レギュレータ回路の構成の例を示す回路図である。   1 is a circuit diagram showing an example of the configuration of a power regulator circuit according to a first embodiment of the present invention.

本実施例の電源レギュレータ回路は、入力電源端子10にソース端子が接続され、出力端子20にドレイン端子が接続されるP型MOSFET1と、入力電源端子10と接地端子30とに接続されて基準電圧Vrefを生成する基準電圧生成回路2と、出力端子20と接地端子30との間に直列に接続され、出力電圧Voutを分圧した帰還電圧Vfbを生成する抵抗R1および抵抗R2と、反転入力(−)端子に入力された基準電圧Vrefの値と、非反転入力(+)端子に入力された帰還電圧Vfbの値とを比較し、その差分に応じた電圧をP型MOSFET1のゲート端子へ入力する比較器3とからなる従来の電源レギュレータ回路に、P型MOSFET1に並列に接続されて、入力電源端子10にドレイン端子が接続され、出力端子20にソース端子が接続されるN型MOSFET4を設け、さらに、入力電源端子10と接地端子30とに接続されてN型MOSFET4のゲート端子へ与える定電圧を生成する定電圧生成回路5Aを備えた構成を有する。   The power supply regulator circuit of this embodiment is connected to a P-type MOSFET 1 having a source terminal connected to the input power supply terminal 10 and a drain terminal connected to the output terminal 20, and to a reference voltage connected to the input power supply terminal 10 and the ground terminal 30. A reference voltage generation circuit 2 that generates Vref, a resistor R1 and a resistor R2 that are connected in series between the output terminal 20 and the ground terminal 30, generate a feedback voltage Vfb obtained by dividing the output voltage Vout, and an inverting input ( The value of the reference voltage Vref input to the −) terminal is compared with the value of the feedback voltage Vfb input to the non-inverting input (+) terminal, and a voltage corresponding to the difference is input to the gate terminal of the P-type MOSFET 1. Is connected in parallel to the P-type MOSFET 1 and has a drain terminal connected to the input power supply terminal 10 and an output terminal. An N-type MOSFET 4 whose source terminal is connected to 0 is provided, and a constant voltage generation circuit 5A that is connected to the input power supply terminal 10 and the ground terminal 30 and generates a constant voltage to be applied to the gate terminal of the N-type MOSFET 4 is provided. It has a configuration.

定電圧生成回路5Aは、出力電圧Voutが所定の電圧であるときのN型MOSFET4のゲート−ソース間電圧Vgsが、N型MOSFET4のしきい値電圧Vthより小さくなる(Vgs<Vth)ような定電圧を発生する。したがって、出力電圧Voutが所定の電圧である通常動作時には、N型MOSFET4はオフしている。   The constant voltage generation circuit 5A is configured such that the gate-source voltage Vgs of the N-type MOSFET 4 when the output voltage Vout is a predetermined voltage is smaller than the threshold voltage Vth of the N-type MOSFET 4 (Vgs <Vth). Generate voltage. Therefore, the N-type MOSFET 4 is off during normal operation when the output voltage Vout is a predetermined voltage.

このように通常はN型MOSFET4がオフしているため、本実施例の電源レギュレータ回路も、従来の電源レギュレータ回路と同様、Vout=Vref×(1+R1/R2)で決定される出力電圧Voutを出力する。   As described above, since the N-type MOSFET 4 is normally off, the power supply regulator circuit of this embodiment also outputs the output voltage Vout determined by Vout = Vref × (1 + R1 / R2), similarly to the conventional power supply regulator circuit. To do.

出力端子20に接続される負荷を流れる負荷電流が急激に増加すると、出力電圧Voutが低下し、出力電圧Voutを抵抗R1および抵抗R2で分圧した帰還電圧Vfbも低下する。そのため、比較器3は、P型MOSFET1を流れる電流が増加するようP型MOSFET1のゲート電圧を下げようとする。しかし、抵抗R1および抵抗R2による帰還時間が大きいため、P型MOSFET1を流れる電流の増加の割合は小さい。   When the load current flowing through the load connected to the output terminal 20 suddenly increases, the output voltage Vout decreases, and the feedback voltage Vfb obtained by dividing the output voltage Vout by the resistors R1 and R2 also decreases. Therefore, the comparator 3 tries to lower the gate voltage of the P-type MOSFET 1 so that the current flowing through the P-type MOSFET 1 increases. However, since the feedback time by the resistors R1 and R2 is long, the rate of increase in the current flowing through the P-type MOSFET 1 is small.

一方、出力電圧Voutが低下して、N型MOSFET4のゲート−ソース間電圧Vgsが、N型MOSFET4のしきい値電圧Vth以上(Vgs≧Vth)になると、N型MOSFET4がオンし、負荷電流を供給するようになる。このとき、N型MOSFET4には常に一定のゲート電圧が印加されているため、N型MOSFET4は急速に導通し、負荷電流を急速に供給する。   On the other hand, when the output voltage Vout decreases and the gate-source voltage Vgs of the N-type MOSFET 4 becomes equal to or higher than the threshold voltage Vth of the N-type MOSFET 4 (Vgs ≧ Vth), the N-type MOSFET 4 is turned on and the load current is reduced. Come to supply. At this time, since a constant gate voltage is always applied to the N-type MOSFET 4, the N-type MOSFET 4 conducts rapidly and supplies a load current rapidly.

このようなN型MOSFET4による高速な電流補強により、出力電圧Voutの大幅な電圧低下を抑えることができる。   Such a high-speed current reinforcement by the N-type MOSFET 4 can suppress a significant voltage drop of the output voltage Vout.

図2に、負荷電流が急激の増加した場合の本実施例の出力電圧Voutと、比較例としてN型MOSFET4を有さない従来の電源レギュレータ回路の出力電圧Voutのシミュレーションによる波形を示す。   FIG. 2 shows waveforms obtained by simulating the output voltage Vout of this embodiment when the load current increases rapidly and the output voltage Vout of a conventional power supply regulator circuit that does not have the N-type MOSFET 4 as a comparative example.

図2に示すように、N型MOSFET4を有さない従来の電源レギュレータ回路の場合、負荷電流が急激に増加すると、出力電圧Voutは大きく低下し、また、元の電圧に回復するまでの時間が長い。それに対して、本実施例の電源レギュレータ回路の場合、負荷電流が急激に増加すると、N型MOSFET4がオンするまでの間は出力電圧Voutが低下するが、N型MOSFET4がオンすると、出力電圧Voutは急速に回復する。   As shown in FIG. 2, in the case of a conventional power supply regulator circuit that does not have the N-type MOSFET 4, when the load current increases rapidly, the output voltage Vout greatly decreases and the time until the original voltage is restored long. On the other hand, in the power supply regulator circuit of this embodiment, when the load current increases rapidly, the output voltage Vout decreases until the N-type MOSFET 4 is turned on, but when the N-type MOSFET 4 is turned on, the output voltage Vout Recovers rapidly.

したがって、従来の電源レギュレータ回路に比べて、本実施例の電源レギュレータ回路の出力電圧Voutの変動は小さく抑えられる。   Therefore, the fluctuation of the output voltage Vout of the power supply regulator circuit of the present embodiment can be suppressed as compared with the conventional power supply regulator circuit.

このような本実施例によれば、電源レギュレータ回路の負荷電流が急激に増加して、電源レギュレータ回路の出力電圧が下がると、P型MOSFETに並列に接続したN型MOSFETが速やかに導通して負荷電流を供給するので、電源レギュレータ回路の出力電圧の変動を小さくすることができる。   According to this embodiment, when the load current of the power supply regulator circuit increases rapidly and the output voltage of the power supply regulator circuit decreases, the N-type MOSFET connected in parallel to the P-type MOSFET quickly conducts. Since the load current is supplied, fluctuations in the output voltage of the power regulator circuit can be reduced.

図3は、本発明の実施例2に係る電源レギュレータ回路の構成の例を示す回路図である。   FIG. 3 is a circuit diagram showing an example of the configuration of the power regulator circuit according to the second embodiment of the present invention.

本実施例の電源レギュレータ回路が実施例1の電源レギュレータ回路と異なる点は、定電圧生成回路5Bが基準電圧生成回路2に接続されていることである。   The power regulator circuit of this embodiment is different from the power regulator circuit of the first embodiment in that the constant voltage generation circuit 5B is connected to the reference voltage generation circuit 2.

その他の回路構成は実施例1と同じであり、その動作も実施例1と同じである。そこで、図3において、図1に示す回路要素と同じ回路要素には図1と同じ符号を付し、ここではその詳細な説明を省略する。   Other circuit configurations are the same as those in the first embodiment, and their operations are also the same as those in the first embodiment. Therefore, in FIG. 3, the same circuit elements as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

本実施例の定電圧生成回路5Bは基準電圧生成回路2に接続されており、N型MOSFET4のゲート端子へ入力する定電圧を基準電圧生成回路2の出力である基準電圧Vrefから生成する。この基準電圧Vrefは、入力電源端子10へ入力される入力電源に電圧変動があっても一定電圧を出力するよう基準電圧生成回路2により制御されている。したがって、定電圧生成回路5Bへ入力される基準電圧Vrefは安定している。   The constant voltage generation circuit 5B of this embodiment is connected to the reference voltage generation circuit 2 and generates a constant voltage input to the gate terminal of the N-type MOSFET 4 from the reference voltage Vref that is the output of the reference voltage generation circuit 2. The reference voltage Vref is controlled by the reference voltage generation circuit 2 so as to output a constant voltage even when the input power supply input to the input power supply terminal 10 has a voltage fluctuation. Therefore, the reference voltage Vref input to the constant voltage generation circuit 5B is stable.

一方、実施例1の定電圧生成回路5Aは入力電源端子10に接続されて、入力電源電圧からN型MOSFET4のゲート端子へ入力する定電圧を生成している。そのため、定電圧生成回路5Bへ入力される入力電源電圧は変動する。したがって、実施例1の定電圧生成回路5Aには、基準電圧生成回路2と同様、入力電源の電圧変動を抑制する制御が必要となる。   On the other hand, the constant voltage generation circuit 5A according to the first embodiment is connected to the input power supply terminal 10 and generates a constant voltage input from the input power supply voltage to the gate terminal of the N-type MOSFET 4. Therefore, the input power supply voltage input to the constant voltage generation circuit 5B varies. Therefore, like the reference voltage generation circuit 2, the constant voltage generation circuit 5A according to the first embodiment needs to be controlled to suppress voltage fluctuations of the input power supply.

これに対して、本実施例の定電圧生成回路5Bでは、電圧レベルが安定している基準電圧VrefからN型MOSFET4のゲート端子へ入力する定電圧を生成するため、実施例1の定電圧生成回路5Aと異なり、入力電源の電圧変動を抑制する制御が不要となる。そのため、本実施例の定電圧生成回路5Bは、実施例1の定電圧生成回路5Aに比べて、回路を簡素化することができる。   On the other hand, the constant voltage generation circuit 5B according to the present embodiment generates a constant voltage that is input to the gate terminal of the N-type MOSFET 4 from the reference voltage Vref having a stable voltage level. Unlike the circuit 5A, the control for suppressing the voltage fluctuation of the input power supply becomes unnecessary. Therefore, the constant voltage generation circuit 5B according to the present embodiment can be simplified in comparison with the constant voltage generation circuit 5A according to the first embodiment.

このような本実施例によれば、N型MOSFETのゲート端子へ入力する電圧を電圧レベルが安定している基準電圧Vrefから生成するため、N型MOSFETのゲート端子へ入力する電圧を定電圧に制御する回路を簡単に構成することができる。   According to the present embodiment, the voltage input to the gate terminal of the N-type MOSFET is generated from the reference voltage Vref whose voltage level is stable, so that the voltage input to the gate terminal of the N-type MOSFET is a constant voltage. The circuit to be controlled can be configured easily.

図4は、本発明の実施例3に係る電源レギュレータ回路の構成の例を示す回路図である。   FIG. 4 is a circuit diagram showing an example of the configuration of the power supply regulator circuit according to the third embodiment of the present invention.

本実施例の電源レギュレータ回路が実施例1の電源レギュレータ回路と異なる点は、N型MOSFET4のゲート端子へ入力する電圧を定電圧生成回路5Aから入力するのではなく、ゲート電圧入力端子40から入力する点である。   The power regulator circuit of this embodiment is different from the power regulator circuit of the first embodiment in that the voltage input to the gate terminal of the N-type MOSFET 4 is not input from the constant voltage generation circuit 5A but input from the gate voltage input terminal 40. It is a point to do.

その他の回路構成は実施例1と同じであり、その動作も実施例1と同じである。そこで、図4において、図1に示す回路要素と同じ回路要素には図1と同じ符号を付し、ここではその詳細な説明を省略する。   Other circuit configurations are the same as those in the first embodiment, and their operations are also the same as those in the first embodiment. Therefore, in FIG. 4, the same circuit elements as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

本実施例のゲート電圧入力端子40は、電源レギュレータ回路の外部からN型MOSFET4のゲート端子へ、出力電圧Voutが所定の電圧であるときのN型MOSFET4のゲート−ソース間電圧Vgsが、N型MOSFET4のしきい値電圧Vthより小さくなる(Vgs<Vth)ような電圧を入力する端子である。   The gate voltage input terminal 40 of this embodiment is such that the gate-source voltage Vgs of the N-type MOSFET 4 when the output voltage Vout is a predetermined voltage from the outside of the power supply regulator circuit to the gate terminal of the N-type MOSFET 4 is N-type. This is a terminal for inputting a voltage lower than the threshold voltage Vth of the MOSFET 4 (Vgs <Vth).

実施例1の定電圧生成回路5Aあるいは実施例2の定電圧生成回路5Bは、電源レギュレータ回路の内部に予め作られているため、その出力電圧は固定である。したがって、N型MOSFET4を流れる電流量も固定されている。   Since the constant voltage generation circuit 5A of the first embodiment or the constant voltage generation circuit 5B of the second embodiment is made in advance in the power supply regulator circuit, its output voltage is fixed. Therefore, the amount of current flowing through the N-type MOSFET 4 is also fixed.

これに対して、本実施例では、N型MOSFET4のゲート端子へ入力する電圧をゲート電圧入力端子40により変更することができる。これにより、出力端子40に接続される負荷に流れる電流の大きさに応じて、N型MOSFET4に流す電流量を自由に制御することができる。   On the other hand, in this embodiment, the voltage input to the gate terminal of the N-type MOSFET 4 can be changed by the gate voltage input terminal 40. Thereby, according to the magnitude | size of the electric current which flows into the load connected to the output terminal 40, the electric current amount which flows into N type MOSFET4 can be controlled freely.

このような本実施例によれば、N型MOSFETのゲート端子へ入力する電圧を電源レギュレータの外部から制御することができるので、N型MOSFETに流す電流量の制御の自由度を広げることができる。   According to this embodiment, since the voltage input to the gate terminal of the N-type MOSFET can be controlled from the outside of the power supply regulator, the degree of freedom in controlling the amount of current flowing through the N-type MOSFET can be expanded. .

本発明の実施例1に係る電源レギュレータ回路の構成の例を示す回路図。1 is a circuit diagram showing an example of a configuration of a power supply regulator circuit according to Embodiment 1 of the present invention. 本発明の実施例1に係る電源レギュレータ回路の動作の例を示すシミュレーション波形図。FIG. 4 is a simulation waveform diagram showing an example of the operation of the power regulator circuit according to the first embodiment of the present invention. 本発明の実施例2に係る電源レギュレータ回路の構成の例を示す回路図。The circuit diagram which shows the example of a structure of the power supply regulator circuit which concerns on Example 2 of this invention. 本発明の実施例3に係る電源レギュレータ回路の構成の例を示す回路図。FIG. 6 is a circuit diagram illustrating an example of a configuration of a power regulator circuit according to a third embodiment of the present invention.

符号の説明Explanation of symbols

1 P型MOSFET
2 基準電圧生成回路
3 比較器
4 N型MOSFET
5A、5B 定電圧生成回路
10 入力電源端子
20 出力端子
30 接地端子
40 ゲート電圧入力端子
R1、R2 抵抗
1 P-type MOSFET
2 Reference voltage generation circuit 3 Comparator 4 N-type MOSFET
5A, 5B Constant voltage generation circuit 10 Input power supply terminal 20 Output terminal 30 Ground terminal 40 Gate voltage input terminals R1, R2 Resistance

Claims (5)

入力電源端子にソース端子が接続され、出力端子にドレイン端子が接続されるP型MOSFETと、
前記出力端子と接地端子との間に接続される第1および第2の抵抗と、
前記出力端子の出力電圧を前記第1および第2の抵抗で分圧した帰還電圧と基準電圧とを比較し、前記帰還電圧が前記基準電圧と一致するよう前記P型MOSFETのゲート端子へ入力する電圧を変化させる比較器と
を備え、
前記P型MOSFETに並列に接続され、前記出力電圧が所定の電圧のときはオフしていて、前記出力電圧が低下したときにオンするN型MOSFETを有すること
を特徴とする電源レギュレータ回路。
A P-type MOSFET having a source terminal connected to the input power supply terminal and a drain terminal connected to the output terminal;
First and second resistors connected between the output terminal and a ground terminal;
A feedback voltage obtained by dividing the output voltage of the output terminal by the first and second resistors is compared with a reference voltage, and input to the gate terminal of the P-type MOSFET so that the feedback voltage matches the reference voltage. A comparator for changing the voltage,
A power supply regulator circuit comprising an N-type MOSFET connected in parallel to the P-type MOSFET and turned off when the output voltage is a predetermined voltage and turned on when the output voltage drops.
前記N型MOSFETのしきい値電圧より低い一定電圧を生成して前記N型MOSFETのゲート端子へ入力する定電圧生成生回路を有することを特徴とする請求項1に記載の電源レギュレータ回路。   2. The power supply regulator circuit according to claim 1, further comprising a constant voltage generation circuit that generates a constant voltage lower than a threshold voltage of the N-type MOSFET and inputs the constant voltage to a gate terminal of the N-type MOSFET. 前記定電圧生成回路は、前記入力電圧端子へ接続されることを特徴とする請求項2に記載の電源レギュレータ回路。   The power supply regulator circuit according to claim 2, wherein the constant voltage generation circuit is connected to the input voltage terminal. 前記定電圧生成回路は、前記基準電圧が入力されることを特徴とする請求項2に記載の電源レギュレータ回路。   The power supply regulator circuit according to claim 2, wherein the reference voltage is input to the constant voltage generation circuit. 前記N型MOSFETのゲート端子へ前記N型MOSFETのしきい値電圧より低い一定電圧を入力する端子を有することを特徴とする請求項1に記載の電源レギュレータ回路。   2. The power supply regulator circuit according to claim 1, further comprising a terminal for inputting a constant voltage lower than a threshold voltage of the N-type MOSFET to the gate terminal of the N-type MOSFET.
JP2005194884A 2005-07-04 2005-07-04 Power source regulator circuit Withdrawn JP2007011947A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021317A (en) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 Drive circuit and display screen
US9059703B2 (en) 2013-08-29 2015-06-16 Kabushiki Kaisha Toshiba Switch circuit
CN105404341A (en) * 2014-09-12 2016-03-16 南车株洲电力机车研究所有限公司 Device and system for power output voltage sampling feedback
JP2016143394A (en) * 2015-02-05 2016-08-08 ローム株式会社 Linear power supply and electronic device using the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021317A (en) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 Drive circuit and display screen
US9059703B2 (en) 2013-08-29 2015-06-16 Kabushiki Kaisha Toshiba Switch circuit
CN105404341A (en) * 2014-09-12 2016-03-16 南车株洲电力机车研究所有限公司 Device and system for power output voltage sampling feedback
JP2016143394A (en) * 2015-02-05 2016-08-08 ローム株式会社 Linear power supply and electronic device using the same
WO2016125412A1 (en) * 2015-02-05 2016-08-11 ローム株式会社 Linear power supply and electronic apparatus using same
US10168720B2 (en) 2015-02-05 2019-01-01 Rohm Co., Ltd. Linear power supply and electronic apparatus using same
KR102057379B1 (en) 2015-02-05 2019-12-18 로무 가부시키가이샤 Linear power supplies and electronic devices using them

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