JP2007010813A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of carrying out a COG implementation on a display panel of a large and ultrahigh-definition display at low cost. <P>SOLUTION: The display device is provided with a part A where the implementation intervals of a plurality of data line driving circuit chips D1-D15 are small and a part B where the implementation intervals are large, and comprises first and second flexible printed boards DFPC1 and DFPC2 for sequentially supplying each of the two systems of the driving signals ch1 and ch2 from data line driving circuit chips D1 and D8 at each end of the data line driving circuit chip arrays in each of the roughly half area of the display region AR, to next data line driving circuit chips in each of the roughly half area of the display region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly, to a chip-on-glass display device having a high-frequency drive signal supply structure that supports ultra-high definition display.

  Various display devices such as liquid crystal display devices and organic EL (OLED) display devices exist. For example, in an active matrix type liquid crystal display device, improvement of the definition of the display is one of technical development issues. In active matrix liquid crystal display devices, thin film transistors are widely used as active elements. A chip-on-glass in which a plurality of driving circuit chips for supplying required driving signals to data lines (drain lines) and scanning lines (gate lines) are directly mounted around one substrate (also referred to as a thin film transistor substrate) on which the thin film transistors are arranged. A method (hereinafter, COG mounting method) is known.

  The COG method employs an inter-chip transfer method that transfers scanning signals and data signals between a plurality of mounted drive circuit chips. Necessary signals and the like are supplied from the display control circuit board to an external flexible printed circuit board (hereinafter referred to as FPC) to the plurality of drive circuit chips mounted with COG.

  Here, the data line driving circuit chip will be further described. A display control board called a TCON board in the first data line driving circuit chip (usually the data line driving circuit chip adjacent to the scanning line driving circuit chip mounting side) of the plurality of data line driving circuit chips mounted around the substrate Various clock signals (frame start signal, scanning timing signal, pixel clock signal, etc.), display data, and display control signal are supplied. Display data is sequentially transferred from the first data line driving circuit chip to the next data line driving circuit. The power is supplied to each chip in parallel.

  In such an inter-chip transfer method, the above-described various drive signals are supplied using one FPC from the power supply end (the part adjacent to the scanning line drive circuit chip mounting side) to the farthest end.

Patent Documents 1 and 2 can be cited as disclosures of prior art relating to the supply of drive signals and the like in this type of liquid crystal display device.
JP 2004-4924 A JP 2004-118089 A

  FIG. 12 is a schematic plan view for explaining one substrate of a liquid crystal panel constituting a COG type liquid crystal display device. The liquid crystal panel PNL is manufactured by sealing liquid crystal in a bonding gap between a thin film transistor substrate which is one substrate and a color filter substrate which is the other substrate (not shown). A plurality of scanning line driving circuits (hereinafter also referred to as gate driving circuits or gate drivers) are mounted on one of the short sides of the thin film transistor substrate, and scanning signals are supplied from a TCON substrate (not shown) by an FPC (gate FPC) GFPC.

  A plurality of data line driving circuits (hereinafter also referred to as drain driving circuits or drain drivers) are mounted on one of the long sides of the thin film transistor substrate, and a clock signal and a data signal are received from a TCON substrate (not shown) by an FPC (drain FPC) DFPC. A control signal is supplied.

  In order to perform a higher definition display with a liquid crystal display device using an interchip data transfer method, the number of data line driving circuit chips mounted on the substrate may be increased. However, increasing the number inevitably increases the operating frequency. For example, in a large-sized liquid crystal display device for ultra-high definition television called WSXGA, even if the number of data line driving circuit chips is increased from 14 to 15, one DFPC exceeds the transfer capability of the data line driving circuit chip. End up.

  FIG. 13 is an explanatory diagram of material removal of the drain FPC as shown in FIG. The drain FPC forms necessary wiring on the original substrate sheet FPC-M of the flexible substrate, and cuts out a plurality of flexible printed substrates DFPC for drain. However, there are many parts that are wasted in removing the DFPC having such a shape.

  FIG. 14, FIG. 15 and FIG. 16 are explanatory views of the installation state of the flexible printed circuit board for drain in the large size liquid crystal panel. FIG. 14 is a diagram using one DFPC that supplies a signal from one end, FIG. 15 is a diagram using a single DFPC that transfers signals from the center in the opposite direction to the left and right, and FIG. The drive signals are transferred in the left and right direction opposite to each other using DFPC.

  14 and 15, the overall length of the DFPC is too long, and it is difficult to obtain the accuracy of the pattern size and pitch dimension of the DFPC. Increasing the manufacturing hurdles. Furthermore, in FIG. 14, when the drain drivers are cascade-connected, the number of connection stages and the transfer distance between the drivers affect the operation margin, and therefore design is difficult. In the case of FIG. 16, the hurdles in designing and manufacturing are lowered by providing the right and left exclusive DFPC, but the material collecting efficiency described in FIG. 13 is low, and two molds are necessary and the cost is high.

  The present invention solves the above-described problems in the prior art, enables COG mounting on a display panel of a display device such as a large-sized, ultra-high-definition liquid crystal display device, an organic EL (OLED) display device, and the like. An object of the present invention is to provide a display device that realizes cost reduction.

  The present invention is characterized by a drive signal supply structure in a display device having a panel and a display control circuit board. The display panel of the present invention has a pixel array of thin film transistors arranged in a matrix, and is mounted on a plurality of data line driving circuit chips that are directly mounted on at least one side along the one side and arranged in an interchip transfer system. It is comprised from a board | substrate and the other board | substrate bonded together to this one board | substrate.

  The timing controller mounted on the display control circuit board includes first and second two systems corresponding to approximately half of the display area of the display panel based on a display signal input from an external signal source such as a host computer. A drive signal is generated.

  The first means of the present invention provides a narrow portion and a wide portion in the mounting interval of the plurality of data line driving circuit chips, and displays each of the two systems of driving signals in the data line driving circuit chip row. First and second flexible printed circuit boards are sequentially supplied from a data line driving circuit chip located at one end corresponding to each approximately half of the area to the next data line driving circuit chip in each approximately half display area. It is a configuration.

  The drive signals transferred by the inter-chip transfer method are a clock signal, a display data signal, and a display control signal, and power to the data line drive circuit chip is directly supplied from each flexible printed circuit board. The

  The display control circuit board includes an input connector for receiving a display signal input from the external signal source, and first and second output connectors for outputting the first and second drive signals from the timing controller, respectively. With. The first flexible printed circuit board has a terminal portion for connecting the first output connector of the display control circuit board, and the second flexible printed circuit board includes the second flexible printed circuit board provided in the display control circuit board. And a terminal portion connected to the two output connectors.

  And the terminal part of the first flexible printed circuit board is arranged at the end of the one side of the one board, the terminal part of the second flexible printed circuit board is arranged at the center of the one side, and The drive signal transfer direction is the same along the one side.

  According to a second means of the present invention, the data lines located on both sides of the substantially central portion of the one side that divides each of the two systems of drive signals into the respective half of the display area of the data line drive circuit chip row. In this configuration, a flexible printed circuit board is sequentially supplied from the drive circuit chip to the next data line drive circuit chip in the substantially half display area in the opposite directions.

  And the flexible printed circuit board is provided with two strip portions cut out in parallel leaving a connecting portion at one end, and the two strip portions are bent from the connecting portion to the opposite side in the direction perpendicular to the connecting portion of the strip portion. It is characterized by the fact that both ends on the opposite side of the part are in the most distant position and are approximately T-shaped.

  Similarly, in the second means, the driving signals transferred by the inter-chip transfer method are a clock signal, a display data signal, and a display control signal, and the power supply to the data line driving circuit chip is directly from the flexible printed circuit board. It was set as the structure supplied to.

  The display control circuit board in the second means includes an input connector for receiving a display signal input from the external signal source, and an output connector for outputting the first and second drive signals from the timing controller. ing. And the terminal part connected to the said output connector with which the said display control circuit board is provided in the said center part of the said flexible printed circuit board was provided.

  Note that approximately half of the above includes one third or one fifth of the display area. Of course, when the drain driver is an even number, including a positive half is also included. The present invention is not limited to the above-described configuration and the configurations disclosed in the claims or the embodiments described below, and various modifications can be made without departing from the technical idea of the present invention. Needless to say.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below in detail with reference to the drawings of the examples.

  The present invention can be applied to general display devices such as a liquid crystal display device and an organic EL (OLED) display device. Examples of the liquid crystal display device are shown below as typical examples. FIG. 1 is a plan view of a thin film transistor substrate which is one substrate constituting a liquid crystal panel for explaining the first embodiment of the present invention. The liquid crystal panel PNL has a thin film transistor substrate SUB1 in which a large number of pixel circuits composed of thin film transistors are arranged in a matrix on the main surface, and a color filter substrate SUB2, which is usually the other substrate in which a color filter group is formed on the main surface. The liquid crystal (not shown) is sealed between the substrates. The two sides of the thin film transistor substrate SUB1 (the short side on the left side and the long side on the lower side in FIG. 1) protrude from the color filter substrate SUB2, and the drive circuit chip is COG-mounted on the protruding portion.

  In the first embodiment, a gate line driving circuit chip (gate driver) DG is mounted on the left side (short side) of the thin film transistor substrate SUB1, and a data line driving circuit (drain driver) D is mounted on the lower side (long side). Yes. Here, it is assumed that five gate drivers and 15 drain drivers are mounted.

  In the first embodiment, two drain drivers D are arranged from the left to the right along the lower side with a small interval. In FIG. 1, the second and third on the left, the fourth and fifth, the sixth and seventh, the eighth and ninth, the tenth and eleventh, the twelfth and thirteenth, the fourteenth and fifteenth, respectively. The interval is narrowed as a pair. A portion where the interval is narrowed is indicated by A, for example. The pair to be paired is not limited to this.

  With this arrangement, a wider portion (indicated by B) is created between the pair of drain drivers than in the case of equidistant arrangement. In the first embodiment, the display area AR is divided into approximately half and driven by a wide portion formed between the sixth and seventh pairs and the eighth and ninth pairs. That is, the first to seventh drain drivers are connected to the first drain-side flexible printed circuit board DFPC1 to supply the drive signal for the first system ch1. Then, the 8th to 15th drain drivers are connected to the second drain side flexible printed circuit board DFPC2 to supply the drive signal for the second system ch2.

  In such a configuration, the clock signal CLK, the display data signal Data, and the control signal, which are drive signals input from the drain side flexible printed circuit board DFPC1, are sequentially transferred to the first to seventh drain drivers by interchip transfer. Similarly, a clock signal CLK, a display data signal Data, and a control signal, which are drive signals input from the drain side flexible printed circuit board DFPC2, are sequentially transferred to the eighth to fifteenth drain drivers by interchip transfer. The gradation voltage is supplied from the first through the fifteenth through the wiring formed on the substrate from the drain side flexible printed circuit board DFPC1. The power is individually applied from each flexible printed circuit board.

  With the configuration of the first embodiment, it is possible to avoid the occurrence of display failure due to unstable operation due to the increase in operating frequency when a drain driver is added in order to improve definition, and to a display panel with a large size and an ultra high definition display. Therefore, it is possible to provide a liquid crystal display device that enables the COG mounting and realizes cost reduction.

  FIG. 2 is a plan view of a thin film transistor substrate which is one substrate constituting a liquid crystal panel for explaining the second embodiment of the present invention. The liquid crystal panel PNL is also configured by adhering a thin film transistor substrate SUB1 and a color filter substrate SUB2 and enclosing liquid crystal between both substrates. The two sides of the thin film transistor substrate SUB1 (the short side on the left side and the long side on the upper side in FIG. 2) protrude from the color filter substrate SUB2, and the drive circuit chip is COG-mounted on the protruding portion.

  In the second embodiment, a gate line driving circuit chip (gate driver) DG is mounted on the left side (short side) of the thin film transistor substrate SUB1, and a data line driving circuit (drain driver) D is mounted on the upper side (long side). Yes. Here, it is assumed that five gate drivers and 15 drain drivers are mounted.

  In the second embodiment, two drain drivers D are arranged along the upper side from the right to the left with a small interval. In FIG. 1, the 2nd and 3rd, 4th and 5th, 6th and 7th, 8th and 9th, 10th and 11th, 12th and 13th, 14th and 15th, The interval is narrowed as a pair. The pair to be paired is not limited to this.

  With such an arrangement, a wider portion is formed between the pair of drain drivers than in the case of equidistant arrangement. In the second embodiment, the display area AR is divided into approximately half and driven by a wide portion formed between the sixth and seventh pairs and the eighth and ninth pairs. That is, the first to seventh drain drivers are connected to the first drain-side flexible printed circuit board DFPC1 to supply the drive signal for the first system ch1. Then, the 8th to 15th drain drivers are connected to the second drain side flexible printed circuit board DFPC2 to supply the drive signal for the second system ch2.

  In such a configuration, the clock signal CLK, the display data signal Data, and the control signal, which are drive signals input from the drain side flexible printed circuit board DFPC1, are sequentially transferred to the first to seventh drain drivers by interchip transfer. Similarly, a clock signal CLK, a display data signal Data, and a control signal, which are drive signals input from the drain side flexible printed circuit board DFPC2, are sequentially transferred to the eighth to fifteenth drain drivers by interchip transfer. The gradation voltage is supplied from the first through the fifteenth through the wiring formed on the substrate from the drain side flexible printed circuit board DFPC1. The power is individually applied from each flexible printed circuit board.

  The drain side flexible printed circuit boards DFPC1 and DFPC2 are supplied with drive signals, gradation voltages, power supplies, and the like from the display control circuit board PC on which the timing controller TCON is mounted. The display control circuit board PC includes an input connector CT1 for inputting a signal for display from an external signal source such as a host computer, and first and second driving signals supplied to the drain side flexible printed boards DFPC1 and DFPC2, respectively. Output connectors CT2 and CT3 are provided. The timing controller TCON generates a drive signal for the first system ch1 and a drive signal for the second system ch2 based on the input display signal, and allows each drain side flexible signal from the first and second connectors CT2 and CT3. Output to the printed circuit boards DFPC1 and DFPC2.

  With the configuration of the second embodiment, the occurrence of display failure due to unstable operation caused by the increase in operating frequency when a drain driver is added in order to improve the definition is avoided, and a display panel for a large-sized and ultra-high-definition display is achieved. A liquid crystal display device that enables COG mounting and realizes cost reduction can be provided.

  FIG. 3 is a plan view of a thin film transistor substrate which is one substrate constituting a liquid crystal panel for explaining the embodiment 3 of the present invention. In Example 3, one long drain-side flexible printed circuit board DFPC is arranged on the long side of a large-sized liquid crystal panel PNL for television or the like. This drain-side flexible printed circuit board DFPC has a terminal portion connected to the display control circuit board in a substantially central portion, and a drive signal inputted to this terminal portion is transferred between the chips in the left-right reverse direction. Power is applied to each drain driver as in the previous embodiment. The gate-side flexible printed circuit board GFPC is supplied with power and a scanning drive signal independently of the drain side.

  FIG. 4 is a diagram for explaining the formation of the drain side flexible printed circuit board according to the third embodiment of the present invention. FIG. 5 is an explanatory diagram of material removal of the drain side flexible printed circuit board according to the third embodiment. As shown in FIG. 4A, the drain-side flexible printed circuit board DFPC of the liquid crystal panel PNL has two strip portions ST cut out in parallel along the central cutting line CCT, leaving the connecting portion FPC-B at one end. Is bent from the connecting part FPC-B to the opposite side in the perpendicular direction at the mountain fold part BNT, and both ends of the strip part ST opposite to the connecting part FPC-B are farthest positions as shown in FIG. It is made into the approximate T shape in the.

  The drain-side flexible printed circuit board having such a shape can take the material as shown in FIG. That is, a plurality of drain flexible printed boards DFPC are cut from the original board sheet FPC-M on which necessary wirings are formed. Thereby, a long flexible printed circuit board can be easily formed, and less materials are wasted than those described with reference to FIG.

  FIG. 6 is an explanatory diagram of a supply form of drive signals and the like in the liquid crystal panel according to the third embodiment of the present invention. The flexible printed circuit board DFPC for drain is installed along one long side of the thin film transistor substrate SUB1 of the liquid crystal panel PNL, here, the lower long side. This drain flexible printed circuit board DFPC has a terminal at a connecting portion FPC-B at substantially the center thereof, and is connected to the output connector CT of the display control circuit board PC. On the long side, drain drivers D (R1), D (R2), D (R3), and D (R4) from the central terminal portion to the right, and D (L1) and D (L2) to the left. , D (L3), and D (L4) are COG-mounted.

  The drain driver drive signals (data, clock, control signal, gradation voltage) supplied from the display control circuit board PC are sequentially supplied to the left and right drain drivers by interchip transfer. The power is applied in parallel from the drain flexible printed circuit board DFPC. The drive signal for the gate driver supplied from the display control circuit board PC is connected to the wiring on the board through the left strip ST of the flexible printed board DFPC for drain, the gate driver DG1 via the flexible printed board GFPC for gate, It is supplied to DG2 and DG3.

  FIG. 7 is an explanatory diagram of another configuration example of the long flexible printed circuit board. This flexible printed circuit board provides a longer flexible printed circuit board than that described with reference to FIG. FIG. 7A is an explanatory diagram of a cutting line when material is taken from the original substrate sheet FPC-M, and a central cutting line CCT leaving a connecting part FPC-B and two sub-connecting parts FPC-B ′ at one end. The two strip portions ST cut out in parallel along the line are bent from the connecting portion FPC-B to the opposite sides in the perpendicular direction at the mountain fold portion BNT as shown in FIG. 7B. Next, as shown in FIG. 7 (c), the sub-connecting portion FPC-B 'is further bent at the mountain-folded portion BNT' in the direction perpendicular to each other. As a result, a long flexible printed circuit board in which the strip portion ST and the sub strip portion ST 'are straight lines is obtained.

  FIG. 8 is an explanatory diagram of still another configuration example of the long flexible printed circuit board. This example shows a configuration for obtaining a long flexible printed circuit board that requires a wiring pattern space at the center C. That is, the long flexible printed circuit board DFPC shown in FIG. 8B is obtained by making a cut along the cutting line CCT as shown in FIG.

  FIG. 9 is an explanatory diagram of a flexible printed circuit board and a drive signal supply form for explaining a fourth embodiment of the present invention. The flexible printed circuit board DFPC for drain according to the fourth embodiment has a structure similar to that described with reference to FIG. The cut shape at the center is slightly different from that in FIG. The drain flexible printed circuit board DFPC is disposed along one long side of the thin film transistor substrate SUB1 of the liquid crystal panel PNL, here, the upper long side. This drain flexible printed circuit board DFPC has terminal portions at its left end and substantially central portion, and is connected to each of the output connectors CT2 and CT3 of the display control circuit substrate PC. On this long side, 15 drain drivers D1 to D15 are COG mounted from left to right.

  Then, the drive signal of the first system (ch1) is supplied from the terminals connected to the output connector CT2 of the display control circuit board PC to the drain drivers D1 to D8. Then, the drive signal of the second system (ch2) is supplied from the terminal connected to the output connector CT3 to the drain drivers D9 to D15. A gate drive signal is supplied from the terminal connected to the output connector CT2 of the display control circuit board PC to the flexible printed board GFPC for gate.

  FIG. 10 is an enlarged view showing details of a P1 portion in FIG. FIG. 11 is an enlarged view showing details of a P2 portion in FIG. In FIG. 10, the drive signal and gray scale voltage of the first system (ch1) are supplied from the drain flexible printed circuit board DFPC of this portion to the drain driver D1. A gate drive signal is output to the flexible printed circuit board GFPC for gate. The gate drive signal is a clock signal or a control signal.

  In FIG. 11 showing the central portion of the drain flexible printed circuit board DFPC, the drive signal of the second system (ch2) is supplied to the drain driver D9. The gradation voltage is supplied from the drain driver 8 to the drain driver D9 through the wiring on the substrate.

It is a top view of the thin-film transistor substrate which is one board | substrate which comprises the liquid crystal panel for describing Example 1 of this invention. It is a top view of the thin-film transistor substrate which is one board | substrate which comprises the liquid crystal panel for describing Example 2 of this invention. It is a top view of the thin-film transistor substrate which is one board | substrate which comprises the liquid crystal panel for describing Example 3 of this invention. It is a figure explaining shaping | molding of the drain side flexible printed circuit board of Example 3 of this invention. It is explanatory drawing of material removal of the drain side flexible printed circuit board of Example 3 of this invention. It is explanatory drawing of the supply form of the drive signal etc. in the liquid crystal panel of Example 3 of this invention. It is explanatory drawing of the other structural example of a elongate flexible printed circuit board. It is explanatory drawing of the other structural example of a elongate flexible printed circuit board. It is explanatory drawing of the supply form of the flexible printed circuit board which demonstrates Example 4 of this invention, and its drive signal. FIG. 10 is an enlarged view showing details of a P1 portion in FIG. 9. It is an enlarged view which shows the detail of P2 part in FIG. FIG. 6 is a schematic plan view illustrating one substrate of a liquid crystal panel constituting a COG type liquid crystal display device. It is explanatory drawing of material removal of drain FPC as shown in FIG. It is explanatory drawing of the installation state of the flexible printed circuit board for drains in a large sized liquid crystal panel. It is explanatory drawing of the other installation state of the flexible printed circuit board for drains in a large size liquid crystal panel. It is explanatory drawing of the further another installation state of the flexible printed circuit board for drains in a large size liquid crystal panel.

Explanation of symbols

PNL ... liquid crystal panel, SUB1 ... thin film transistor substrate, SUB2 ... color filter substrate, DG ... gate line drive circuit chip (gate driver), D ... drain line drive circuit chip (drain driver), DFPC1, DFPC2 ... flexible printed circuit board for drain, GFPC ... flexible printed circuit board for gate.

Claims (9)

One substrate on which a plurality of data line driving circuit chips are mounted, in which pixels formed by thin film transistors are arranged in a matrix, and are mounted on at least one side along the one side and arranged in an interchip transfer method, and the one substrate A display panel having the other substrate bonded to the substrate;
A display control circuit board having a timing controller that generates and supplies two first and second drive signals corresponding to approximately half of the display area of the display panel based on a display signal input from an external signal source; ,
One end corresponding to each approximately half of the display area of the data line drive circuit chip row, each having a narrow portion and a wide portion in the mounting interval of the plurality of data line drive circuit chips. A display device comprising first and second flexible printed boards that are sequentially supplied from a data line driving circuit chip located at a next to a next data line driving circuit chip in each of the substantially half display areas.   The display device according to claim 1, wherein the drive signal transferred by the inter-chip transfer method is a clock signal, a display data signal, or a display control signal.   The display device according to claim 1, wherein power to the data line driving circuit chip is directly supplied from each of the flexible printed boards. The display control circuit board includes an input connector for receiving a display signal input from the external signal source, and first and second output connectors for outputting the first and second drive signals from the timing controller, respectively. ,
The second flexible printed circuit board has a terminal portion for connecting the first output connector provided in the display control circuit board to the first flexible printed circuit board, and the second output provided in the display control circuit board is provided in the second flexible printed circuit board. The display device according to claim 1, further comprising a terminal portion connected to the connector.   The terminal portion of the first flexible printed circuit board is disposed at an end of the one side of the one substrate, the terminal portion of the second flexible printed circuit board is disposed at a substantially central portion of the one side, and The display device according to claim 4, wherein a transfer direction of the drive signal is the same along the one side. One substrate on which a plurality of data line driving circuit chips are arranged in a matrix arrangement of pixels composed of thin film transistors, and mounted directly on at least one side along the one side and arranged in an interchip transfer method, and the one substrate A display panel having the other substrate bonded to the substrate;
A display control circuit board having a timing controller that generates and supplies two first and second drive signals corresponding to approximately half of the display area of the display panel based on a display signal input from an external signal source; ,
Each of the two systems of driving signals is divided into the respective half of the display area of the data line driving circuit chip row, and each half is displayed from the data line driving circuit chip located on both sides of the substantially central portion of the side. A flexible printed circuit board that sequentially supplies the next data line driving circuit chip in the region in opposite directions,
The flexible printed circuit board has two strip portions cut out in parallel, leaving a connecting portion at one end, and the two strip portions are bent from the connecting portion to the opposite side in the direction perpendicular to the connecting portion of the strip portion. A display device having a substantially T-shape in which both end portions on the opposite side to the farthest position are farthest.   The display device according to claim 6, wherein the drive signal transferred by the inter-chip transfer method is a clock signal, a display data signal, or a display control signal.   The display device according to claim 6, wherein power to the data line driving circuit chip is directly supplied from the flexible printed circuit board. The display control circuit board includes an input connector that receives a display signal input from the external signal source, and an output connector that outputs the first and second drive signals from the timing controller,
The display device according to claim 6, further comprising: a terminal portion connected to the output connector provided in the display control circuit board at the central portion of the flexible printed circuit board.

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