JP2007005773A - Carrier tape - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a carrier tape capable of reducing the electrostatic breakdown of an integrated circuit element caused by the discharge of an electrified charge or the like, and conducting performance test on the integrated circuit element such as conducting input/output inspection of signals by contacting a probe pin with an input terminal or output terminal or the like in the manufacturing process of the tape carrier package. <P>SOLUTION: The carrier 1 includes a tape carrier package 200 disposed on an insulating tape 100, and first and second integrated circuit elements 201, 202 disposed at the tape carrier package 200. In addition, a connection wiring 500 is connected to any one of the terminals of the first integrated circuit element 201, and any one of the terminals of the second integrated circuit element 202. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a carrier tape, a plurality of tape carrier packages (Tape Carrier Package) provided on a long insulating tape at regular intervals, and a plurality of integrated circuit elements mounted on each of the plurality of tape carrier packages; It is related with the carrier tape provided with.

  In recent years, a method of mounting on a tape carrier package has been widely used as a method of mounting an integrated circuit element. At present, since the tape carrier package has flexibility and ability to handle narrow pitches, for example, it is a mainstream of a mounting method of an integrated circuit element that supplies a driving signal of a liquid crystal display (LCD) panel.

  Each of such tape carrier packages is shipped in a single long carrier tape, and is used by being mounted on an automatic mounting apparatus by a user. The automatic mounting apparatus is configured to press the tape carrier package one by one from the carrier tape and to mount the pressed tape carrier package on the liquid crystal display panel.

  In the process of mounting the integrated circuit element on the patterned wiring insulating tape and pressing the tape carrier package from the carrier tape, there is a potential difference between the adjacent integrated circuit elements due to charging due to friction between the members. In some cases, the integrated circuit element may be electrostatically broken due to discharge of the charged electric charge.

Conventionally, in order to reduce the electrostatic breakdown of an integrated circuit element due to discharge of a charged charge, for example, all of a plurality of input terminals formed on each tape carrier package are electrically connected to each other by the same potential wiring. There has been proposed a carrier tape that is short-circuited and in which all of a plurality of output terminals formed on each tape carrier package are electrically short-circuited by the same potential wiring (for example, Patent Document 1).
JP 2003-318232 A (FIG. 1, paragraph 0027)

  However, in the technique described in Patent Document 1, since all of the plurality of input terminals and output terminals are all short-circuited to the same potential wiring, until the tape carrier package is pressed from the carrier tape, for example, the input terminal Alternatively, the performance test of the integrated circuit element such as the input / output inspection of the signal by applying the probe pin to the output terminal could not be performed.

  A carrier tape according to the present invention is provided on an insulating tape, and includes at least one or more tape carrier packages, first and second integrated circuit elements provided in the tape carrier package, and first and second integrated circuits. A plurality of terminals provided in each of the elements, wherein the first terminal of the first integrated circuit element and the first terminal of the second integrated circuit element are electrically connected, and the first integrated circuit The second terminal of the circuit element and the second terminal of the second integrated circuit element are not electrically connected.

  With such a configuration, in the course of the tape carrier package manufacturing process, electrostatic breakdown of the integrated circuit element due to discharge of charged electric charges and the like is reduced, and a probe pin is applied between the terminals to input and output signals. An integrated circuit element performance test such as inspection can be performed.

  According to the present invention, it is possible to reduce the electrostatic breakdown of the integrated circuit element in the process of manufacturing the tape carrier package and to perform the performance test of the integrated circuit element.

Embodiment 1 of the Invention
The configuration of the carrier tape according to Embodiment 1 of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view showing a configuration of a carrier tape according to Embodiment 1 of the present invention.
As shown in FIG. 1, the carrier tape 1 is configured by providing a plurality of tape carrier packages 200 on a long insulating tape 100 at regular intervals.

As shown in FIG. 1, a plurality of sprocket holes 101 are formed at both ends of the insulating tape 100 at regular intervals along the extending direction of the insulating tape 100. The insulating tape 100 is made of a flexible material such as polyimide.
The plurality of sprocket holes 101 are used, for example, to intermittently feed the carrier tape 100 when the tape carrier package 200 is pressed one by one from the carrier tape 1.

  As shown in FIG. 1, a first integrated circuit element 201 and a second integrated circuit element 202 are mounted on each tape carrier package 200. The first and second integrated circuit elements 201 and 202 are mounted on each of the tape carrier packages 200 by, for example, a TAB method (Tape Automated Bonding). In FIG. 1, for the sake of convenience, the number of integrated circuit elements is two, but may be three or more.

  As shown in FIG. 1, the tape carrier package 200 is formed with a plurality of input terminals 203 and a plurality of output terminals 204 arranged in parallel at regular intervals. In FIG. 1, the plurality of input terminals 203 and the plurality of output terminals 204 are arranged at regular intervals along the extending direction of the insulating tape 100, but are arranged along the direction perpendicular to the extending direction of the insulating tape 100. May be.

As shown in FIG. 1, the first and second semiconductor elements 201 and 202 are formed in a rectangular parallelepiped shape, and input pins and output pins are provided on both sides of the rectangular parallelepiped along the long side.
Further, as shown in FIG. 1, the input pins of the first and second semiconductor elements 201 and 202 are arranged on the plurality of input terminals 203 side, and the first and second terminals are arranged on the plurality of output terminals 204 side. The output pins of the second semiconductor elements 201 and 202 are arranged. Each input pin is connected to each input terminal 203, and each output pin is connected to each output terminal 204.

  As shown in FIG. 1, the tape carrier package 200 includes a wiring 205 that electrically connects the first and second integrated circuit elements 201 and 202 and the plurality of input terminals 203, and an integrated circuit element. 201 and 202 and the wiring 206 which electrically connects between the some output terminal 204 are formed.

The plurality of input terminals 203, the plurality of output terminals 204, and the wirings 205 and 206 are formed by patterning on the insulating tape 100 using a conductive member such as copper foil or gold foil.
The integrated circuit elements 201 and 202 and the wirings 205 and 206 are covered with an insulating film (not shown). The input terminal 202 and the output terminal 203 are not covered with an insulating film (not shown), and the conductive member forming the input terminal 202 and the output terminal 203 is exposed.

Here, generally, the plurality of output terminals 204 are connected to drains or sources of relatively large MOS transistors (not shown) in the first and second integrated circuit elements 201 and 202. The drain or source of this MOS transistor is connected to the p diffusion region on the n well on the substrate. Since the transistor has a high withstand voltage against static electricity due to the junction capacitance at pn, generally, countermeasures against electrostatic breakdown are taken for the output terminal.
In general, since an input protection circuit or the like is also provided for the plurality of input terminals 203, generally, countermeasures against electrostatic breakdown are also taken for the input terminals.

  However, as shown in FIG. 1, when the first and second semiconductor elements 201 and 202 are adjacent to each other, one semiconductor element (for example, 201) is + 1000V, and the other semiconductor element (for example, 202) is -1000V. May be charged. When the tape carrier package 200 is pressed out in such a state, a die press blade is electrically connected between the adjacent semiconductor elements 201 and 202 to form a discharge path, and the adjacent semiconductor elements 201, A large current flows between 202.

The discharge at this time is a large discharge that cannot be protected by a general countermeasure against electrostatic breakdown applied to the plurality of output terminals 204 and the plurality of input terminals 203, and the adjacent semiconductor elements 201 and 202 are electrostatically damaged. End up.
Although it is conceivable to provide a protection element for a large current, this increases the mounting area of the semiconductor element and is not a practical measure.

Therefore, as shown in FIG. 1, between any one terminal of the first integrated circuit element 201 and any one terminal of the second integrated circuit element 202 adjacent to the first integrated circuit 201. The connection wiring 500 which electrically short-circuits only was provided. As shown in FIG. 1, the connection wiring 500 is particularly provided on the input terminal 203 side because the power supply voltage and the ground voltage are applied only to the input terminal 203 side. On the other hand, since all the output terminals 204 are generally signal terminals, it is not preferable to provide the connection wiring 500 on the output terminal 203 side as compared to providing the connection terminal 500 on the input terminal 203 side.
When the connection wiring 500 is formed by patterning the plurality of input terminals 203, the plurality of output terminals 204, and the wirings 205 and 206 on the insulating tape 100 using a conductive member such as copper foil or gold foil, Is formed.

By configuring the carrier tape 1 in this way, the first and second integrated circuit elements 201 and 202 are electrically connected by the connection wiring 500, and are connected between the first and second integrated circuit elements 201 and 202. The potential is always the same.
Therefore, it is possible to reduce electrostatic breakdown of the integrated circuit elements 201 and 202 due to discharge of charged electric charges or the like in the process of manufacturing the tape carrier package.

Further, all of the plurality of input terminals 203 and output terminals 204 are not short-circuited.
Therefore, it is possible to perform a performance test of the integrated circuit element such as a signal input / output test by applying a probe pin to the input terminal 203 or the output terminal 204. That is, even if the input terminals 203 are short-circuited, the test signal can be input.
Therefore, by using the carrier tape 1 according to the first embodiment of the present invention, the integrated circuit elements 201 and 202 are prevented from electrostatic breakdown due to discharge of charged charges or the like in the process of manufacturing the tape carrier package. In addition to the reduction, it is possible to perform a performance test of the integrated circuit element such as performing input / output inspection of signals by applying probe pins to the input terminal 203 and the output terminal 204.

Preferably, any one terminal of the first integrated circuit element 201 and any one terminal of the second integrated circuit element 202 adjacent to the first integrated circuit 201 are respectively a power supply terminal or a ground potential. The ground terminal connected to.
In this case, the potential between the first and second integrated circuit elements 201 and 202 can always be the same potential more stably.
Note that the terminals of the first and second integrated circuit elements 201 and 202 connected by the connection wiring 500 may be selected in accordance with the content of the performance test of the integrated circuit elements 201 and 202.

When three or more integrated circuit elements are mounted on each of the tape carrier packages 200, any one terminal of each integrated circuit element is only between any one terminal of adjacent integrated circuit elements. The connection wiring may be formed so as to be connected at.
As shown in FIG. 1, the connection wiring 500 is provided on the insulating tape 100 and outside the outline 400 of the tape carrier package 200.
Further, as shown in FIG. 1, each of the tape carrier packages 200 is pressed out one by one from the carrier tape 1 along the cutting line 300.

As shown in FIG. 1, the cutting line 300 is provided along the outline 400 of the tape carrier package 200. That is, the cutting line 300 and the outline 400 of the tape carrier package 200 are arranged so as to overlap each other on the plan view of the carrier tape 1.
The tape carrier package 200 is cut from the carrier tape 1 along the cutting line 300 and then connected to another electrical component such as a liquid crystal display panel by connector connection, thermocompression bonding, or the like.

Next, the process of cutting the tape carrier package 200 from the carrier tape 1 will be described with reference to the drawings.
FIG. 2 is a diagram showing a tape path when the tape carrier package is cut and separated from the carrier tape.
As shown in FIG. 2, the carrier tape 1 wound around the unwinding reel 601 that rotates in the direction of the arrow so as to overlap the spacer tape 700 is separated from the spacer tape 700 in a portion A (indicated by a dotted line) and rolled 602A. Then, the tape carrier package 200 is cut and separated by the mold 603 at the B portion (dotted line display) which is a punched portion.

On the other hand, in the take-up reel 604 that rotates in the arrow direction, the carrier tape 1000 after cutting and separating the tape carrier package 200 sent via the roll 602B is sent via the rolls 602C and 602D. The spacer tape 700 is rolled up.
The punched portion of the portion B indicated by a dotted line includes a press die 603 and a press cylinder (not shown). In this punched portion (B portion), the press die 603 is moved up and down by a press cylinder, intermittently fed by a sprocket, and the tape carrier package 200 of the carrier tape 1 positioned by a positioning mechanism is cut along a cutting line 300. To do.

At this time, as shown in FIG. 1, since the connection wiring 500 is provided on the insulating tape 100 and outside the outline 400 of the tape carrier package 200, after the tape carrier package 200 is cut and separated, In the tape carrier package 200, a circuit configuration in which the electrical connection between the first and second integrated circuit elements 201 and 202 is disconnected can be obtained.
The tape carrier package 200 cut and separated is stored in a tray (not shown) provided below the press die 603.

FIG. 3 is a perspective view showing the relationship between the carrier tape and the spacer tape.
As shown in FIG. 3, a spacer tape 700 in which convex portions 701 formed by embossing are arranged on both sides is overlapped with the carrier tape 1 in order to protect the integrated circuit elements 201 and 202 on the carrier tape 1. It is rolled up.

As described above, according to the present invention, only one terminal of the first integrated circuit element 201 and only one terminal of the second integrated circuit element 202 are electrically short-circuited. Thus, the first and second integrated circuit elements 201 and 202 can be kept at the same potential.
Therefore, in the A part where the carrier tape 1 and the spacer tape 700 are peeled when the unwinding reel 601 is unwound as shown in FIG. 2 and the B part where the tape carrier package 200 is cut and separated from the carrier tape 1, The integrated circuit elements 201 and 202 can be prevented from being damaged because they are hardly affected by the generated static electricity.

In addition to this, according to the present invention, electrical connection is made only between any one terminal of the first integrated circuit element 201 and any one terminal of the second integrated circuit element 202. Since they are short-circuited, all of the plurality of input terminals 203 or output terminals 204 are not at the same potential.
Therefore, it is possible to perform a performance test of the integrated circuit element such as a signal input / output test by applying probe pins to the input terminal 203 and the output terminal 204.

  Therefore, by using the carrier tape 1 according to the first embodiment of the present invention, the integrated circuit elements 201 and 202 are prevented from electrostatic breakdown due to discharge of charged charges or the like in the process of manufacturing the tape carrier package. In addition to the reduction, it is possible to perform a performance test of the integrated circuit element such as performing input / output inspection of a signal by applying a probe pin to the input terminal 203 or the output terminal 204.

Next, the connection relationship of the input terminals 203 of the carrier tape 1 according to Embodiment 1 of the present invention will be specifically described. FIG. 4 is a plan view showing the configuration of the carrier tape according to Embodiment 1 of the present invention, particularly for explaining the connection relationship of the input terminals.
As shown in FIG. 4, the input terminal 203 of the carrier tape 1 according to Embodiment 2 of the present invention includes power terminals 203a and 203b, ground terminals 203c and 203d, and signal terminals 203e and 203f. The power terminal 203a, the ground terminal 203c, and the signal terminal 203e are connected to the first integrated circuit element 201, and the power terminal 203b, the ground terminal 203d, and the signal terminal 203f are connected to the second integrated circuit element 202. Yes.

  In general, as shown in FIG. 4, the wiring width connected to the power supply terminals 203a and 203b and the ground terminals 203c and 203d is wider than the wiring width connected to the signal terminals 203e and 203f. Is formed. This is because the power supply terminal and the ground terminal must pass a larger current than the signal terminal.

  Here, the input terminals connected by the connection wiring 500 must be the same type of input terminals. That is, in order to connect the input terminals of the first and second integrated circuit elements 201 and 202 by the connection wiring 500, the power supply terminal 203a and the power supply terminal 203b are connected or the ground terminal 203c and the ground terminal 203d are connected. It is necessary to connect between the signal terminals 203e and 203f. FIG. 4 shows an example in which the power supply terminal 203a and the power supply terminal 203b are connected by the connection wiring 500. The reason for this will be described with reference to FIG.

  FIG. 5 is a diagram illustrating an example of a timing chart of the power supply terminals and the signal terminals. As shown in FIG. 5, the power terminals 203a and 203b are always at a constant level, whereas the signal terminals 203e and 203f are not at a constant level. Therefore, the first and second integrated circuit elements 201 and 202 can be operated even when input terminals having different timing patterns are connected, for example, between the power supply terminal 203a and the signal terminal 203f. In addition, signal input / output inspection cannot be performed. Therefore, as described above, in order to connect the input terminals between the first and second integrated circuit elements 201 and 202 by the connection wiring 500, the power supply terminal 203a and the power supply terminal 203b are connected or the ground terminal 203c is connected. And the ground terminal 203d or the signal terminal 203e and the signal terminal 203f need to be connected.

Embodiment 2 of the Invention
The configuration of the carrier tape according to Embodiment 2 of the present invention will be described with reference to the drawings.
FIG. 6 is a plan view showing the configuration of the carrier tape according to Embodiment 2 of the present invention.
In the carrier tape 1 according to Embodiment 1 of the present invention, the connection wiring 500 is provided on the insulating tape 100 and outside the outline 400 of the tape carrier package 200, whereas FIG. As described above, the carrier tape 1a according to the second embodiment of the present invention is different in that the connection wiring 500a is provided on the insulating tape 100 and inside the outline 400 of the tape carrier package 200. To do.

In the cutting process of the carrier tape 1a according to the second embodiment of the present invention, in the punched portion (B portion) shown in FIG. 2, the press die 603 is moved up and down by the press cylinder and intermittently fed by the sprocket, and the positioning mechanism The tape carrier package 200 of the carrier tape 1 positioned by the step is cut along the cutting line 300.
At this time, as shown in FIG. 6, the connection wiring 500 is provided on the insulating tape 100 and inside the outline 400 of the tape carrier package 200. Therefore, even after the tape carrier package 200 is cut and separated, a circuit configuration in which the first and second integrated circuit elements 201 and 202 are electrically connected in the tape carrier package 200 can be obtained.

  Further, by using the carrier tape 1a according to the second embodiment of the present invention, the same effect as that obtained by using the carrier tape 1 according to the first embodiment of the present invention can be obtained. In other words, in the process of manufacturing the tape carrier package, the integrated circuit elements are prevented from electrostatic breakdown due to discharge of charged electric charges, etc., and the input / output inspection of signals is performed by applying probe pins to the input terminals and output terminals. The performance test of the integrated circuit element such as

Next, the connection relationship of the input terminals 203 of the carrier tape 1a according to Embodiment 2 of the present invention will be specifically described. FIG. 7 is a plan view showing the configuration of the carrier tape according to the second embodiment of the present invention, and is a diagram for explaining the connection relationship of input terminals in particular.
As shown in FIG. 7, the input terminal 203 of the carrier tape 1a according to the second embodiment of the present invention includes power supply terminals 203a and 203b, ground terminals 203c and 203d, and signal terminals 203e and 203f. The power terminal 203a, the ground terminal 203c, and the signal terminal 203e are connected to the first integrated circuit element 201, and the power terminal 203b, the ground terminal 203d, and the signal terminal 203f are connected to the second integrated circuit element 202. Yes.

In general, as shown in FIG. 7, the terminal widths of the power supply terminals 203a and 203b and the ground terminals 203c and 203d are formed to be wider than the terminal widths of the signal terminals 203e and 203f.
Here, the input terminals connected by the connection wiring 500a must be the same type of input terminals. That is, in order to connect the input terminals of the first and second integrated circuit elements 201 and 202 by the connection wiring 500a, the power supply terminals 203a and 203b are connected, or the ground terminals 203c and 203d are connected. It is necessary to connect between the signal terminals 203e and 203f. The reason for this is as described in FIG. Note that FIG. 7 illustrates an example in which the power supply terminal 203a and the power supply terminal 203b are connected by the connection wiring 500a.

The above description is for explaining the embodiment of the present invention, and the present invention is not limited to the above embodiment. Moreover, those skilled in the art can easily change, add, and convert each element of the above embodiment within the scope of the present invention.
In the above embodiment, when only one terminal of the first integrated circuit element 201 and only one terminal of the second integrated circuit element 202 are electrically short-circuited by the connection wirings 500 and 500a. As described above, unless all the input terminals 203 of the first and second integrated circuit elements 201 and 202 are connected, the plurality of terminals of the first integrated circuit element 201 and the plurality of terminals of the second integrated circuit element 202 They may be connected by a plurality of connection wires.

It is a top view which shows the structure of the carrier tape which concerns on Embodiment 1 of this invention. It is a figure which shows the tape path | route in the case of cut-separating a tape carrier package from a carrier tape. It is a perspective view which shows the relationship between a carrier tape and a spacer tape. It is a top view which shows the structure of the carrier tape which concerns on Embodiment 1 of this invention, Comprising: It is a figure for demonstrating the connection relationship of an input terminal especially. It is a figure which shows an example of the timing chart of a power supply terminal and a signal terminal. It is a top view which shows the structure of the carrier tape which concerns on Embodiment 2 of this invention. It is a top view which shows the structure of the carrier tape which concerns on Embodiment 2 of this invention, Comprising: It is a figure for demonstrating the connection relationship of an input terminal especially.

Explanation of symbols

1, 1a Carrier tape 100 Insulating tape 101 Sprocket hole 200 Tape carrier package 201 First integrated circuit element 202 Second integrated circuit element 203 Input terminal 203a, 203b Power terminal 203c, 203d Ground terminal 203e, 203f Signal terminal 204 Output terminal 205, 206 Wiring 300 Cutting line 400 Outline line 500, 500a Connection wiring 601 Unwinding reel 602A, 602B, 602C, 602D Roll 603 Mold 604 Winding reel 700 Spacer tape

Claims (12)

Provided on each of the at least one tape carrier package, the first and second integrated circuit elements provided on the tape carrier package, and the first and second integrated circuit elements provided on the insulating tape. A plurality of terminals,
The first terminal of the first integrated circuit element and the first terminal of the second integrated circuit element are electrically connected, the second terminal of the first integrated circuit element, and the first terminal A carrier tape, wherein the second terminal of the second integrated circuit element is not electrically connected.   The carrier tape according to claim 1, wherein the first terminals of the first and second integrated circuit elements have the same potential.   The carrier tape according to claim 2, wherein the first terminal of the first and second integrated circuit elements is a power supply terminal.   The carrier tape according to claim 2, wherein the first terminals of the first and second integrated circuit elements are terminals connected to a ground potential.   The carrier tape according to claim 2, wherein the first terminals of the first and second integrated circuit elements are terminals having the same function.   The wiring width connected to the first terminal of the first and second integrated circuit elements is larger than the wiring width connected to the second terminal of the first and second integrated circuit elements. 2. The carrier tape according to 2. A connection wiring for electrically connecting the first terminal of the first integrated circuit element and the first terminal of the second integrated circuit element;
A cutting line for cutting and separating the tape carrier package along the outer shape of the tape carrier package is provided,
The carrier tape according to claim 1, wherein the connection wiring is provided on the insulating tape and outside the outer shape of the tape carrier package. A connection wiring for electrically connecting the first terminal of the first integrated circuit element and the first terminal of the second integrated circuit element;
A cutting line for cutting and separating the tape carrier package along the outer shape of the tape carrier package is provided,
The carrier tape according to claim 1, wherein the connection wiring is provided on the insulating tape and inside the outer shape of the tape carrier package.   The carrier tape according to claim 1, wherein the insulating tape is made of polyimide. The tape carrier package is further equipped with a third integrated circuit element,
The carrier tape of claim 1, wherein a first terminal of the third integrated circuit element is coupled to a first terminal of the first and second integrated circuit elements. Provided on each of the at least one tape carrier package, the first and second integrated circuit elements mounted on the tape carrier package, and the first and second integrated circuit elements provided on the insulating tape. Multiple input terminals and output terminals,
At least one input terminal of the input terminals of the first integrated circuit element and at least one input terminal of the second integrated circuit element are electrically connected, and the first integrated circuit element is connected. A carrier tape, wherein an output terminal of the circuit element and an output terminal of the second integrated circuit element are not electrically connected.   A first potential is supplied to the second terminal of the first integrated circuit element, and a second potential different from the first potential is applied to the second terminal of the second integrated circuit element. The carrier tape according to claim 1 being supplied.

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