JP2006502505A5 - - Google Patents

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Publication number
JP2006502505A5
JP2006502505A5 JP2004543542A JP2004543542A JP2006502505A5 JP 2006502505 A5 JP2006502505 A5 JP 2006502505A5 JP 2004543542 A JP2004543542 A JP 2004543542A JP 2004543542 A JP2004543542 A JP 2004543542A JP 2006502505 A5 JP2006502505 A5 JP 2006502505A5
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JP
Japan
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thread
issue
threads
processor
instruction
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Pending
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JP2004543542A
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English (en)
Japanese (ja)
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JP2006502505A (ja
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Priority claimed from US10/269,245 external-priority patent/US6842848B2/en
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Publication of JP2006502505A publication Critical patent/JP2006502505A/ja
Publication of JP2006502505A5 publication Critical patent/JP2006502505A5/ja
Pending legal-status Critical Current

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JP2004543542A 2002-10-11 2003-10-09 トークン・トリガ・マルチスレッディングの方法および装置 Pending JP2006502505A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/269,245 US6842848B2 (en) 2002-10-11 2002-10-11 Method and apparatus for token triggered multithreading
PCT/US2003/031905 WO2004034340A2 (en) 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading

Publications (2)

Publication Number Publication Date
JP2006502505A JP2006502505A (ja) 2006-01-19
JP2006502505A5 true JP2006502505A5 (https=) 2006-11-24

Family

ID=32068734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004543542A Pending JP2006502505A (ja) 2002-10-11 2003-10-09 トークン・トリガ・マルチスレッディングの方法および装置

Country Status (7)

Country Link
US (1) US6842848B2 (https=)
EP (2) EP1550089B1 (https=)
JP (1) JP2006502505A (https=)
KR (1) KR100991912B1 (https=)
CN (1) CN100428282C (https=)
AU (1) AU2003282487A1 (https=)
WO (1) WO2004034340A2 (https=)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1623307B1 (en) * 2003-05-09 2015-07-01 QUALCOMM Incorporated Processor reduction unit for accumulation of multiple operands with or without saturation
US7475222B2 (en) * 2004-04-07 2009-01-06 Sandbridge Technologies, Inc. Multi-threaded processor having compound instruction and operation formats
US8074051B2 (en) 2004-04-07 2011-12-06 Aspen Acquisition Corporation Multithreaded processor with multiple concurrent pipelines per thread
US7797363B2 (en) * 2004-04-07 2010-09-14 Sandbridge Technologies, Inc. Processor having parallel vector multiply and reduce operations with sequential semantics
TW200625097A (en) * 2004-11-17 2006-07-16 Sandbridge Technologies Inc Data file storing multiple date types with controlled data access
US20070223599A1 (en) * 2005-07-25 2007-09-27 Sysair, Inc., A Delaware Corporation Cellular PC modem architecture and method of operation
US20070156928A1 (en) * 2005-12-30 2007-07-05 Makaram Raghunandan Token passing scheme for multithreaded multiprocessor system
US8819099B2 (en) * 2006-09-26 2014-08-26 Qualcomm Incorporated Software implementation of matrix inversion in a wireless communication system
WO2008060948A2 (en) * 2006-11-10 2008-05-22 Sandbridge Technologies, Inc. Method and system for parallelization of pipelined computations
CN101689110B (zh) * 2007-06-20 2013-07-31 富士通株式会社 指令执行控制装置以及指令执行控制方法
US20100241834A1 (en) * 2007-11-05 2010-09-23 Sandbridge Technologies, Inc. Method of encoding using instruction field overloading
JP5576798B2 (ja) * 2007-12-12 2014-08-20 ユニバーシティ・オブ・ワシントン 決定論的マルチプロセッシング（ｄｅｔｅｒｍｉｎｉｓｔｉｃｍｕｌｔｉｐｒｏｃｅｓｓｉｎｇ）
US8539188B2 (en) * 2008-01-30 2013-09-17 Qualcomm Incorporated Method for enabling multi-processor synchronization
EP2245529A1 (en) * 2008-02-18 2010-11-03 Sandbridge Technologies, Inc. Method to accelerate null-terminated string operations
WO2009114691A2 (en) * 2008-03-13 2009-09-17 Sandbridge Technologies, Inc. Method for achieving power savings by disabling a valid array
EP2324430A4 (en) 2008-08-06 2012-07-25 Aspen Acquisition Corp DIRECT MEMORY ACCESS MOTOR (DMA) THAT CAN BE STOPPED AND RESTARTED
CN102495726B (zh) * 2011-11-15 2015-05-20 无锡德思普科技有限公司 机会多线程方法及处理器
US9342314B2 (en) 2011-12-08 2016-05-17 Oracle International Corporation Efficient hardware instructions for single instruction multiple data processors
US9792117B2 (en) 2011-12-08 2017-10-17 Oracle International Corporation Loading values from a value vector into subregisters of a single instruction multiple data register
CN107545066B (zh) * 2011-12-08 2021-01-15 甲骨文国际公司 用于在易失性存储器内保持关系型数据的列向量的技术
US10534606B2 (en) 2011-12-08 2020-01-14 Oracle International Corporation Run-length encoding decompression
US9697174B2 (en) 2011-12-08 2017-07-04 Oracle International Corporation Efficient hardware instructions for processing bit vectors for single instruction multiple data processors
GB2499277B (en) * 2012-08-30 2014-04-02 Imagination Tech Ltd Global register protection in a multi-threaded processor
US9063974B2 (en) 2012-10-02 2015-06-23 Oracle International Corporation Hardware for table scan acceleration
CN103150149B (zh) 2013-03-26 2015-11-25 华为技术有限公司 处理数据库重做数据的方法和装置
US10318305B2 (en) 2013-09-06 2019-06-11 Huawei Technologies Co., Ltd. System and method for an asynchronous processor with pepelined arithmetic and logic unit
US11113054B2 (en) 2013-09-10 2021-09-07 Oracle International Corporation Efficient hardware instructions for single instruction multiple data processors: fast fixed-length value compression
US9378232B2 (en) 2013-09-21 2016-06-28 Oracle International Corporation Framework for numa affinitized parallel query on in-memory objects within the RDBMS
US9766894B2 (en) 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Method and apparatus for enabling a processor to generate pipeline control signals
US9766895B2 (en) * 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Opportunity multithreading in a multithreaded processor with instruction chaining capability
US9558000B2 (en) 2014-02-06 2017-01-31 Optimum Semiconductor Technologies, Inc. Multithreading using an ordered list of hardware contexts
EP3131004A4 (en) 2014-04-11 2017-11-08 Murakumo Corporation Processor and method
US10180841B2 (en) 2014-12-22 2019-01-15 Centipede Semi Ltd. Early termination of segment monitoring in run-time code parallelization
US10296350B2 (en) * 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences
US10296346B2 (en) * 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences based on pre-monitoring
US10073885B2 (en) 2015-05-29 2018-09-11 Oracle International Corporation Optimizer statistics and cost model for in-memory tables
US9990308B2 (en) 2015-08-31 2018-06-05 Oracle International Corporation Selective data compression for in-memory databases
US10061714B2 (en) 2016-03-18 2018-08-28 Oracle International Corporation Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors
US10402425B2 (en) 2016-03-18 2019-09-03 Oracle International Corporation Tuple encoding aware direct memory access engine for scratchpad enabled multi-core processors
US10055358B2 (en) 2016-03-18 2018-08-21 Oracle International Corporation Run length encoding aware direct memory access filtering engine for scratchpad enabled multicore processors
US10061832B2 (en) 2016-11-28 2018-08-28 Oracle International Corporation Database tuple-encoding-aware data partitioning in a direct memory access engine
US10599488B2 (en) 2016-06-29 2020-03-24 Oracle International Corporation Multi-purpose events for notification and sequence control in multi-core processor systems
US10380058B2 (en) 2016-09-06 2019-08-13 Oracle International Corporation Processor core to coprocessor interface with FIFO semantics
US10783102B2 (en) 2016-10-11 2020-09-22 Oracle International Corporation Dynamically configurable high performance database-aware hash engine
US10459859B2 (en) 2016-11-28 2019-10-29 Oracle International Corporation Multicast copy ring for database direct memory access filtering engine
US10176114B2 (en) 2016-11-28 2019-01-08 Oracle International Corporation Row identification number generation in database direct memory access engine
US10725947B2 (en) 2016-11-29 2020-07-28 Oracle International Corporation Bit vector gather row count calculation and handling in direct memory access engine
DE102017223844B4 (de) * 2017-12-28 2026-04-30 Robert Bosch Gmbh Verfahren zum Betreiben eines Riementriebs
WO2023249637A1 (en) * 2022-06-24 2023-12-28 Zeku, Inc. Apparatus and method to implement a token-based processing scheme for virtual dataplane threads

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339415A (en) * 1990-06-11 1994-08-16 Cray Research, Inc. Dual level scheduling of processes to multiple parallel regions of a multi-threaded program on a tightly coupled multiprocessor computer system
US5404469A (en) * 1992-02-25 1995-04-04 Industrial Technology Research Institute Multi-threaded microprocessor architecture utilizing static interleaving
US5613114A (en) * 1994-04-15 1997-03-18 Apple Computer, Inc System and method for custom context switching
US6128720A (en) 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5682491A (en) 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US5649135A (en) 1995-01-17 1997-07-15 International Business Machines Corporation Parallel processing system and method using surrogate instructions
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
US5799182A (en) * 1997-01-21 1998-08-25 Ford Motor Company Multiple thread micro-sequencer apparatus and method with a single processor
US6151683A (en) * 1997-03-31 2000-11-21 Sun Microsystems, Inc. Rebuilding computer states remotely
US6298431B1 (en) * 1997-12-31 2001-10-02 Intel Corporation Banked shadowed register file
US6079010A (en) 1998-03-31 2000-06-20 Lucent Technologies Inc. Multiple machine view execution in a computer system
US6317821B1 (en) 1998-05-18 2001-11-13 Lucent Technologies Inc. Virtual single-cycle execution in pipelined processors
US6260189B1 (en) 1998-09-14 2001-07-10 Lucent Technologies Inc. Compiler-controlled dynamic instruction dispatch in pipelined processors
US6256725B1 (en) 1998-12-04 2001-07-03 Agere Systems Guardian Corp. Shared datapath processor utilizing stack-based and register-based storage spaces
US6341338B1 (en) * 1999-02-04 2002-01-22 Sun Microsystems, Inc. Protocol for coordinating the distribution of shared memory
US6282585B1 (en) 1999-03-22 2001-08-28 Agere Systems Guardian Corp. Cooperative interconnection for reducing port pressure in clustered microprocessors
US6269437B1 (en) 1999-03-22 2001-07-31 Agere Systems Guardian Corp. Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor
US6230251B1 (en) 1999-03-22 2001-05-08 Agere Systems Guardian Corp. File replication methods and apparatus for reducing port pressure in a clustered processor
WO2001046827A1 (en) * 1999-12-22 2001-06-28 Ubicom, Inc. System and method for instruction level multithreading in an embedded processor using zero-time context switching

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