JP2006352090A5 - - Google Patents
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- JP2006352090A5 JP2006352090A5 JP2006131797A JP2006131797A JP2006352090A5 JP 2006352090 A5 JP2006352090 A5 JP 2006352090A5 JP 2006131797 A JP2006131797 A JP 2006131797A JP 2006131797 A JP2006131797 A JP 2006131797A JP 2006352090 A5 JP2006352090 A5 JP 2006352090A5
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- channel transistor
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- electrically connected
- gate
- potential power
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- 239000004065 semiconductor Substances 0.000 claims 12
- 239000000758 substrate Substances 0.000 claims 2
- 239000011521 glass Substances 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
Claims (12)
ゲートが前記ｐチャネル型トランジスタのゲートに電気的に接続され、第１端子が前記ｐチャネル型トランジスタの第２端子に電気的に接続された第１のｎチャネル型トランジスタと、
第１端子が前記第１のｎチャネル型トランジスタの第２端子に電気的に接続され、第２端子が低電位電源に電気的に接続された第２のｎチャネル型トランジスタと、を含む回路群と、
入力端子が前記ｐチャネル型トランジスタの第２端子及び前記第１のｎチャネル型トランジスタの第１端子に電気的に接続されたインバータ回路と、をｍ段（ｍは任意の正の整数であり、ｍ≧３）有し、
第２ｎ−１段目（ｎは任意の整数であり、ｍ≧２ｎ≧２）の前記第２のｎチャネル型トランジスタのゲートにはクロック信号が入力され、
第２ｎ段目の前記第２のｎチャネル型トランジスタのゲートには反転クロック信号が入力されることを特徴とする半導体回路。 A p-channel transistor having a first terminal electrically connected to a high potential power source;
A first n-channel transistor having a gate electrically connected to the gate of the p-channel transistor and a first terminal electrically connected to a second terminal of the p-channel transistor;
The first terminal is electrically connected to the second terminal of the first n-channel transistor, the circuit group including a second n-channel transistor in which the second terminal is electrically connected to the low-potential power supply, a When,
An inverter circuit having an input terminal electrically connected to the second terminal of the p-channel transistor and the first terminal of the first n-channel transistor, and m stages (m is an arbitrary positive integer, m ≧ 3)
A clock signal is input to the gate of the second n-channel transistor in the 2n-1 stage (where n is an arbitrary integer and m ≧ 2n ≧ 2),
A semiconductor circuit, wherein an inverted clock signal is input to a gate of the second n-channel transistor in the second n-th stage.
ゲートが前記ｐチャネル型トランジスタのゲートに電気的に接続され、第１端子が前記ｐチャネル型トランジスタの第２端子に電気的に接続された第１のｎチャネル型トランジスタと、
第１端子が前記第１のｎチャネル型トランジスタの第２端子に電気的に接続され、第２端子が低電位電源に電気的に接続された第２のｎチャネル型トランジスタと、を含む回路群と、
入力端子が前記ｐチャネル型トランジスタの第２端子及び前記第１のｎチャネル型トランジスタの第１端子に電気的に接続されたインバータ回路と、をｍ段（ｍは任意の正の整数であり、ｍ≧３）有し、
第２ｎ−１段目（ｎは任意の整数であり、ｍ≧２ｎ≧２）の前記第２のｎチャネル型トランジスタのゲートにはクロック信号が入力され、
第２ｎ段目の前記第２のｎチャネル型トランジスタのゲートには反転クロック信号が入力され、
前記クロック信号、及び前記反転クロック信号のそれぞれの振幅は、前記高電位電源と前記低電位電源の電位差よりも小さいことを特徴とする半導体回路。 A p-channel transistor having a first terminal electrically connected to a high potential power source;
A first n-channel transistor having a gate electrically connected to the gate of the p-channel transistor and a first terminal electrically connected to a second terminal of the p-channel transistor;
The first terminal is electrically connected to the second terminal of the first n-channel transistor, the circuit group including a second n-channel transistor in which the second terminal is electrically connected to the low-potential power supply, a When,
An inverter circuit having an input terminal electrically connected to the second terminal of the p-channel transistor and the first terminal of the first n-channel transistor, and m stages (m is an arbitrary positive integer, m ≧ 3)
A clock signal is input to the gate of the second n-channel transistor in the 2n-1 stage (where n is an arbitrary integer and m ≧ 2n ≧ 2),
An inverted clock signal is input to the gate of the second n-channel transistor in the second n-th stage,
Said clock signal, and respective amplitudes of said inverted clock signal, a semiconductor circuit wherein the high smaller than the potential difference between the potential source and the low potential power supply.
ゲートが前記第１のｐチャネル型トランジスタのゲートに電気的に接続され、第１端子が前記第１のｐチャネル型トランジスタの第２端子に電気的に接続された第１のｎチャネル型トランジスタと、
第１端子が前記第１のｎチャネル型トランジスタの第２端子に電気的に接続され、第２端子が低電位電源に電気的に接続された第２のｎチャネル型トランジスタと、を含む第１の回路群と、
第１端子が高電位電源に電気的に接続された第２のｐチャネル型トランジスタと、
ゲートが前記第１のｐチャネル型トランジスタの第２端子及び前記第１のｎチャネル型トランジスタの第１端子、並びに前記第２のｐチャネル型トランジスタのゲートに電気的に接続され、第１端子が前記第２のｐチャネル型トランジスタの第２端子に電気的に接続された第３のｎチャネル型トランジスタと、
第１端子が前記第３のｎチャネル型トランジスタの第２端子に電気的に接続され、第２端子が低電位電源に電気的に接続された第４のｎチャネル型トランジスタと、を含む第２の回路群と、をｍ段（ｍは任意の正の整数であり、ｍ≧３）有し、
第２ｎ−１段目（ｎは任意の整数であり、ｍ≧２ｎ≧２）の前記第２のｎチャネル型トランジスタのゲート、及び前記第４のｎチャネル型トランジスタのゲートにはクロック信号が入力され、
第２ｎ段目の前記第２のｎチャネル型トランジスタのゲート、及び前記第４のｎチャネル型トランジスタのゲートには反転クロック信号が入力されることを特徴とする半導体回路。 A first p-channel transistor having a first terminal electrically connected to a high potential power source;
A first n-channel transistor having a gate electrically connected to the gate of the first p-channel transistor and a first terminal electrically connected to a second terminal of the first p-channel transistor; ,
The first terminal is electrically connected to the second terminal of the first n-channel transistor, the first comprising a second n-channel transistor in which the second terminal is electrically connected to the low-potential power supply, a A circuit group of
A second p-channel transistor having a first terminal electrically connected to a high potential power source;
A gate is electrically connected to a second terminal of the first p-channel transistor, a first terminal of the first n-channel transistor, and a gate of the second p-channel transistor, and the first terminal is A third n-channel transistor electrically connected to a second terminal of the second p-channel transistor;
The first terminal is electrically connected to the second terminal of the third n-channel transistor, the second comprising a fourth n-channel transistor in which the second terminal is electrically connected to the low-potential power supply, a And m stages (m is an arbitrary positive integer, m ≧ 3),
A clock signal is input to the gate of the second n-channel transistor and the gate of the fourth n-channel transistor in the 2n-1 stage (n is an arbitrary integer, m ≧ 2n ≧ 2). And
A semiconductor circuit, wherein an inverted clock signal is input to a gate of the second n-channel transistor in the second n-th stage and a gate of the fourth n-channel transistor.
ゲートが前記第１のｐチャネル型トランジスタのゲートに電気的に接続され、第１端子が前記第１のｐチャネル型トランジスタの第２端子に電気的に接続された第１のｎチャネル型トランジスタと、
第１端子が前記第１のｎチャネル型トランジスタの第２端子に電気的に接続され、第２端子が低電位電源に電気的に接続された第２のｎチャネル型トランジスタと、を含む第１の回路群と、
第１端子が高電位電源に電気的に接続された第２のｐチャネル型トランジスタと、
ゲートが前記第１のｐチャネル型トランジスタの第２端子及び前記第１のｎチャネル型トランジスタの第１端子、並びに前記第２のｐチャネル型トランジスタのゲートに電気的に接続され、第１端子が前記第２のｐチャネル型トランジスタの第２端子に電気的に接続された第３のｎチャネル型トランジスタと、
第１端子が前記第３のｎチャネル型トランジスタの第２端子に電気的に接続され、第２端子が低電位電源に電気的に接続された第４のｎチャネル型トランジスタと、を含む第２の回路群と、をｍ段（ｍは任意の正の整数であり、ｍ≧３）有し、
第２ｎ−１段目（ｎは任意の整数であり、ｍ≧２ｎ≧２）の前記第２のｎチャネル型トランジスタのゲート、及び前記第４のｎチャネル型トランジスタのゲートにはクロック信号が入力され、
第２ｎ段目の前記第２のｎチャネル型トランジスタのゲート、及び前記第４のｎチャネル型トランジスタのゲートには反転クロック信号が入力され、
前記クロック信号、及び前記反転クロック信号のそれぞれの振幅は、前記高電位電源と前記低電位電源の電位差よりも小さいことを特徴とする半導体回路。 A first p-channel transistor having a first terminal electrically connected to a high potential power source;
A first n-channel transistor having a gate electrically connected to the gate of the first p-channel transistor and a first terminal electrically connected to a second terminal of the first p-channel transistor; ,
The first terminal is electrically connected to the second terminal of the first n-channel transistor, the first comprising a second n-channel transistor in which the second terminal is electrically connected to the low-potential power supply, a A circuit group of
A second p-channel transistor having a first terminal electrically connected to a high potential power source;
A gate is electrically connected to a second terminal of the first p-channel transistor, a first terminal of the first n-channel transistor, and a gate of the second p-channel transistor, and the first terminal is A third n-channel transistor electrically connected to a second terminal of the second p-channel transistor;
The first terminal is electrically connected to the second terminal of the third n-channel transistor, the second comprising a fourth n-channel transistor in which the second terminal is electrically connected to the low-potential power supply, a And m stages (m is an arbitrary positive integer, m ≧ 3),
A clock signal is input to the gate of the second n-channel transistor and the gate of the fourth n-channel transistor in the 2n-1 stage (n is an arbitrary integer, m ≧ 2n ≧ 2). And
An inverted clock signal is input to the gate of the second n-channel transistor in the second n-th stage and the gate of the fourth n-channel transistor,
Each of the clock signal and the inverted clock signal has a smaller amplitude than a potential difference between the high potential power source and the low potential power source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006131797A JP5057696B2 (en) | 2005-05-20 | 2006-05-10 | Semiconductor circuit and display device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005148814 | 2005-05-20 | ||
| JP2005148814 | 2005-05-20 | ||
| JP2006131797A JP5057696B2 (en) | 2005-05-20 | 2006-05-10 | Semiconductor circuit and display device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012152097A Division JP2012256056A (en) | 2005-05-20 | 2012-07-06 | Display device, display module, and electronic appliance |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006352090A JP2006352090A (en) | 2006-12-28 |
| JP2006352090A5 true JP2006352090A5 (en) | 2009-06-18 |
| JP5057696B2 JP5057696B2 (en) | 2012-10-24 |
Family
ID=37647553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006131797A Active JP5057696B2 (en) | 2005-05-20 | 2006-05-10 | Semiconductor circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5057696B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011052396A1 (en) | 2009-10-29 | 2011-05-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| EP2494594B1 (en) * | 2009-10-29 | 2020-02-19 | Semiconductor Energy Laboratory Co. Ltd. | Semiconductor device |
| SG188112A1 (en) * | 2009-10-30 | 2013-03-28 | Semiconductor Energy Lab | Logic circuit and semiconductor device |
| WO2011077946A1 (en) | 2009-12-25 | 2011-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US8780629B2 (en) | 2010-01-15 | 2014-07-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method thereof |
| JP5947099B2 (en) | 2011-05-20 | 2016-07-06 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001143491A (en) * | 1999-08-31 | 2001-05-25 | Semiconductor Energy Lab Co Ltd | Shift register circuit, drive circuit for display device, and display device using the drive circuit |
| JP2003101394A (en) * | 2001-05-29 | 2003-04-04 | Semiconductor Energy Lab Co Ltd | Pulse output circuit, shift register and display unit |
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2006
- 2006-05-10 JP JP2006131797A patent/JP5057696B2/en active Active
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