JP2006351064A - Current or voltage measurement circuit, sense circuit, and semiconductor non-volatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a measurement circuit which is registant to noise and has a high precision and is suitable for measuring a voltage difference, in a semiconductor chip, and to provide a sense circuit capable of sensing with a high sensitivity regardless of an increase in size of an array in a semiconductor non-volatile memory or the like having, for example, a VGA configuration. <P>SOLUTION: As regards pair wiring 120 comprising a first signal line 120a and a second signal line 120b, the first signal line 120a and the second signal line 120b are laid out so that their floating capacities are approximately equalized. Two output terminals of a measurement object terminal 1000 and input terminals of a differential amplifier 110 are connected by the pair wiring 120. Thus noise included in the first signal line 120a and that in the second signal line 120b become the in-phase noises and are canceled by differential amplification of the differential amplifier 110. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a voltage measuring circuit for measuring a voltage between two terminals of a device under test, a current measuring circuit for measuring a current flowing into and out of the two terminals of the device under test, and reading information stored in a memory cell. The present invention relates to a sense circuit and a semiconductor nonvolatile memory.

  Semiconductor non-volatile memory has been increasingly miniaturized and increased in capacity. However, the semiconductor nonvolatile memory cannot be miniaturized according to the scaling law, and the cell current at the smallest cell is decreasing. For this reason, a semiconductor nonvolatile memory requires a high-speed and high-sensitivity memory cell sensing method.

  On the other hand, while the cell current is decreasing, the increase in the memory capacity required for the system exceeds the miniaturization speed, and therefore the mat size of the array in which the memory cells are arranged is increasing. There is no problem if the capacity of the bit line or the like decreases with miniaturization, but the actual memory cell size becomes smaller and the bit line lateral direction and fringe capacity increase, which increases the array mat size. In combination with this, the bit line capacitance increases. An increase in bit line capacitance may cause a problem when performing highly sensitive sensing.

  Further, since the access speed must be maintained even when the memory capacity is increased, a sense amplifier and a sense technique with higher speed and higher sensitivity are required to maintain the access speed.

  For example, a VGA (Virtual Ground Array Architecture) configuration is well known as an array architecture suitable for high integration in a semiconductor non-volatile memory. Various techniques for using a dynamic amplification type sense amplifier and maintaining the symmetry of the differential input as much as possible have been developed.

  Specifically, the folded bit line method is adopted for the bit line, and the mutual distance between the bit line and the reference bit line is made much closer compared to the previous open bit line method, and the electrical characteristics are less likely to be imbalanced. Furthermore, a method has been proposed in which the noise voltage coupled from another conductor such as a peripheral circuit to the paired line is made as equal as possible (see, for example, Patent Document 1).

  FIG. 18 is a block diagram showing a configuration of a conventional semiconductor nonvolatile memory 4000. As shown in FIG. 18, the semiconductor nonvolatile memory 4000 includes a memory cell, a bit line BL, a word line WL, a reference bit line BLR, a Y decoder 4001, a reference unit 4002, and a sense amplifier 4003.

  The memory cells are arranged in a matrix. Further, the bit lines BL are arranged in the column direction between the memory cells arranged in a matrix, and the word lines WL are arranged in the row direction between the memory cells arranged in a matrix.

  The reference bit line BLR is a wiring for receiving noise and the like on the memory cell side in the data read operation, and has a parasitic capacitance equivalent to the parasitic capacitance associated with the bit line BL. I am doing so. Usually, the reference bit line BLR is usually arranged for each sense amplifier (in some cases, a plurality of sense amplifiers share the reference bit line). The reference bit line BLR and the bit line BL paired with the reference bit line BLR are laid out in a form that maintains relatively symmetry in the vicinity.

  The Y decoder 4001 connects the bit line BL to which the memory cell to be read is connected to the sense amplifier 4003.

  The reference unit 4002 generates a reference voltage Vref used in the sense amplifier 4003.

  The sense amplifier 4003 amplifies and outputs the voltage difference between the voltage Vcell of the bit line BL connected by the Y decoder 4001 and the reference voltage Vref serving as a reference.

  In the semiconductor nonvolatile memory 4000 configured as described above, when data is read from the memory cell, first, the bit line BL connected to the diffusion layer of the memory cell to be read and the gate are connected. The data stored in the memory cell is read using the word line WL, and the voltage Vcell of the bit line BL connected to the drain side is output to the Y decoder 4001. The Y decoder 4001 outputs the voltage Vcell of the bit line BL connected to the drain side to the sense amplifier 4003.

  On the other hand, the reference unit 4002 generates a reference voltage Vref and outputs it to the sense amplifier 4003. Two reference bit lines BLR are selected and connected to the reference unit 4002.

As a result, the parasitic capacitance associated with the bit line BL connected to the memory cell from which data is read becomes equal to the parasitic capacitance associated with the reference bit line BLR connected to the reference unit 4002. That is, the capacitance balance between the bit line BL and the reference bit line BLR is maintained, and the noise received by the paired bit lines can be made substantially equal. As a result, the signal difference between the read signal from the memory cell and the read signal from the reference unit can be made a signal suitable for differential amplification that depends substantially only on the difference in cell current.
US Pat. No. 6,128,226 (first page, FIG. 1)

  However, in the semiconductor non-volatile memory employing the folded bit line method for the above bit line, the size of the array increases as the memory capacity increases, and there are many arrays of memory cells to be handled by one sense amplifier. Become. Therefore, although the comparison bit line and the reference bit line are closer to each other than the previous open bit line system, the distance may be increased by about several hundred μm as the capacity increases. As the distance increases, an electrical imbalance occurs and differential noise is mixed, and it has become impossible to realize sufficient speed and sensitivity.

  The present invention has been made paying attention to the above-mentioned problem, and provides a measurement circuit suitable for measuring a voltage difference resistant to noise and with high accuracy in a semiconductor chip, for example, a semiconductor having a VGA configuration. An object of the present invention is to provide a sense circuit capable of highly sensitive sensing even when the size of the array is increased in a nonvolatile memory or the like.

In order to solve the above problems, the invention of claim 1
A voltage measurement circuit for measuring a voltage difference between a first voltage and a second voltage,
The first wiring to which the first voltage is supplied and the second wiring to which the second voltage is supplied, and the stray capacitance of the first wiring and the stray capacitance of the second wiring. And a pair wiring in which the first wiring and the second wiring are configured, so that
A differential amplifier that differentially amplifies a voltage input from the first wiring and a voltage input from the second wiring;
It is provided with.

The invention of claim 2
A current measuring circuit for measuring current flowing into or out of the two terminals of the device under test;
The first wiring connected to one terminal of the two terminals and the second wiring connected to the other terminal of the two terminals, and the stray capacitance of the first wiring and the second wiring A pair of wirings in which the first wiring and the second wiring are configured so that the stray capacitance of the wiring of
A differential amplifier that differentially amplifies the current flowing in the pair wiring;
It is provided with.

  As a result, noise included in the two input signals becomes in-phase noise, so that the noise is canceled out by the differential amplifier. As a result, it is possible to measure a current / voltage difference that is highly resistant to noise and accurate.

The invention of claim 3
A source line that is a bit line connected to the source diffusion region of the memory cell and a drain line that is a bit line connected to the drain diffusion region, and the floating capacitance of the source line and the floating capacitance of the drain line So that the source line and the drain line are configured to be substantially equivalent,
A differential amplifier that differentially amplifies the voltage at the source line and the voltage at the drain line;
It is provided with.

  As a result, noise included in signals input to the two bit lines connected to the memory cell becomes in-phase noise, so that the noise is canceled out by the differential amplifier. As a result, it is possible to perform a noise-resistant sensing operation in memory reading by the single-ended sensing method.

The invention of claim 4
The sense circuit of claim 3, further comprising:
A first precharge circuit for precharging the source line to a first voltage potential;
A second precharge circuit for precharging the drain line to a second voltage potential;
The differential amplifier is configured to differentially amplify after the precharge of the source line and the drain line is released.

The invention of claim 5
The sense circuit of claim 4,
Each of the pair wiring, the differential amplifier, the first precharge circuit, and the second precharge circuit is provided for each of a reference memory cell and a read memory cell for reading data,
The output voltage of the differential amplifier for the read memory cell and the output voltage of the differential amplifier for the reference memory cell are configured to be differentially amplified.

The invention of claim 6
The sense circuit of claim 3,
And a current monitor that outputs a voltage signal according to the amount of current flowing through the source line and a voltage signal according to the amount of current flowing through the drain line,
The differential amplifier is configured to differentially amplify a signal output from the current monitor.

The invention of claim 7
The sense circuit of claim 6, wherein
Further, two current monitors for outputting a voltage signal corresponding to the amount of current flowing through the source line and a voltage signal corresponding to the amount of current flowing through the drain line are provided for the reference memory cell and for the read memory cell. ,
The read memory cell differential amplifier is configured to differentially amplify a signal output from the read memory cell current monitor,
The reference memory cell differential amplifier is configured to differentially amplify a signal output from the reference memory cell current monitor.

  As a result, it is possible to improve noise resistance at the time of reading in a memory or the like that precharges the bit line and measures the voltage and current of the bit line after releasing the precharge to read the storage state of the memory cell. Further, when a reference cell is provided, the speed can be increased.

The invention of claim 8
A semiconductor non-volatile memory having a virtual ground array configuration,
A sense circuit according to any one of claims 4 and 6, comprising:
The second precharge circuit is configured to precharge a drain line of a memory cell adjacent to the memory cell to be read when reading from the memory cell is performed.

The invention of claim 9
A semiconductor non-volatile memory having a virtual ground array configuration,
A sense circuit according to any one of claims 5 and 7, comprising:
The second precharge circuit for the read memory cell is configured to precharge the drain line of the read memory cell adjacent to the read memory cell to be read when reading from the read memory cell is performed. ,
The reference cell second precharge circuit is configured to precharge a drain line of a reference memory cell adjacent to a reference memory cell to be read.

The invention of claim 10 provides
A semiconductor non-volatile memory having a virtual ground array configuration,
A sense circuit according to any one of claims 4 and 6;
A first memory cell and a second memory cell configured to be read simultaneously;
A third memory cell provided between the first memory cell and the second memory cell,
In the third memory cell, when the first memory cell and the second memory cell are read simultaneously, the source line and the drain line connected to the third memory cell are precharged to the same potential. It is comprised so that it may be comprised.

The invention of claim 11
The semiconductor nonvolatile memory according to claim 10, comprising:
The first memory cell, the second memory cell, and the third memory cell are provided for a reference memory cell and a read memory cell, respectively.

  Thus, it is possible to perform a noise-resistant sensing operation in the semiconductor nonvolatile memory and not to be affected by the memory cell adjacent to the memory cell to be read at the time of reading. In addition, since the number of bit lines to be precharged can be reduced, the current can be reduced.

The invention of claim 12
The semiconductor nonvolatile memory according to claim 11, comprising:
In addition, when the reference cell is read, each of the source lines of the reference cell to be read and other reference memory cells, and a switch for electrically connecting the drain lines, respectively,
The read reference memory cell is configured to be read simultaneously with other reference cells when reading is performed.
The two reference memory cells read simultaneously are characterized in that predetermined information is stored in each of them so that different currents flow when reading is performed.

  Thereby, since the amount of current flowing into the sense circuit can be adjusted, the circuit for adjusting the current amount of the reference cell itself can be reduced.

The invention of claim 13
A semiconductor nonvolatile memory according to any one of claims 9 and 11, comprising:
The precharge voltage by the first precharge circuit for the read memory cell and the precharge voltage by the first precharge circuit for the reference cell are configured to have the same potential.

The invention of claim 14
A semiconductor nonvolatile memory according to any one of claims 9 and 11, comprising:
The precharge voltage by the second precharge circuit for the read memory cell and the precharge voltage by the second precharge circuit for the reference cell are configured to have the same potential.

  As a result, the precharge voltages of the read memory cell and the reference memory cell are equalized, and an accurate sensing operation is possible.

The invention of claim 15
A semiconductor nonvolatile memory according to any one of claims 3 to 13,
The memory cell is a floating gate type memory cell.

The invention of claim 16
A semiconductor nonvolatile memory according to any one of claims 3 to 13,
The memory cell is a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell.

  As a result, in a semiconductor nonvolatile memory constituted by floating gate type memory cells and MONOS type memory cells, it is possible to perform a sensing operation resistant to noise.

The invention of claim 17
A first differential amplifier and a second differential amplifier having the same gain and different optimum input ranges;
And a third differential amplifier for differentially amplifying the outputs of the first differential amplifier and the second differential amplifier.

  As a result, accurate differential amplification is possible with a simple circuit configuration.

  According to the present invention, it is possible to measure a voltage difference or a current difference with high accuracy against noise and with high accuracy.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 of the Invention
FIG. 1 is a block diagram showing a configuration of a voltage difference measurement circuit 100 according to Embodiment 1 of the present invention. The voltage difference measuring circuit 100 measures the voltage difference between the two output terminals by differentially amplifying the voltage between the two output terminals of the device under test 1000.

  Specifically, the voltage difference measuring circuit 100 includes a differential amplifier 110 and a pair wiring 120 as shown in FIG.

  The differential amplifier 110 amplifies the voltage difference between the input signals and outputs the amplified signal. In the present embodiment, the gain (A) of the differential amplifier 110 is set to 1. A node to which the positive phase side (high side) voltage of the differential amplifier 110 is input is referred to as VH, and a node to which the negative phase side (low side) voltage is input is referred to as VL.

  The pair wiring 120 is a pair wiring composed of a first signal line 120a and a second signal line 120b. The pair wiring 120 is laid from the differential amplifier 110 to the device under measurement 1000 and is electrically connected to measure a voltage difference between two output terminals of the device under measurement 1000.

  In the first signal line 120a and the second signal line 120b, modeled stray capacitances Cs_m0 and Cs_m1 exist between the ground terminals GND_m0 and GND_m1, respectively.

  The first signal line 120a and the second signal line 120b are laid out so that the stray capacitances Cs_m0 and Cs_m1 are almost the same. Specifically, for example, a layout considering the symmetry of the pair wiring 120 with respect to the base and the symmetry with respect to the upper layer wiring, or laying a GND level wiring on both sides of the pair wiring 120 is performed. Can adjust the stray capacitance.

  In the conventional voltage difference measurement circuit, one end of the device under test 1000 is connected to a common terminal, for example, a GND terminal, and the other end is fed into the voltage difference measurement circuit.In this embodiment, as described above, Nodes at both ends of the device under measurement 1000 are connected to the differential amplifier 110 via a balanced wiring 120 that is balanced.

  Hereinafter, the voltage difference measurement operation of the present embodiment will be described.

  In general, in a semiconductor integrated circuit, when the chip becomes larger and the distance between the device under test 1000 and the differential amplifier 110 becomes longer, the GND level and the voltage in the vicinity of the device under test 1000 are monitored at GND. There will be a difference in level.

  For example, if the position is different due to the floating of the GND line voltage due to the current flowing through the GND line and the GND level bounce due to the current accompanying the circuit operation in various places, the GND level is different and various noises are introduced. In the present embodiment, when noise enters the floating capacitances GND_m0 and GND_m1 with respect to the GND level in the vicinity of the differential amplifier 110, the floating capacitance with respect to the GND of each wiring configuring the paired wiring is aligned. The same amount of noise appears at the VH and VL nodes. That is, noise as in-phase noise is placed on the VH node and the VL node, that is, the two input terminals of the voltage difference measuring circuit 100. This noise is canceled as the output of the differential amplifier 110, and the output voltage (measured value) is a voltage not affected by the noise.

  As described above, according to the present embodiment, the pair wiring is laid like a twisted pair known in a general electric circuit, and the respective stray capacitances are adjusted to be equal. Further, in this embodiment, a common ground of one of the elements to be measured in the semiconductor integrated circuit is floated from the GND, and the voltage between these two terminals is measured, so that it is possible to measure a voltage difference resistant to noise and with high accuracy. become.

  In this embodiment, the circuit to be measured 1000 is not particularly specified. However, the element to be measured 1000 may be a device having an electromotive force such as a photodiode, an MRAM (Magnetoretic RAM), or a PRAM (PRAM). The present embodiment can be applied to various elements such as a phase change random access memory (FG), an FG type memory (floating gate type memory), and a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory element.

  In addition, in the conventional signal transmission in SRAM (Static RAM), DRAM (Dynamic RAM), etc., a method of transmitting read data using a pair wiring is taken, but these send out complementary signals, It is not used for non-complementary signal transmission as in this embodiment.

  Further, it may be configured as a current measuring circuit that differentially amplifies the current flowing into or out of the two terminals of the element to be measured. Also in this case, the noise on the pair wiring is canceled as the output of the differential amplifier. Therefore, the output voltage (measured value) is a voltage that is not affected by noise, and accurate current measurement is possible.

<< Embodiment 2 of the Invention >>
FIG. 2 is a block diagram showing a configuration of the sense circuit 200 according to Embodiment 2 of the present invention. The sense circuit 200 is an example in which the voltage difference measurement circuit 100 according to the first embodiment is applied to a sense circuit in a memory circuit.

  The sense circuit 200 reads information stored in the memory cell 2000 (M0 and M1 in FIG. 2). This memory cell 2000 is a non-volatile memory in which the cell current of the read cell changes according to the written information. In the present embodiment, for the sake of simplicity, it is assumed that a prescribed read current flows when “1” is stored as information, and no current flows when “0” is stored as information. explain.

  As shown in FIG. 2, the sense circuit 200 includes a differential amplifier 110, a pair wiring 220, select transistors 230a and 230b, a precharge switch 240, a reset switch 250, and a differential amplifier 260. In the following embodiments, components having the same functions as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The pair wiring 220 includes a bit line 220a (BLS) and a bit line 220b (BLD), and connects the memory cell 2000 to the selection transistor 230a (ML_m) / selection transistor 230b (MH_m) as shown in FIG. It is like that. The bit line 220a has a stray capacitance Cs_m0 between the ground GND_m0 and the bit line 220b has a stray capacitance Cs_m1 between the ground GND_m1 and the bit lines 220a and 220b. The capacitance is balanced so that Cs_m0 and Cs_m1 become equal by adjustment.

  In the bit lines 220a and 220b, the bit line 220b is connected to the high-side node VH of the differential amplifier 110 and the bit line 220a is connected to the low-side node VL via the selection transistors 230a and 230b, respectively. The bit lines 220a and 220b between the selection transistors 230a and 230b and the differential amplifier 110 are also configured to be paired wirings with balanced capacitance as described above.

  The selection transistors 230a and 230b are configured to activate and deactivate the bit lines 220a and 220b, respectively.

  The precharge switch 240 (SW_P) is a switch for precharging the bit line 220b to the precharge level VdBL.

  The reset switch 250 (SW_R) is a switch for resetting the bit line 220a to the GND level.

  The differential amplifier 260 outputs a signal (Sout) obtained by differentially amplifying the output voltage (Vout) of the differential amplifier 110 and the reference voltage (VREF).

  In the sense circuit 200 configured as described above, when information is read from the memory cell 2000, first, the selection transistors 230a and 230b are turned on, the precharge switch 240 (SW_P) is turned on, and further the reset switch 250 (SW_R). Is turned on, and the word line WL of the memory cell to be read (for example, M0) is activated.

  As a result, the potential of the bit line 220b connected to the high-side node VH of the differential amplifier 110 rises to the precharge level VdBL. In addition, the bit line 220a connected to the low-side node VL of the differential amplifier 110 is kept at the GND level.

  Next, when the precharge switch 240 (SW_P) and the reset switch 250 (SW_R) are turned off, for example, when the information of the activated read memory cell is “0”, a current flows in the memory cell. Not flowing. Therefore, both the high-side node and the low-side node of differential amplifier 110 are kept at the voltage level before the switch is turned off.

  Further, for example, when the information of the memory cell is “1”, a prescribed read current flows through the memory cell, so that the voltage of the high-side node VH of the differential amplifier 110 drops at a constant speed. The low-side node VL has a polarity opposite to that of the high-side node VH, and the voltage rises at a constant speed. FIG. 3 is a diagram showing voltage waveforms of the bit lines 220a and 220b when the above operation is performed.

  Here, for example, noise that causes floating of the ground GND_m0 and GND_m1 of the stray capacitances Cs_m0 and Cs_m1 is input at the sense data determination timing (timing when an appropriate waiting time for outputting a predetermined level from the differential amplifier 260). In this case, since the pair wiring 220 is laid out so as to have a symmetric stray capacitance with respect to the ground, the same amount is included in the high-side node VH and the low-side node VL of the differential amplifier 110. Noise will appear in the signal. When the noises input to the node VH and the node VL are common-mode noises, they are canceled by the differential amplifier 110 and do not appear as noise at the output of the differential amplifier 110.

  Then, after an appropriate waiting time has elapsed to determine the level of the output (sense data) from the differential amplifier 110, the output of the differential amplifier 110 is compared with the reference voltage VREF by the differential amplifier 260. As a result, a signal (Sout) corresponding to whether the information in the memory cell is “1” or “0” is output from the differential amplifier 260.

  As described above, according to the present embodiment, since the stray capacitances of the bit lines 220a and 220b are configured to be equal, noise generated in the bit lines 220a and 220b becomes in-phase noise. Canceled by the differential amplifier 110. Therefore, erroneous detection of sense data is eliminated, and noise-resistant reading is possible.

<< Embodiment 3 of the Invention >>
FIG. 4 is a block diagram showing a configuration of the sense circuit 300 according to Embodiment 3 of the present invention. As shown in FIG. 4, the sense circuit 300 includes a pull-up resistor 340 (RL) instead of the precharge switch 240 in the second embodiment, and a pull-down resistor 350 (RL ′) instead of the reset switch 250. Yes. In the sense circuit 200 according to the second embodiment, the memory cell state is determined by a dynamic operation. However, in this embodiment, data is read according to the presence or absence of a read current depending on the “0” or “1” state of the memory cell. It has become.

  In the sense circuit 300 configured as described above, when information is read from the memory cell 2000, the pull-up resistor 340 and the pull-down resistor 350 cause a voltage drop and a voltage rise. As a result, information (data) is read according to the degree to which the voltage at the high side and low side nodes of the differential amplifier 110 decreases and the voltage at the high side and low side nodes decreases. Since the noise generated in the bit lines 220a and 220b becomes common-mode noise as in the circuit of the second embodiment, this noise is canceled out by the differential amplifier 110.

  Therefore, also in this embodiment, sense data is not erroneously determined, and noise-resistant readout is possible.

<< Embodiment 4 of the Invention >>
FIG. 5 is a block diagram showing a configuration of the sense circuit 400 according to the fourth embodiment of the present invention.

  The sense circuit 400 includes a differential amplifier 110, a pair wiring 220, select transistors 230a and 230b, a precharge switch 240, a reset switch 250, a differential amplifier 260, a high-side current monitor 440, and a low-side current monitor 450. Has been.

  The high-side current monitor 440 (current monitor IH) monitors the current flowing between the node of the precharge level VdBL and the bit line 220a, and outputs a voltage of conductance g times to the node VH of the differential amplifier 110. It has become.

The low-side current monitor 450 (current monitor IL) monitors the current flowing between the ground and the bit line 220b, and outputs a voltage of conductance g times to the node VL of the differential amplifier 110. (Specifically, these current monitors and differential amplifier 110 can be configured by current-driven sense amplifiers whose specific circuit examples are described later in the seventh embodiment.)
In the sense circuit 400 configured as described above, when information is read from the memory cell 2000, first, the selection transistors 230a and 230b are turned on, the precharge switch 240 (SW_P) is turned on, and further the reset switch 250 (SW_R). Is turned on, and the word line WL of the selected memory cell (for example, M0) is activated. As a result, the potential of the bit line 220b connected to the high-side node VH of the differential amplifier 110 rises to the precharge level VdBL. On the other hand, the bit line 220a connected to the low-side node VL of the differential amplifier 110 is kept at the GND level. At this time, no current flows through the high-side current monitor 440 and the low-side current monitor 450 because both ends are short-circuited by the precharge switch 240 and the reset switch 250, respectively.

  Next, when the precharge switch 240 (SW_P) and the reset switch 250 (SW_R) are turned off, for example, when the information of the activated read memory cell is “0”, a current flows in the memory cell. Since the current does not flow, both the high-side node and the low-side node of the differential amplifier 110 are maintained at the voltage level before the switch is turned off. Therefore, no current flows through the high-side current monitor 440 and the low-side current monitor 450.

  On the other hand, in the case of the cell information “1”, since a prescribed read current flows from the memory cell, the read current (IH) flows out from the high side current monitor 440, and the low side current monitor 450 includes the high side current monitor 440. A current (-IL) having a reverse polarity flows. Then, the high-side current monitor 440 and the low-side current monitor 450 output voltages that are times the conductance g of the respective monitor currents. FIG. 6 is a diagram showing current waveforms of the high-side current monitor 440 and the low-side current monitor 450 when the above operation is performed. In the figure, + Imem and -Imem are currents (memory cell currents) flowing from the cells during reading.

  Here, for example, when noise that causes floating of the ground GND_m0 and GND_m1 of the stray capacitances Cs_m0 and Cs_m1 at the timing when the sense data is determined by the differential amplifier 260, the pair wiring 220 is Since the layout is made to have a symmetrical stray capacitance, the change in the ground voltage becomes a transition current, and the same amount of current flows into both the bit line 220a and the bit line 220b. This transition current is monitored by the high-side current monitor 440 and the low-side current monitor 450 and input to the differential amplifier 110 at the next stage. Noises input to the node VH and the node VL are equivalent in-phase noise. The noise input to each node is canceled by the differential amplifier 110 and does not appear as noise at the output of the differential amplifier 110.

  Therefore, also in this embodiment, sense data is not erroneously determined, and noise-resistant readout is possible.

<< Embodiment 5 of the Invention >>
FIG. 7 is a block diagram showing a configuration of a sense circuit 500 according to the fifth embodiment of the present invention.

  In the fifth embodiment, an example of a sense circuit in a memory circuit including a reference cell 3000 (MR) in which a read current is adjusted to about half that of the memory cell 2000 will be described.

  As shown in FIG. 7, the sense circuit 500 is configured by further adding a pair wiring 520, selection transistors 530 a and 530 b, a precharge switch 540, and a reset switch 550 to the sense circuit 200.

  The differential amplifier 510 amplifies the voltage difference between the input signals and outputs the amplified signal. In the present embodiment, the gain (A) of the differential amplifier 510 is set to 1.

  The pair wiring 520 includes a first reference side signal line 520a (BLS_r) and a second reference side signal line 520b (BLD_r), and includes a reference cell 3000, a selection transistor 530a (ML_r), a selection transistor 530b (MH_r), and the like. Is supposed to be connected. The first reference side signal line 520a has a stray capacitance Cs_r0 between the ground GND_r0 and the second reference side signal line 520b has a stray capacitance Cs_r1 between the ground GND_r1 and the ground GND_r0. The capacitances are balanced so that Cs_r0 and Cs_r1 become equal by adjusting the layout of the first reference side signal line 520a and the second reference side signal line 520b.

  The first reference side signal line 520a and the second reference side signal line 520b are connected to the high side node VH of the differential amplifier 510 via the selection transistors 530a and 530b, respectively. The first reference side signal line 520a is connected to the low side node VL. The first reference-side signal line 520a and the second reference-side signal line 520b between the selection transistors 530a and 530b and the differential amplifier 510 are also configured to be paired wirings with balanced capacitance as described above. Yes.

  The selection transistors 530a and 530b are configured to activate and deactivate the first reference-side signal lines 520a and 520b, respectively.

  In this embodiment, the precharge, reset, VdBL, and GND nodes on the memory cell 2000 side and the reference cell 3000 side are common nodes, and power is supplied from the common node to the memory cell side and the reference side. I have to. This is because if the voltages applied to the memory cell 2000 side to be compared and the reference cell 3000 side are different, that amount is output as an error.

  In the sense circuit 500 configured as described above, when information is read from the memory cell 2000, the memory cell 2000 and the reference cell 3000 are except that the reference cell 3000 side is controlled by the memory reference word line REFWL. Other operations are performed completely symmetrically.

  First, the selection transistors 230a, 230b, 530a, and 530b are turned on, the precharge switches 240 and 540 (SW_P) are turned on, and the reset switches 250 and 550 (SW_R) are turned on. The word line WL of M0) and the memory reference word line REFWL are activated.

  Next, when the precharge switches 240 and 540 and the reset switches 250 and 550 are turned off, the voltage waveform of the pair wiring 220 (voltage waveform corresponding to information “0” or “1”) and the pair wiring 520 The gap (voltage difference) with the voltage waveform increases.

  FIG. 8 shows the bit lines 220b and 220a in the states where the memory cell information is “0” and “1”, and the second reference side signal line 520b and the first reference side signal line 520a on the reference cell 3000 side. Each voltage waveform is shown. In the voltage waveform (Ref) of the pair wiring 520, since the cell current of the reference cell 3000 is set to half the cell current of the memory cell 2000, the voltage waveform when the information is just “0” and the case of “1” Is located in the center of the voltage waveform. Therefore, from the timing when the precharge switches 240 and 540 and the reset switches 250 and 550 are turned off, the voltage waveform when the information is “1” and the voltage waveform of the pair wiring 520 and the information are “0”. In this case, the difference between the voltage waveform and the voltage waveform of the pair wiring 520 increases.

  Here, for example, when noise is applied to the pair wiring 220, the noise generated in the bit lines 220a and 220b becomes in-phase noise, so that the output (Vout) of the differential amplifier 110 as shown in FIG. No noise appears.

  When the bit line on the memory cell 2000 side and the bit line on the reference cell 3000 side are laid out at a distance, symmetry with respect to noise such as ground is lost. Resistance can be prevented from deteriorating.

  In addition, in the present embodiment, the reading speed can be improved by shifting the timing for determining the reading forward. For example, in the second embodiment, the information cannot be sensed unless the voltage in the case of the information “1” is the timing after crossing the reference potential VREF. Of course, in the second embodiment, the timing for sensing information can be changed by changing the setting of the reference voltage VREF. However, when variations such as a variation factor, the number of factors, a variation amount, and symmetry are considered, the limit comes first. On the other hand, in this embodiment, since the AC matching is performed by the reference cell 3000, the sense timing (t_sense) can be shifted before the timing shown in FIG. Specifically, it can be advanced to the limit of the differential amplifier 260 at the next stage for determining the differential voltage.

  As described above, according to the present embodiment, it is possible to achieve a high-precision and high-speed sensing operation without deteriorating noise tolerance.

Embodiment 6 of the Invention
Instead of the differential amplifier 110, the differential amplifier 260, and the differential amplifier 510 (these are referred to as an amplifier unit) in the fifth embodiment, an amplifier unit illustrated in FIG. 9 may be used. This amplifier unit is an example in which the circuit scale can be made smaller than that of the amplifier unit in the fifth embodiment.

  First, the amplifier unit in the fifth embodiment will be described in detail. FIG. 10 shows the amplifier unit in the fifth embodiment again. This configuration can be viewed as a dual differential amplifier (voltage-type dual differential amplifier). In the amplifier unit of the fifth embodiment, the first-stage amplifier (differential amplifier 110) does not increase the gain so much that the inputs from the nodes VH_m and VL_m (the high side and low side nodes on the memory cell 2000 side) are different. Dynamically amplified and output (here, gain A = 1). Similarly, the differential amplifier 510 is configured to differentially amplify and output the inputs from the high side and low side nodes on the reference cell 3000 side. The outputs of the differential amplifier 110 and the differential amplifier 510 are input to the next-stage amplifier (differential amplifier 260) for differential amplification.

  In the above configuration, the first stage amplifier performs differential amplification between the high side level and the low side level of the bit line, and then performs differential amplification of the output of the differential amplifier 110 and the output of the differential amplifier 510. Therefore, the input range of the first stage amplifier is widened. In other words, the first-stage amplifier must amplify a relatively large input range, and a MOS amplifier or the like cannot cope with simple differential amplification. For this reason, the first-stage amplifier requires various additional circuits, and the circuit scale tends to increase.

  On the other hand, the amplifier unit 600 according to the sixth embodiment includes a differential amplifier 610, a differential amplifier 620, and a differential amplifier 630 as shown in FIG. The amplifier unit 600 differentially amplifies the voltage of the node VH_m and the voltage of the node VH_r among the signals input from the four nodes (VH_m, VL_m, VH_r, and VL_r) by the differential amplifier 610, and the voltage of the node VL_m The voltage of the node VL_r is differentially amplified by the differential amplifier 620, and then the output of the differential amplifier 610 and the output of the differential amplifier 620 are differentially amplified by the differential amplifier 630. Therefore, according to this embodiment, the first-stage amplifier does not need to amplify a signal having a large input range.

  Assuming that the gain (A) of each amplifier is A = 1, the voltage (Sout) finally output from the amplifier unit and the amplifier unit 600 according to the fifth embodiment is expressed by the equations shown in FIGS. 10 and 9, respectively. It becomes like this. If the equation is transposed, it can be seen that both outputs have the same value.

  FIG. 11 is a diagram illustrating a more specific configuration example of the amplifier unit 600. This amplifier section includes a current limiting transistor MN00 and current mirror transistors MP00 and MP01, and Nch transistors MN30 and MN31 controlled by first differential inputs (VH_m and VH_r) are connected therebetween. . Only the elements described so far are general differential amplifiers, which are circuits that differentially amplify two inputs on the high side level.

  In the amplifier unit 600, Nch transistors MN20 and MN21 for further differential input are connected. On the node VL_m side, a level shifter / inverter composed of a Pch transistor MP10 and an Nch load MN10 is connected, and this output is connected to the gate of the previous Nch transistor MN20. The same applies to the reverse node VL_r. The level, gain, etc. of this amplifier can be set according to the device size.

  As described above, according to the present embodiment, the range of the signal input to each amplifier in the first stage is smaller than that of the amplifier of the second embodiment, so that the dual differential amplifier has a smaller circuit scale than the amplifier section of the second embodiment. Can be obtained.

<< Embodiment 7 of the Invention >>
Instead of the amplifier unit in the fifth and sixth embodiments, an amplifier unit shown in FIG. 12 may be used. This amplifier unit is an example of a current-driven amplifier that can replace the amplifier unit (voltage type dual differential amplifier) in the fifth and sixth embodiments.

  FIG. 12 is a block diagram illustrating a configuration of the amplifier unit 700 according to the seventh embodiment. As shown in FIG. 12, the amplifier unit 700 includes a voltage-type dual differential amplifier 710, a current-voltage conversion circuit 720 (current-voltage conversion_H), and a current-voltage conversion circuit 730 (current-voltage conversion_L). Yes. As shown in the figure, the amplifier unit 700 includes a current-voltage conversion circuit 720 for the high-side node and a current-voltage conversion circuit 730 for the low-side node before the four-input terminals of the voltage-type dual differential amplifier 710. Each is inserted.

  The voltage type dual differential amplifier 710 is the amplifier unit (voltage type dual differential amplifier) in the fifth and sixth embodiments.

  As illustrated in FIG. 12, the current-voltage conversion circuit 720 includes a resistor 721, a control Nch transistor 722, and a differential amplifier 723. The current-voltage conversion circuit 720 includes a differential amplifier 723 in which a set voltage VdBL is input to one node so that a current is output from the power supply Vdd via the resistor 721 and the control Nch transistor 722 at a constant voltage. The control Nch transistor 722 is controlled by the amplified output, and a voltage dropped from the power supply voltage Vdd is output from the output terminal OUT according to the flowing current. Specifically, an output VH_m ′ is output to the terminal VH_m, and an output VH_r ′ is output to the terminal VH_r.

  The current-voltage conversion circuit 730 includes a resistor 731, a control Pch transistor 732, and a differential amplifier 733. The current-voltage conversion circuit 730 has a differential amplifier 733 in which a set voltage 0 V is input to one node so that current is output at a constant voltage from the negative power source Vneg via the resistor 731 and the control Pch transistor 732. The control Pch transistor 732 is controlled by the amplified output, and a voltage increased from the negative power source Vneg is output from the output terminal OUT according to the flowing current. Specifically, an output VL_m ′ is output to the terminal VL_m, and an output VL_r ′ is output to the terminal VL_r.

  In the amplifier unit 700 configured as described above, the current value as the sum of the current values on the high side and the low side is evaluated on both the memory cell 2000 side and the reference cell 3000 side (actually, the vector direction is reversed). Therefore, the difference in current value between the high side and the low side is evaluated.)

  Therefore, for example, when some noise is placed on the pair wiring 220 in the circuit in which the amplifier unit 700 is applied instead of the amplifier unit of the fifth embodiment, almost the same noise is generated in the bit line 220a and the bit line 220b. appear. This noise is canceled by the voltage-type dual differential amplifier 710 after current-voltage conversion, as in the fifth embodiment. FIG. 13 shows the current flowing in the amplifier unit 700 on the high side and the low side when the amplifier unit 700 is applied instead of the amplifier unit of the fifth embodiment.

  As described above, even when a current drive type amplifier is used, it is possible to perform a sense operation with good noise resistance.

<< Embodiment 8 of the Invention >>
An example in which the sense circuit is applied to a semiconductor nonvolatile memory in which a virtual ground array architecture (hereinafter, abbreviated as VGA) configuration is adopted as a memory array will be described.

  FIG. 14 is a block diagram showing a configuration of a semiconductor nonvolatile memory 800 according to Embodiment 8 of the present invention, and shows a configuration for explaining only reading.

(Overall configuration)
The semiconductor nonvolatile memory 800 is a memory having a virtual ground array configuration (hereinafter referred to as a VGA configuration), and as shown in FIG. 14, a plurality of array units (ARRAY00-13), a reference cell array (REF ARRAY), and a control circuit. 810, a row predecoder 820, a row decoder 830, a REF row decoder 840, a column decoder 850, a selection line decoder 860, a column selection circuit 870, a precharge / reset control circuit 880, and a sense circuit block 890, for example, a MONOS type nonvolatile memory The memory is configured.

(Configuration of memory array)
In the present embodiment, for the sake of simplicity, an example will be described in which two word lines are provided in one sector.

  In the semiconductor nonvolatile memory 800, ARRAY00 to 03 in which the VGA configuration is adopted for the sub-bit lines are sequentially arranged in the word line direction as shown in FIG. 14, and the reference bit line unit is further arranged.

  In the lower part of ARRAY00 to 03, ARRAYs 10 to 13 are arranged as separate sectors, and blocks in which reference bit lines are arranged are similarly arranged.

  Further, a reference cell array of 2 rows × 8 columns is arranged in the lower stage. Also for this reference cell array, reference word lines RWL [10] to [11] similar to the word lines WL [00] to [01] of the memory cell array and selection line signals SL [00] to [07] Reference main bit lines RMBL [0] to [3] similar to the same reference selection lines RSL [00] to [07] and main bit lines MBL [0] to [3] are connected.

(Configuration of array unit ARRAY00-13)
Since all the array units ARRAY00 to 13 have the same configuration, only ARRAY00 will be described.

  FIG. 15 is a block diagram showing a specific configuration of ARRAY00. In ARRAY00, a total of 16 memory cells of 2 rows × 8 columns are arranged in a VGA configuration, and word lines WL [00] and WL [01] for selecting the memory cells are connected to the respective memory cells. ing. The sub bit lines SBL0 to SBL7 are connected to the main bit lines MBL [0] to [3] under the control of the selection line signals SL [00] to [07]. The ARRAYs 01 to 03 in the word line direction have the same structure, and the sub bit lines are selectively connected to the main bit lines.

  The ARRAY00 of this embodiment is configured so that reading is performed simultaneously for two systems. For example, in ARRAY00, two systems of the memory cell MC04 and the memory cell MC02 are read simultaneously.

  In ARRAY00, as shown in FIG. 15, the memory cells MC02 and MC04 are connected to the same word line WL [00].

  Memory cell MC02 has its source and drain connected to sub-bit lines SBL2 and SBL3, respectively. The drain of the memory cell MC04 is connected to the sub bit line SBL4, and the source of the memory cell MC04 is connected to the sub bit line SBL5. That is, the drains of two memory cells that are read simultaneously are continuously arranged with one memory cell interposed therebetween.

  The source / drain of the memory cell MC02 is connected to the main bit lines MBL [1] to [0] via the respective sub bit lines SBL2, SBL3 and select gate transistors MSL5, MSL1. Further, the main bit lines MBL [1] to [0] are connected to the nodes VL_m1 and VH_m1 of the sense circuit 891 through the column selection circuit 870, respectively.

  The source / drain of the memory cell MC04 has the same configuration and is connected to the nodes VL_m2 and VH_m2 of the sense circuit 892, respectively.

  Other memory cells (MC00, MC01, etc.) are also connected to the sub-bit lines, respectively, as shown in FIG. 15, and further connected to the main bit line via the select gate transistor.

(Reference cell array configuration)
In the reference cell array, as shown in FIG. 16, the reference cells MR02 and MR04 are arranged in the order of the source / drain of the reference cell MR02 and the drain / source of the reference cell MR04, as in the case of the memory cell. It is connected to RSBL2, RSBL3, RSBL4, and RSBL5. Then, the reference main bit lines RMBL [1] to [3] are connected to each other through the reference selection gate transistors MRSL6, MRSL2, MRSL5, and MRSL1.

  Reference main bit lines RMBL [1] to [3] are connected to nodes VL_r1, VH_r1, VL_r2, and VH_r2 through a column selection circuit 870, respectively.

  As shown in FIG. 16, the other reference memory cells (MR00, MR01, etc.) are also connected to the reference sub-bit line, and further connected to the reference main bit line via a reference selection gate transistor.

  Also in this embodiment, the bit line connecting each cell and the sense circuit (the sense circuit 891 and the sense circuit 892) has a high side so that the stray capacitance is symmetric as in the above embodiment. The low side is laid out as a pair wiring.

(Configuration of control unit and data router system for controlling the memory array unit)
The control circuit 810 controls an information reading operation from the ARRAYs 00 to 13 in accordance with an externally input control signal.

  The row predecoder 820 predecodes and outputs the input row address.

  The control circuit 810 decodes the predecoded row address and activates the word line.

  The REF row decoder 840 decodes the predecoded row address and activates the reference word line.

  The column decoder 850 decodes the input column address and outputs it.

  Select line decoder 860 selects signal SL [00] to [07] for determining the connection relationship between the main bit line and the sub bit line on the memory cell side according to the column address decoded by column decoder 850, and the reference cell The selection signals RSL [00] to [07] for determining the connection relationship between the main bit line and the sub bit line on the side are output.

  The column selection circuit 870 connects the main bit line and the reference main bit line to the precharge / reset control circuit 880 in accordance with the column address decoded by the column decoder 850.

  The precharge / reset control circuit 880 precharges and resets the bit line of the selected memory cell and the bit line of the reference cell. Specifically, the bit line read voltage VdBL is applied to the nodes VH_m1 and VH_m2, which are the high-side nodes of the sense circuit 891 and the sense circuit 892, via the switch SW_P and precharged, while the sense circuit 891 and the sense circuit 891 are sensed. The bit line voltage is reset to nodes VL_m1 and VL_m2, which are nodes on the low side of the circuit 892, via the switch SW_R, and the bit line voltage is reset. Similarly, the bit line read voltage VdBL is applied to VH_r1 and VH_r2 via the switch SW_P and precharged. On the other hand, the bit line voltage is reset to VL_r2 and VL_r1 via the switch SW_R and the bit line voltage is reset. To do.

  The sense circuit block 890 includes a sense circuit 891 and a sense circuit 892. The sense circuit 891 and the sense circuit 892 are configured to read a signal from the selected bit line. Specifically, the sense circuit 891 is configured using, for example, the sense circuit described in the fifth embodiment, and is input to a high-side node (nodes VH_m1 and VH_r1) and a low-side node (nodes VL_m1 and VL_r1). A voltage signal corresponding to the voltage (or current) is output. Similarly, the sense circuit 892 outputs a signal having a voltage corresponding to the voltage (or current) input to the high-side nodes (nodes VH_m2, VH_r2) and the low-side nodes (VL_m2, VL_r2). Yes. For example, the voltage output from the sense circuit 891 is (VH_m1-VH_r1) − (VL_m1-VL_r1) where the voltages at the respective nodes are VH_m1, VH_r1, VL_m1, and VL_r1, respectively.

  Summarizing the differences between the present embodiment and the fifth embodiment, the applied memory array has a VGA configuration, two read systems are included, and has a hierarchical bit line configuration. Three points. With regard to the hierarchical bit line configuration, only the transfer gate (the selection gate transistor and the reference selection gate transistor) is added to the pair wiring connecting the memory cell and the sense amplifier, and the conventional discussion is not changed.

  Note that the VGA configuration described above is different from the array configuration shown in the fifth embodiment in the arrangement of memory cells and reference cells. In general, in the VGA configuration, the drain and source of the memory cell are continuously connected.

  In the semiconductor nonvolatile memory 800 configured as described above, for example, when two systems of the memory cells MC02 and MC04 are simultaneously read, first, the word line WL [00] is activated for reading, Become high level.

  As a result, all the memory cells (MC00 to MC07) connected to the word line WL [00] are activated, and their drain / This brings the possibility of flowing a read current between the sources. That is, when information is read from the memory cells MC02 and MC04, adjacent memory cells (bits) connected to the respective drains and sources, specifically, the memory cells MC01, MC03, and MC05 can pass current. Bring sex. For example, if these memory cells are not connected, no current flows into (or flows into) the adjacent bit line, and the situation is not different from the circuit of the fifth embodiment described above.

  Next, the column selection circuit 870 connects the main bit line pair MBL [0] and MBL [1] to the node VH_m1 and the node VL_m1, respectively. Furthermore, the main bit line pair MBL [2] and MBL [3] Are connected to the node VL_m2 and the node VH_m2, respectively.

  In addition, selection lines SL [01], SL [02], SL [05], and SL [06] are activated, and MSL01, MSL02, MSL05, and MSL06 are selected. The main bit line pair MBL [0] and MBL [1] are connected to the sub bit lines SBL4 and SBL5, respectively, and the main bit line pair MBL [2] and MBL [3] are respectively connected to the sub bit lines SBL2. And SBL3.

  Next, the precharge switch SW_P and the reset switch SW_R are turned on by the control circuit 810, and the selected word line WL [00] is activated.

  Even if the word line is activated, the value of the memory cell current is very small, so that the voltage drop and rise of the bit line due to this current can be ignored, and the sub bit lines SBL2, SBL3, SBL4 and SBL5 , VdBL, VdBL, and 0 V level, respectively, are precharged or reset.

  At this time, the same operation is performed on the reference side (reference cell array). It is assumed that all other bit lines are discharged to 0V. Note that the bit line precharge level VdBL is generally about 1 V in the case of a non-volatile memory such as an FG type due to problems such as disturb.

  Next, the precharge switch SW_P and the reset switch are turned off. As a result, the potentials of sub-bit lines SBL2, SBL3, SBL4, and SBL5 begin to change.

  Here, in the memory cell in which a series of word lines from memory cells MC01 to MC05 are activated, the memory cell to which a voltage is applied between the source and drain is the source of the memory cells MC02 and MC04 to be read. -It is only at both ends of the drain, and the voltage at both ends in other memory cells is 0V. Therefore, a read current starts to flow from sub-bit lines SBL3 to SBL2 and from sub-bit lines SBL4 to SBL5 according to the stored information of memory cells MC02 and MC04.

For example, if the memory cell MC02 stores “1” as information and the memory cell MC04 stores “0” as information, the voltage of the sub-bit line SBL2 increases and the voltage of the sub-bit line SBL3 decreases. However, the voltages on the sub bit lines SBL4 and SBL5 do not drop or rise. However, a voltage difference occurs between the source and drain of the memory cells MC01 and MC03 as time elapses. If the information stored in the memory cells MC01 and MC03 is “1” through which a current flows when the voltage difference increases, the voltage change between the sub-bit lines SBL2 and SBL3 is affected. Become. (The effect of such a leakage current to the adjacent memory cell peculiar to the VGA configuration is generally called a neighbor effect.)
Actually, it can be designed to perform the sensing operation when the voltage between the source and the drain of the memory cell adjacent to the read target bit is about 100 mV or less. When the voltage difference between the source and drain of the memory cell to be read is about 1 V or more, the voltage difference between the source and drain of the memory cells connected adjacently and possibly affecting the voltage change is about 100 mV or less. Therefore, there is a current difference of about 10 times, and the influence degree is sufficiently small.

  For this reason, other active memory cells are connected adjacent to the memory cell to be read, but the influence of this is negligible and reading is possible.

  In the present embodiment, the configuration in which two bits of the memory cells MC02 and MC04 are simultaneously read has been described. However, when only one bit is read, the following problem occurs.

  For example, assume that only the memory cell MC04 is read. In this case, the selection lines related to the sub bit lines SBL2 and SBL3 related to the memory cell MC02 side are not precharged or reset.

  When the subbit line SBL4 is precharged and then the precharge is released, the stored information in the memory cell MC03 affects the voltage transition of the subbit line SBL4 after the precharge is released. This is because the sub-bit line SBL3 that is the source of the adjacent memory cell MC03 is no longer precharged, so that the potential remains at a low voltage (in some cases, remains at 0V), and the charge of the pre-charged sub-bit line SBL4 is reduced. This is because a part of the memory cell MC03 may be pulled out to the sub bit line SBL3.

  For example, when the information “0” of the memory cell MC04 is read out, and the information of the memory cell MC03 is “1”, the adjacent subbit is read even when only the memory cell MC04 is read out. It is necessary to control the line (SBL3) to be precharged to the precharge potential VdBL or to keep the precharge potential during the reading period.

  Note that the current drive amplifier shown in FIG. 12 is used in the sense circuit instead of the voltage type dual differential amplifier, and the current drive amplifier is applied to a normal array configuration even if the other circuit configuration is the same. As in the case of (Embodiment 4), a noise-resistant readout system can be realized. That is, in the current driven amplifier, the voltage between the drain and source of the read memory cell is maintained at the precharge level (VdBL) and the reset voltage (0 V) during the read period, and between the source and drain of adjacent memory cells. Since no voltage is applied, the neighbor effect is completely eliminated, and a more sensitive sensing operation can be realized.

  As described above, also in this embodiment, sense data is not erroneously determined, and noise-resistant reading is possible.

  In this embodiment, an example in which there are two outputs has been described. However, an array unit may be further arranged in the word line direction so that multi-bit output can be performed.

  In addition, an example in which the reference cell side circuit is configured with exactly the same elements as the memory cell side has been described, but the reference array side reference word may be sufficient as the minimum array scale considering symmetry with the memory cell side. The number of lines, reference main bit lines, reference sub bit lines, and the like may be determined in consideration of symmetry with the memory side.

<< Ninth Embodiment of the Invention >>
An example of a semiconductor nonvolatile memory in which the current amount of the reference cell itself does not need to be adjusted to an intermediate level will be described. Specifically, as shown in FIG. 17, in the circuit of the eighth embodiment, switches SW_H and SW_L are respectively connected between nodes VH_r1 and VH_r2 on the bit line side of the reference cell and between VL_r1 and VL_r2. In addition, at the time of reading, the high-side nodes and the low-side nodes are short-circuited.

  In the first to eighth embodiments, information “0” indicates a state in which no current flows, “1” indicates a state in which a current flows, and the reference cell 3000 has an example in which the read current is adjusted to half that of the memory cell 2000. explained. However, an actual sense amplifier may be configured to sense a state where a large amount of current flows as “1” and a state where a small amount of current flows as “0”. In some cases, a reference cell with a read current adjusted is used.

  In the present embodiment, a memory cell in which a large amount of current flows when “1” stored is read and a small amount of current flows when “0” is read. A reference cell that is used for the reference cell array, uses a reference cell storing “1” as a reference cell connected to VH_r1 and VL_r1, and uses a reference cell storing “0” as a reference cell connected to VH_r2 and VL_r2. It is designed to be used.

  In the semiconductor nonvolatile memory configured as described above, when a high-side node and a low-side node are short-circuited at the time of reading, for example, when a current-driven amplifier is used for the sense circuit 891 or the like The currents flowing through the two nodes on the high side and the two nodes on the low side are the current flowing when “0” is read and the current flowing when “1” is read. Become sum. Therefore, the current that flows through one node of the sense amplifier is substantially the average of the current that flows when “0” is read and the current that flows when “1” is read. An operation equivalent to a reference adjusted to a current value approximately in the middle of is performed.

  When a voltage-type dual differential amplifier is used, the current flowing in the reference cell at each of the two nodes on the high side and the two nodes on the low side flows when “0” is read. This is the sum of the current and the current that flows when “1” is read. On the other hand, since the capacity of the reference main bit line is doubled, the reference current that flows when sensing is substantially the current that flows when “0” is read and the current that flows when “1” is read. An operation equivalent to a reference adjusted to a current value that is an average of the flowing current and adjusted to an intermediate current value between the two states is performed.

  According to the present embodiment, as described above, the amount of current flowing into the sense amplifier is determined using the reference cell in which information “0” is stored and the reference cell in which information “1” is stored. Since it can be adjusted, it is not necessary to adjust the current amount of the reference cell itself to an intermediate level. Therefore, the circuit for adjusting the read current of the reference cell to the intermediate level can be reduced.

  Note that the number of bits stored in the memory cells described in the above embodiments is not particularly limited. For example, a level multi-value (generally used as a multi-value memory) (current flowing through a memory cell does not flow but is weighted according to the flow amount, for example, “00”, “01”, “10”, “ Even if it is applied to a 4-value 2-bit memory such as 11 ″, the effects in the above embodiments can be obtained. Further, the present invention may be applied to a MONOS type nonvolatile memory called physical multivalue. This is a memory that stores a local charge in each of the drain end and the source end and stores the state without storing it. On the drain end side, since the drain end is depleted by the applied voltage, the cell current is not modulated by the charge accumulation at the drain end, but the cell current is modulated by the presence or absence of the charge accumulation at the source end. For this reason, information can be stored independently in the drain / source of one memory cell, but the drain side and the source side can be read out by shifting the reading location.

  For example, in FIG. 14, the left node end (source) is read in the left memory cell MC02, but the right node end (source) is read in the right memory cell MC04. . By shifting the memory cell to be read, the drain and source are reversed left and right, so that information on both sides can be read, and the MONOS type 2-bit cell is also effective in the above-described embodiment.

  In the eighth embodiment, the MONOS type nonvolatile memory has been described as an example. However, the device type is not limited as long as the memory is configured by an element whose element current is different depending on the storage state. It can be applied to non-volatile memories such as NAND type and floating gate type.

  The current or voltage measurement circuit according to the present invention has an effect of being able to measure a voltage difference or a current difference with high accuracy against noise, and can measure a voltage between two terminals of an object to be measured. It is useful as a measurement circuit, a current measurement circuit that measures current flowing into and out of the two terminals of the device under test, a sense circuit for reading information stored in a memory cell, and a semiconductor nonvolatile memory.

It is a block diagram which shows the structure of the voltage difference measuring circuit which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the sense circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the voltage waveform of the bit line in the sense circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the sense circuit which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the sense circuit which concerns on Embodiment 4 of this invention. It is a figure which shows the current waveform of the high side current monitor in the sense circuit which concerns on Embodiment 4 of this invention, and a low side current monitor. It is a block diagram which shows the structure of the sense circuit which concerns on Embodiment 5 of this invention. It is a figure which shows the voltage waveform of each bit line in the sense circuit which concerns on Embodiment 5 of this invention. It is a block diagram which shows the structure of the amplifier part in the sense circuit which concerns on Embodiment 6 of this invention. It is a block diagram which shows the structure of the amplifier part in the sense circuit which concerns on Embodiment 5 of this invention. It is the figure which showed the specific structural example of the amplifier part in the sense circuit which concerns on Embodiment 6 of this invention. It is a block diagram which shows the structure of the amplifier part in the sense circuit which concerns on Embodiment 7 of this invention. It is the figure which showed the electric current which flows in the amplifier part of the sense circuit which concerns on Embodiment 7 of this invention about each of the high side and the low side. It is a block diagram which shows the structure of the semiconductor non-volatile memory which concerns on Embodiment 8 of this invention. It is a block diagram which shows the structure of the array unit of the semiconductor non-volatile memory which concerns on Embodiment 8 of this invention. It is a block diagram which shows the structure of the reference cell array of the semiconductor non-volatile memory which concerns on Embodiment 8 of this invention. It is a block diagram which shows a part of structure of the semiconductor non-volatile memory which concerns on Embodiment 9 of this invention. It is a block diagram which shows the structure of the conventional semiconductor non-volatile memory.

Explanation of symbols

100 voltage difference measurement circuit 110 differential amplifier 120 pair wiring 120a first signal line 120b second signal line 200 sense circuit 220 pair wiring 220a / 220b bit line 230a / 230b selection transistor 240 precharge switch 250 reset switch 260 differential Amplifier 300 Sense circuit 340 Pull-up resistor 350 Pull-down resistor 400 Sense circuit 440 High-side current monitor 450 Low-side current monitor 500 Sense circuit 510 Differential amplifier 520 Pair wiring 520a First reference-side signal line 520b Second reference-side signal line 530a / 530b selection transistor 540 precharge switch 550 reset switch 600 amplifier section 610 differential amplifier 620 differential amplifier 630 differential amplifier 700 amplifier section 710 Voltage type dual differential amplifier 720 Current voltage conversion circuit 721 Resistance 722 Control Nch transistor 723 Differential amplifier 730 Current voltage conversion circuit 731 Resistance 732 Control Pch transistor 733 Differential amplifier 800 Semiconductor non-volatile memory 810 Control circuit 820 Low predecoder 830 Row decoder 840 REF row decoder 850 column decoder 860 selection line decoder 870 column selection circuit 880 precharge / reset control circuit 890 sense circuit block 891 sense circuit 892 sense circuit 1000 device under test 2000 memory cell 3000 reference cell 4000 semiconductor nonvolatile memory 4001 Y decoder 4002 Reference unit 4003 Sense amplifier ARRAY00-13 Array unit EF ARRAY Reference cell array MC01 to MC07, MC10 to MC17 Memory cell MN20, MN21 Nch transistor MN30, MN31 Nch transistor MP00, MP01 Current mirror transistors MR00 to MR07, MR10 to MR17 Reference cells MSL0 to MSL7 Select gate transistors SBL0 to SBL8 Sub Bit lines RSBL0 to RSBL8 Reference sub bit lines WL [00] to [01] Memory cell array word lines RWL [10] to [11] Reference word lines SL [00] to [07] Selection line signals RSL [00] to [07] Reference selection lines MRSL0 to MRSL7 Reference selection gate transistors MBL [0] to [3] Main bit lines RMBL [0] to [3] Arensu main bit line

Claims (17)

A voltage measurement circuit for measuring a voltage difference between a first voltage and a second voltage,
The first wiring to which the first voltage is supplied and the second wiring to which the second voltage is supplied, and the stray capacitance of the first wiring and the stray capacitance of the second wiring. And a pair wiring in which the first wiring and the second wiring are configured, so that
A differential amplifier that differentially amplifies a voltage input from the first wiring and a voltage input from the second wiring;
A voltage measuring circuit comprising: A current measuring circuit for measuring current flowing into or out of the two terminals of the device under test;
The first wiring connected to one terminal of the two terminals and the second wiring connected to the other terminal of the two terminals, and the stray capacitance of the first wiring and the second wiring A pair of wirings in which the first wiring and the second wiring are configured so that the stray capacitance of the wiring of
A differential amplifier that differentially amplifies the current flowing in the pair wiring;
A current measuring circuit comprising: A source line that is a bit line connected to the source diffusion region of the memory cell and a drain line that is a bit line connected to the drain diffusion region, and the floating capacitance of the source line and the floating capacitance of the drain line So that the source line and the drain line are configured to be substantially equivalent,
A differential amplifier that differentially amplifies the voltage at the source line and the voltage at the drain line;
A sense circuit comprising: The sense circuit of claim 3, further comprising:
A first precharge circuit for precharging the source line to a first voltage potential;
A second precharge circuit for precharging the drain line to a second voltage potential;
The sense circuit, wherein the differential amplifier is configured to differentially amplify after releasing the precharge of the source line and the drain line. The sense circuit of claim 4,
Each of the pair wiring, the differential amplifier, the first precharge circuit, and the second precharge circuit is provided for each of a reference memory cell and a read memory cell for reading data,
The sense circuit, wherein the output voltage of the read memory cell differential amplifier and the output voltage of the reference memory cell differential amplifier are differentially amplified. The sense circuit of claim 3,
And a current monitor that outputs a voltage signal according to the amount of current flowing through the source line and a voltage signal according to the amount of current flowing through the drain line,
The differential amplifier is configured to differentially amplify a signal output from the current monitor. The sense circuit of claim 6, wherein
Further, two current monitors for outputting a voltage signal corresponding to the amount of current flowing through the source line and a voltage signal corresponding to the amount of current flowing through the drain line are provided for the reference memory cell and for the read memory cell. ,
The read memory cell differential amplifier is configured to differentially amplify a signal output from the read memory cell current monitor,
The differential amplifier for a reference memory cell is configured to differentially amplify a signal output from a current monitor for a reference memory cell. A semiconductor non-volatile memory having a virtual ground array configuration,
A sense circuit according to any one of claims 4 and 6, comprising:
The second precharge circuit is configured to precharge a drain line of a memory cell adjacent to a memory cell to be read when reading from the memory cell is performed. Non-volatile memory. A semiconductor non-volatile memory having a virtual ground array configuration,
A sense circuit according to any one of claims 5 and 7, comprising:
The second precharge circuit for the read memory cell is configured to precharge the drain line of the read memory cell adjacent to the read memory cell to be read when reading from the read memory cell is performed. ,
2. The semiconductor nonvolatile memory according to claim 1, wherein the second precharge circuit for reference cells is configured to precharge a drain line of a reference memory cell adjacent to a reference memory cell to be read. A semiconductor non-volatile memory having a virtual ground array configuration,
A sense circuit according to any one of claims 4 and 6;
A first memory cell and a second memory cell configured to be read simultaneously;
A third memory cell provided between the first memory cell and the second memory cell,
In the third memory cell, when the first memory cell and the second memory cell are read simultaneously, the source line and the drain line connected to the third memory cell are precharged to the same potential. It is comprised so that the semiconductor non-volatile memory characterized by the above-mentioned. The semiconductor nonvolatile memory according to claim 10, comprising:
A semiconductor nonvolatile memory, wherein the first memory cell, the second memory cell, and the third memory cell are provided for a reference memory cell and a read memory cell, respectively. The semiconductor nonvolatile memory according to claim 11, comprising:
In addition, when the reference cell is read, each of the source lines of the reference cell to be read and other reference memory cells, and a switch for electrically connecting the drain lines, respectively,
The read reference memory cell is configured to be read simultaneously with other reference cells when reading is performed.
A semiconductor nonvolatile memory characterized in that two reference memory cells that are read simultaneously store predetermined information so that different currents flow when reading is performed. A semiconductor nonvolatile memory according to any one of claims 9 and 11, comprising:
The non-volatile semiconductor device is characterized in that the precharge voltage by the first precharge circuit for the read memory cell and the precharge voltage by the first precharge circuit for the reference cell are configured to have the same potential. memory. A semiconductor nonvolatile memory according to any one of claims 9 and 11, comprising:
A semiconductor device characterized in that the precharge voltage by the second precharge circuit for the read memory cell and the precharge voltage by the second precharge circuit for the reference cell are configured to have the same potential. Non-volatile memory. A semiconductor nonvolatile memory according to any one of claims 3 to 13,
2. The semiconductor nonvolatile memory according to claim 1, wherein the memory cell is a floating gate type memory cell. A semiconductor nonvolatile memory according to any one of claims 3 to 13,
2. The semiconductor non-volatile memory according to claim 1, wherein the memory cell is a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell. A first differential amplifier and a second differential amplifier having the same gain and different optimum input ranges;
A differential amplifier comprising: a first differential amplifier; and a third differential amplifier that differentially amplifies the output of the second differential amplifier.

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