JP2006350892A - Multi-cpu device and inter-cpu communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce communication volume among chips of a plurality of central processing units without depending on a shared RAM. <P>SOLUTION: A data storage means 23 stores data. A central processing unit 2 and another central processing unit 1 are connected to each other via a communication path 3. The central processing unit 2 transmits the data stored in the data storage means 23, via the communication path 3, to another central processing unit 1 based on data writing to the data storage means 23. When receiving notification requesting a callback from another central processing unit 1 connected via the communication path 3, the central processing unit 2 registers a task, which executes the notification, with a task storage means 23. When data is written to the data storage means 23, the central processing unit 2 transmits the written data to another central processing unit 1, and then executes the notification for the callback based on the registration in the task storage means 23. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multi-CPU device and an inter-CPU communication method.

  Patent Document 1 discloses a printer. This printer has a CPU that exclusively executes any of a plurality of “tasks” (sometimes referred to as “processes”). Specifically, for example, the CPU exclusively selects and executes tasks such as a print processing language interpretation task, a print processing task, a delay task, a print control task, and a print task.

JP 2001-1598 A (Detailed description of the invention, drawings, etc.)

  As disclosed in Patent Document 1, various computer control devices such as a printer realize a desired function by the central processing unit executing various tasks. When improving the processing capability and processing speed in such a computer control device, as one option, it is conceivable to use a plurality of central processing units and distribute the functions to the plurality of central processing units.

  However, for example, when the function of one device is to be distributed to a plurality of central processing units, there are the following problems.

  When the function of one device is realized by a plurality of central processing units, the plurality of central processing units are connected to each other through a communication path, for example. A certain central processing unit accesses data held by other central processing units based on the execution of the task. In this case, each central processing unit must frequently access the other central processing unit using the communication path every time the data held by the other central processing unit is used. It is difficult to obtain the performance improvement effect by using a plurality of central processing units as expected.

  As one method for solving such a problem, it is conceivable to use a shared RAM (Random Access Memory) that can be accessed in common by a plurality of central processing units. However, the shared RAM is more expensive than a general RAM, and processing such as exclusive control of access to the shared RAM is necessary. As a result, when a shared RAM is used, it is impossible to avoid an increase in system cost and complexity. Further, due to exclusive control of access to the shared RAM, performance degradation due to memory access latency occurs, and it becomes difficult to obtain the merit of using a plurality of central processing units.

  An object of the present invention is to obtain a multi-CPU device and an inter-CPU communication method capable of reducing inter-chip communication of a plurality of central processing units without relying on a shared RAM.

  The multi-CPU device according to the present invention is connected to a data storage means for storing data and another central processing unit through a communication path, and is stored in the data storage means based on data writing to the data storage means. And a central processing unit that transmits data to the other central processing unit via the communication path.

  If this structure is employ | adopted, the central processing unit can transmit the data memorize | stored in a data storage means to another central processing unit. Other central processing units can use the received data. As a result, the other central processing unit does not need to access the data storage unit every time the data stored in the data storage unit is used. The number of inter-chip communications by a plurality of central processing units can be reduced without relying on a shared RAM.

  In addition to the configuration of the invention described above, the multi-CPU device according to the present invention has task storage means for storing tasks to be executed by the central processing unit, and the central processing unit is connected to another central processing unit connected by a communication path. When there is a notification requesting a callback from the device, the task for executing the notification is registered in the task storage means, and when the data is written to the data storage means, the data after the writing is transmitted to another central processing unit. After that, a notification for callback is executed based on the registration of the task storage means.

  By adopting this configuration, the central processing unit can execute notification for callback to another central processing unit based on the data writing to the data storage means. Thus, the other central processing unit can execute the task using the updated data based on the callback notification.

In the multi-CPU device according to the present invention, in addition to each configuration of the above-described invention, the central processing unit notifies the callback after the completion of the processing based on the notification of the callback from another central processing unit is notified. The task to be executed is executed after the execution of the task for executing.
If this configuration is adopted, tasks executed by the central processing unit and tasks executed by other central processing units can be executed in the same order as when those tasks are executed by one central processing unit. it can.

  The inter-CPU communication method according to the present invention includes a step of writing data in the data storage means by a central processing unit connected to another central processing unit via a communication path, and a data storage means based on the data writing. Transmitting the stored data to another central processing unit.

  If this method is employed, when the data stored in the data storage means is updated by writing, it is transmitted to another central processing unit. Other central processing units can use the received data. As a result, the other central processing unit does not need to access the data storage unit every time the data stored in the data storage unit is used. The number of inter-chip communications by a plurality of central processing units can be reduced without relying on a shared RAM.

  Hereinafter, a multi-CPU device and an inter-CPU communication method according to embodiments of the present invention will be described with reference to the drawings. The inter-CPU communication method will be described as a part of the operation of the multi-CPU device.

  FIG. 1 is an apparatus configuration diagram showing a multi-CPU apparatus according to an embodiment of the present invention. The multi-CPU device has two IC chips, a front-end chip 1 and a back-end chip 2.

  The front-end chip 1 includes a central processing unit 11, a RAM 12, a storage device 13 as a data storage unit and a task storage unit, an LVDS (Low Voltage Differential Signaling) I / F 14, and a system bus 15 for connecting them, Have The back-end chip 2 includes a central processing unit 21, a RAM 22, a storage device 23 as a data storage unit and a task storage unit, an LVDSI / F 24, and a system bus 25 for connecting them.

  The LVDSSI / F 14 of the front end chip 1 is connected to the LVDSI / F 24 of the back end chip 2 by a signal line 3 as a communication path. The LVDSI / F 14, 24 outputs a differential voltage signal to the signal line 3 when data to be transmitted is supplied. The differential voltage signal may be a signal obtained by modulating a sine wave having an amplitude of about 0.9 V in accordance with transmission data, for example. The LVDSI / F 14 and 24 receive the differential voltage signal from the signal line 3. The LVDSI / F 14, 24 generates reception data from the received differential voltage signal.

  The storage device 13 of the front-end chip 1 includes a front-end AP (application) program 31, an RTOS (real-time operating system) bridge program 32, an RTOS program 33, a communication protocol handler program 34, and an I / O (Input / Output). ) The driver program 35 is stored.

  The storage device 23 of the back-end chip 2 stores a back-end AP program 41, an RTOS bridge program 42, an RTOS program 43, a communication protocol handler program 44, and an I / O driver program 45.

  The central processing unit 11 of the front end chip 1 implements various functions by reading these programs stored in the storage device 13 into the RAM 12 and executing them. The central processing unit 21 of the back-end chip 2 implements various functions by reading these programs stored in the storage device 23 into the RAM 22 and executing them.

  FIG. 2 is a diagram showing a stack structure of functions realized in the multi-CPU device of FIG.

  Specifically, the central processing unit 11 of the front-end chip 1 implements the front-end AP unit 51 by reading the front-end AP program 31 into the RAM 12 and executing it. The central processing unit 11 implements the RTOS bridge unit 52 by reading the RTOS bridge program 32 into the RAM 12 and executing it. The central processing unit 11 implements the RTOS unit 53 by reading the RTOS program 33 into the RAM 12 and executing it. The central processing unit 11 implements the communication protocol handler unit 54 by reading the communication protocol handler program 34 into the RAM 12 and executing it. The central processing unit 11 implements the I / O driver unit 55 by reading the I / O driver program 35 into the RAM 12 and executing it.

  Specifically, the central processing unit 21 of the back-end chip 2 implements the back-end AP unit 61 by reading the back-end AP program 41 into the RAM 22 and executing it. The central processing unit 21 implements the RTOS bridge unit 62 by reading the RTOS bridge program 42 into the RAM 22 and executing it. The central processing unit 21 implements the RTOS unit 63 by reading the RTOS program 43 into the RAM 22 and executing it. The central processing unit 21 implements the communication protocol handler unit 64 by reading the communication protocol handler program 44 into the RAM 22 and executing it. The central processing unit 21 implements the I / O driver unit 65 by reading the I / O driver program 45 into the RAM 22 and executing it.

  The I / O driver units 55 and 65 supply transmission data to the LVDSI / F 14 and 24. The I / O driver units 55 and 65 are supplied with received data from the LVDSI / F 14 and 24.

  When the data to be transmitted is supplied, the communication protocol handlers 54 and 64 generate transmission data for transmission according to a predetermined communication protocol using the data as original data. The communication protocol handler units 54 and 64 supply the generated transmission data to the I / O driver units 55 and 65. When the received data is supplied from the I / O driver units 55 and 65, the communication protocol handler units 54 and 64 process the data according to a predetermined communication protocol to generate original data.

  The RTOS units 53 and 63 manage the execution of programs by the central processing units 11 and 21. The central processing units 11 and 21 generate tasks by executing the various programs described above. When the RTOS is used, the various programs described above are generally described as a collection of a plurality of functions. A function corresponds to a function, for example. The central processing units 11 and 21 generate a task for each function, for example.

  The task management state includes an execution state, an executable state, a waiting state, and a hibernation state. The task execution state is a state in which the task is currently being executed by the central processing units 11 and 21. The task executable state is a state where the task side is ready for execution but is not being executed by the central processing units 11 and 21. When there are a plurality of tasks in the executable state, when the execution of the tasks in the execution state ends, the central processing units 11 and 21 execute the task having the highest priority among the tasks in the executable state. The task wait state is a state where the task side is not ready for execution. For example, the task is waiting for the event flag to be cleared. The task dormant state is a state in which the task is not activated. When a general task is newly created, it first enters this state.

  The RTOS units 53 and 63 manage the state of tasks generated by the central processing units 11 and 21 based on programs. For example, the RTOS units 53 and 63 make a task in a waiting state or a task in a dormant state executable. When the execution of the task in the execution state is completed, the RTOS units 53 and 63 select a task having a higher priority from the tasks in the executable state as a task to be executed next. The central processing units 11 and 21 execute the task selected by the RTOS units 53 and 63. The RTOS units 53 and 63 put unnecessary tasks that have been executed into a dormant state.

  The RTOS units 53 and 63 have an inter-task communication function. Examples of the inter-task communication function include an inter-task message and an event flag. By using the inter-task communication function, a certain task (hereinafter referred to as “task A”) may supply data to another task (hereinafter referred to as “task B”) or notify the status of the task. it can.

  When the inter-task message is used, for example, the RTOS unit 53 writes the parameter data delivered to the task B as a parameter block in the memory space of the RAM 12. The RTOS unit 53 generates an inter-task message using information such as the top address information of the parameter block as a parameter. The RTOS unit 53 supplies the generated inter-task message to the task B. When executing the task B, the central processing unit 11 reads the parameter data from the head address specified by the inter-task message. The central processing unit 11 executes the task B using the read parameter data.

  Note that the supply source task notifies the information of the head address of the parameter block as the content of the inter-task message to the supply destination task. The parameter block data itself is not supplied by the inter-task message. For this reason, the supply source task can supply an arbitrary amount of data to the supply destination task by using the inter-task message.

  As described above, when the central processing units 11 and 21 executing RTOS execute a program, they generate a task based on the program, and execute the generated task in a predetermined order. Further, the central processing units 11 and 21 that execute RTOS supply necessary data between tasks by using an inter-task message or the like. As a result, the central processing units 11 and 21 execute the program, thereby realizing the functions encoded in the program.

  The RTOS units 53 and 63 have interrupt handler units 57 and 67, respectively.

  The interrupt handler units 57 and 67 execute an interrupt process when the central processing unit 11 or 21 has an interrupt request. For example, there is an LVDSI / F14, 24 as an interrupt request to the central processing unit 11, 21. When there is an interrupt request from the LVDS / F 14, 24, the interrupt handler units 57, 67 use the communication protocol handler units 54, 64 and the I / O driver units 55, 65 to transfer data from the LVDS / F 14, 24. get.

  The RTOS units 53 and 63 and the interrupt handler units 57 and 67 are also realized by the central processing units 11 and 21 executing the RTOS programs 33 and 43. Therefore, it is executed as a task by the central processing units 11 and 21. However, the tasks of the RTOS units 53 and 63 are generally executed by the central processing units 11 and 21 as tasks having higher priority than other tasks based on other programs.

  Further, the interrupt handler units 57 and 67 are described as a set of functions in the RTOS programs 33 and 43 in the same manner as other functions by the RTOS programs 33 and 43. The RTOS units 53 and 63 have a function called a system call for directly or indirectly calling the interrupt handler units 57 and 67 from a program outside the RTOS units 53 and 63.

  The RTOS bridge units 52 and 62 provide an API (application program interface) that is insufficient for system calls to the front-end AP unit 51 or the back-end AP unit 61. The RTOS bridge units 52 and 62 provide a new function that is not defined by the RTOS units 53 and 63, and is used specifically in a device in which a multi-CPU device is incorporated. This function is a function that can be called from a program external to the RTOS bridge units 52 and 62, such as the front-end AP program 31.

  The RTOS bridge units 52 and 62 include DSM (Default Setting status Manager) units 58 and 68. The DSM units 58 and 68 manage task execution. The DSM units 58 and 68 have task registration data 60 and 70 and status setting data 59 and 69. The task registration data 60 and 70 and the status setting data 59 and 69 are stored in the storage devices 13 and 23 as data storage means and task storage means. The task registration data 60 and 70 and the status setting data 59 and 69 may be stored in the RAMs 12 and 22.

  As shown in FIG. 5, which will be described later, the task registration data 60, 70 has a plurality of task management numbers. In the task registration data 60 and 70, a task management block 71 executed by the central processing units 11 and 21 is registered for each task management number. The task management block 71 includes, for example, the top addresses of the storage devices 13 and 23 in which the execution program corresponding to the task is stored, the execution status setting data of the task, and the like. A plurality of task management blocks 71 can be registered in each task management number. When a plurality of task management blocks 71 are registered in one task management number, for example, tasks are executed in the registration order.

  The status setting data 59 and 69 include, for example, task status data and setting data registered in the task registration data 60 and 70.

  For example, when a task registration request is issued by a callback function registration message or the like, the DSM units 58 and 68 register the task management block 71 of the requested task in the task registration data 60 and 70, and relate to the requested task. Status data, setting data, and the like are registered in the status setting data 59 and 69 together with initial values. Thereafter, the DSM units 58 and 68 generate a necessary message structure based on the callback function registration message or the like.

  FIG. 3 is an explanatory diagram showing the data structure of the message structure generated by the DSM units 58 and 68. The message structure shown in FIG. 3 is generated by the DSM units 58 and 68 when a new callback function is registered, and requests a callback notification. The message structure has a plurality of parameters. In the message structure of FIG. 3, as parameter data, data notifying that a callback function is newly registered, data of a task management number (“1” in FIG. 3) in which the callback function is registered, and CPU The data of the number (“1” in FIG. 3) is included. The CPU number is an identification number assigned to each central processing unit in the multi-CPU device. In this embodiment, the following description will be made assuming that the CPU number “1” is assigned to the front end chip 1 and the CPU number “2” is assigned to the back end chip 2.

  The front-end AP unit 51 and the back-end AP unit 61 realize functions required for a device in which a multi-CPU device is incorporated. For example, when two functions of function A and function B are required in a device in which a multi-CPU device is incorporated, function A is realized as a task of the front-end AP unit 51, and function B is performed as a task of the back-end AP unit 61. Realized.

  In the front-end AP unit 51 and the back-end AP unit 61, functional tasks are generated by the RTOS units 53 and 63 for each function or for each function obtained by further subdividing the function. The execution of this functional task is managed by the RTOS units 53 and 63. The function task uses functions as an API provided by the RTOS units 53 and 63 and the RTOS bridge units 52 and 62, and performs inter-task communication using inter-task messages.

  Next, the operation of the multi-CPU device according to the embodiment having the above configuration will be described.

  FIG. 4 is a diagram showing a sequence when the task A of the front-end AP unit 51 executed by the front-end chip 1 is a so-called callback function task. That is, the task A executes processing based on the write processing to the status setting data 69 by the task B of the back-end AP unit 61 executed by the back-end chip 2.

  In this case, the central processing unit 21 of the back end chip 2 corresponds to a central processing unit, and the central processing unit 11 of the front end chip 1 corresponds to another central processing unit.

  When the callback function registration message for the task A executed by the front end chip 1 is supplied (step ST1), the DSM unit 58 of the front end chip 1 uses the task A information as the task registration of the front end chip 1. Data 60 and status setting data 59 are registered (step ST2). In FIG. 4, the callback function registration message for the task A is generated by the task A itself. However, for example, the callback function registration message is a task A executed by the front end chip 1. It may be generated by a task other than

  FIG. 5 shows the task registration data 60 of the front end chip 1 and the task registration data 70 of the back end chip 2 immediately before the task management block 71 of task A is registered in the task registration data 60 of the front end chip 1. FIG. Each of the task registration data 60 and 70 has (n + 1) task management numbers from 0 to n. The task management block 71 of task B is registered in the task management number “1” of the task registration data 70 of the back-end chip 2.

  FIG. 6 shows the task registration data 60 of the front end chip 1 and the task registration data 70 of the back end chip 2 immediately after the task management block 71 of task A is registered in the task registration data 60 of the front end chip 1. FIG. In FIG. 6, the task management block 71 of task A is registered in the task registration data 60 of the front-end chip 1 with the task management number “1”.

  After registering the task management block 71 of the task A, which is a callback function, in the task registration data 60, the DSM unit 58 calls back the task A waiting for the callback notification from the task executed in the front end chip 1. It is determined whether it is waiting for notification or waiting for callback notification from a task executed by the back-end chip 2 (step ST3). Note that the DSM unit 58 has, for example, a list of tasks to be executed by the front-end chip 1, and by confirming that the task of the callback notification source is not included in the list, the callback notification source It may be determined that these tasks are not tasks executed by the front-end chip 1.

  When the callback notification source task B is not a task executed by the front end chip 1, the DSM unit 58 generates a message structure for requesting the callback notification. As shown in FIG. 3, the message structure for requesting the callback notification includes, as its parameters, data for notifying that the callback function task A is registered, and the task management number for which the callback function task A is registered. “1”, CPU number “1”, and the like are included.

  The DSM unit 58 supplies the generated message structure to the communication protocol handler unit 54 as shown in FIG. The communication protocol handler unit 54 of the front end chip 1 generates transmission data for transmitting the supplied message structure by a predetermined communication protocol, and supplies it to the I / O driver unit 55. The I / O driver unit 55 of the front end chip 1 supplies transmission data to the LVDSI / F 14. The LVDSI / F 14 of the front end chip 1 outputs a differential voltage signal corresponding to the data to be transmitted to the signal line 3.

  The differential voltage signal output from the LVDSSI / F 14 of the front end chip 1 is received by the LVDSI / F 24 of the back end chip 2. The LVDSSI / F 24 of the back end chip 2 outputs an interrupt request to the central processing unit 21 of the back end chip 2.

  When there is an interrupt request in the central processing unit 21 of the back-end chip 2, the interrupt handler unit 67 of the back-end chip 2 executes an interrupt process. The interrupt handler unit 67 acquires data from the LVDSI / F 24 using the communication protocol handler unit 64 and the I / O driver unit 65. When the reception data is supplied from the LVDSI / F 24, the I / O driver unit 65 of the back-end chip 2 supplies this to the communication protocol handler unit 64. The communication protocol handler unit 64 supplies the received data to the interrupt handler unit 67.

  As a result, the DSM unit 58 of the front-end chip 1 transmits a message structure requesting a callback notification to the interrupt handler unit 67 of the back-end chip 2 (step ST4).

  The interrupt handler unit 67 that has received the message structure analyzes the contents of the message structure. If the message structure is a request for callback notification, the DSM unit 68 of the back-end chip 2 is specified as the transmission destination of the message structure. The interrupt handler unit 67 generates a callback function registration message based on the parameters of the message structure and supplies it to the DSM unit 68 (step ST5). The callback function registration message includes, for example, a task management number “1” in which the callback function is registered, a CPU number “1”, and the like as information included in the message structure.

  When the callback function registration message is supplied from the interrupt handler unit 67, the DSM unit 68 of the back-end chip 2 stores the callback in the task registration data 70 of the back-end chip 2 based on the callback function registration message. The task management block 71 of the task that executes the notification is additionally registered (step ST6).

  FIG. 7 is a diagram showing a state when the DSM unit 68 of the back-end chip 2 additionally registers the task management block 71 of the task for executing the callback notification to the front-end chip 1 in the task registration data 70. In the task management number “1” of the task registration data 70 of the back-end chip 2, the task management block 71 of the task that executes the callback notification is registered after the task management block 71 of the task B. The task management block 71 of the task that executes the callback notification includes the CPU number “CPU1 (CPU number of the front end chip 1)” in which the callback destination task (task A in this case) is executed, and the task management number “01”. (The number at which task A is registered) "is registered.

  In the state where the task management block 71 of the task for executing the callback notification is additionally registered in the task registration data 70 of the back-end chip 2, for example, the central processing unit 21 of the back-end chip 2 has the task management number “1”. Task B is executed.

  FIG. 8 is a diagram showing a state in which the task management block 71 of task C is registered in the task registration data 70 of the back-end chip 2. The task management block 71 of task C is registered in the task registration data 70 as task B is executed, for example.

  Further, by executing task B, the central processing unit 21 makes a write access (write access) to the status setting data 69 by a write message. The DSM unit 68 writes the data designated by the Write message in the status setting data 69 (step ST7).

  When the status setting data 69 is updated by the Write message, the DSM unit 68 of the back-end chip 2 starts a synchronization process of the status setting data 69 (step ST8). Specifically, the DSM unit 68 of the back-end chip 2 transmits the status setting data 69 managed by the DSM unit 68 to the DSM unit 58 of the front-end chip 1.

  Specifically, the status setting data 69 managed by the DSM unit 68 of the back-end chip 2 includes the communication protocol handler unit 64, the I / O driver unit 65, the LVDSI / F 24, the signal line 3, and the front-end of the back-end chip 2. The data is transmitted to the DSM unit 58 of the front-end chip 1 via the LVDSI / F 14 of the chip 1, the I / O driver unit 55, the communication protocol handler unit 54 and the interrupt handler unit 57.

  When the DSM unit 58 of the front end chip 1 receives the status setting data 69 from the DSM unit 68 of the back end chip 2, it updates its own status setting data 59 with the received status setting data 69. As a result, the content of the status setting data 59 of the front end chip 1 matches the content of the status setting data 69 of the back end chip 2. The status setting data 59 and 69 are synchronized.

  When the synchronization processing of the status setting data 69 is completed, the DSM unit 68 of the backend chip 2 determines whether or not a callback notification to the frontend chip 1 is necessary (step ST9). Specifically, in the DSM unit 68, the task management block 71 registered next to the task management block 71 of the task B in the task registration data 70 performs a task task for executing a callback notification to the front-end chip 1. It is determined whether it is the management block 71 or not. In FIG. 8, the task management block 71 of the task that notifies the task A of the callback is registered after the task management block 71 of the task B.

  If it is determined that the callback notification is necessary based on the task registration data 70, the DSM unit 68 of the backend chip 2 registers the task management block 71 next to the task B after the execution of the task B is completed. Execute the existing task and generate a message structure for callback notification. The message structure for the callback notification includes the task management number “01”, the CPU number “CPU1”, and the like of the callback notification destination registered in the task registration data 70.

  FIG. 9 is a diagram illustrating a state when a callback notification is executed from the back-end chip 2 to the front-end chip 1. The central processing unit 21 of the back-end chip 2 executes a task based on the task management block 71 registered in the task management number “1”, and executes a callback notification using a message structure.

  The DSM unit 68 transmits the generated message structure to the interrupt handler unit 57 of the front end chip 1 (step ST10). Specifically, the message structure for the callback notification includes the communication protocol handler unit 64 of the back end chip 2, the I / O driver unit 65, the LVDSI / F unit 24, the signal line 3, and the LVDSI of the front end chip 1. / F14, the I / O driver unit 55, and the communication protocol handler unit 54 to be transmitted to the interrupt handler unit 57.

  Further, after transmitting the generated message structure, the DSM unit 68 prohibits (locks) the execution of the task management number in which the task management block 71 of the task that has notified the callback is registered (step ST11).

  When the message structure for the callback notification is supplied, the interrupt handler unit 57 generates a Write message including the task management number “1” and supplies it to the DSM unit 58 (step ST12).

  When the Write message is supplied, the DSM unit 58 of the front-end chip 1 supplies a callback notification message to the task A (step ST13). The central processing unit 11 of the front-end chip 1 executes task A (step ST14).

  Through the series of processes described above, the central processing unit 11 of the front end chip 1 can execute the task A of the callback function by the callback notification from the task B executed by the back end chip 2. Further, since the status setting data 59 of the front end chip 1 is synchronously processed before executing the callback function task, the front end chip 1 stores the status setting data 59 that has been synchronously processed after the update. Can access and properly execute task A of the callback function.

  When the execution of the task A as the callback function task is completed (step ST15), the DSM unit 58 of the front-end chip 1 executes the execution of the task A based on the callback notification from the back-end chip 2. It is determined whether it has been done (step ST16). If the DSM unit 58 determines that the task A is executed based on the callback notification from the back-end chip 2 when the task A is executed based on the Write message from the interrupt handler unit 57, for example. Good.

  If it is determined that the task A has been executed based on the callback notification from the back-end chip 2, the DSM unit 58 of the front-end chip 1 generates a message structure of the callback execution completion notification and allocates the back-end chip 2. This is transmitted to the embedded handler section 67 (step ST17). Based on this message structure, the interrupt handler unit 67 supplies a callback execution completion notification message to the DSM unit 68 (step ST18).

  FIG. 10 is a diagram showing the state of the task registration data 60 and 70 when the callback execution completion notification is executed from the front end chip 1 to the back end chip 2.

  When the callback execution completion notification message is supplied from the interrupt handler unit 67, the DSM unit 68 releases the lock of the task management number in which the task management block 71 of the task that has notified the callback is registered (step ST19). ), The task C of the task management block 71 registered after the task management block 71 of the task of the callback notification in the task registration data 70 is executed.

  As a result, the task A, which is a callback function, is executed in the front-end chip 1, and the back-end chip 2 can execute the task C after waiting for completion of the execution. The front-end chip 1 and the back-end chip 2 can execute a plurality of tasks executed by them in the same order as when executed by one central processing unit.

  In the above description, the case where the status setting data 69 and the message structure for callback notification are transmitted from the task B of the backend chip 2 to the task A of the frontend chip 1 will be described with reference to FIG. is doing. Conversely, status setting data 59 and a message structure for callback notification can be transmitted from the task of the front end chip 1 to the task of the back end chip 2 by the same operation sequence as in FIG.

  Next, a printer multifunction peripheral will be described as an example of an embedded device incorporating the multi-CPU device of FIG.

  FIG. 11 is a diagram illustrating an example of functional separation between the front-end AP unit 51 and the back-end AP unit 61 when the multi-CPU device illustrated in FIG. 1 is applied to a printer multifunction peripheral. The multifunction printer is connected to a computer (not shown) and prints an image based on a print instruction from the computer. In addition to the image file stored in a semiconductor memory such as a flash memory (not shown) attached to the printer And a function for printing an image read by a scanner (not shown).

  The central processing unit of the multifunction printer basically executes the application program, so that the file system management unit 81, user interface unit 82, file list management unit 83, image decoding unit 84, image layout unit 85, binary It is necessary to realize the conversion processing unit 86, the interlace processing unit 87, the data processing controller unit 88, the card print function unit 89, and the like.

  The file system management unit 81 manages image files (not shown) of the multifunction printer. The image file of the printer multifunction device is an image file stored in a semiconductor memory mounted on the printer multifunction device, for example.

  The user interface unit 82 controls an input device and a display device (not shown) of the printer multifunction peripheral. The user interface unit 82 selects an image to be printed by a user operation, and selects a sheet and a layout for printing the image.

  The file list management unit 83 holds the print setting information selected by the user interface unit 82. The print setting information includes, for example, the file name of the selected image file, the size and layout of the paper to be printed, and printing conditions such as whether image correction processing is necessary.

  The image decoding unit 84 reads image file data to be printed, and generates image data based on the read data.

  The image layout unit 85 reads the print setting information held by the file list management unit 83 and generates data for each sheet. The image layout unit 85 specifies a print range of the paper based on the read print setting information, and generates print image data in which an image to be printed within the print range is laid out.

  The binarization processing unit 86 converts the print image data generated by the image layout unit 85 into binarized data.

  The interlace processing unit 87 rearranges the binarized data generated by the binarization processing unit 86 in the order in which the print engine 90 prints, inserts necessary control codes, and generates print control data. The print control data generated by the interlace processing unit 87 is supplied to the print engine 90. The print engine 90 executes printing on a sheet based on the print control data.

  The data processing controller unit 88 manages and controls the data flow among the image layout unit 85, the image decoding unit 84, the binarization processing unit 86, and the interlace processing unit 87. For example, the binarized data generated by the binarization processing unit 86 is supplied to the interlace processing unit 87. The data processing controller unit 88 manages the flow of data such as the binarized data. In the case of binarized data, the binarization processing unit 86 supplies the generated binarized data to the data processing controller unit 88. The data processing controller unit 88 supplies the supplied binarized data to the interlace processing unit 87. By managing and controlling the data flow in this way, the data processing controller unit 88 can centrally manage up to which process of the printing process has been completed.

  The card print function unit 89 sets data flow control (continuous job start-up and cancellation processing) and operation conditions in the data processing controller unit 88, and acquires printing progress status information from the data processing controller unit 88. Or

  In the printer multifunction machine shown in FIG. 11, these basic functions based on the printer application program are executed by the front end chip 1 and the back end chip 2 in a distributed manner. Specifically, the front end AP unit 51 includes a file system management unit 81, a user interface unit 82, a file list management unit 83, and a card print function unit 89. The back-end AP unit 61 includes an image decoding unit 84, an image layout unit 85, a binarization processing unit 86, an interlace processing unit 87, and a data processing controller unit 88.

  For this reason, in the multifunction printer of FIG. 11, the file list management unit 83 retains information relating to printing such as an image or paper selected by the user interface unit 82 as print setting information and transmits it to the image layout unit 85. The image layout unit 85 determines a print layout and the like based on the information and information on the image acquired from the file system management unit 81. Further, the image decoding unit 84 acquires image data of an image to be printed from the file system management unit 81. The image layout unit 85 generates a print image having a paper size in which the image decoded by the image decoding unit 84 is allocated according to the print layout. The binarization processing unit 86 converts the print image data into binarized data. The interlace processing unit 87 generates print control data from the binarized data. The print engine 90 executes printing on a sheet based on the print control data.

  11, both the front end chip 1 and the back end chip 2 include interrupt handler sections 57 and 67 of the RTOS sections 53 and 63, and DSM sections 58 and 68 of the RTOS bridge sections 52 and 62. Have The above-described functions of the multifunction printer are executed in units of tasks, and data is transmitted / received to / from each other by an inter-task communication function using a message structure or the like.

  For example, the file system management unit 81 may wish to divide and transmit image data by a predetermined amount of data. In this case, a callback notification function may be used.

  Specifically, when the file system management unit 81 transmits a predetermined amount of data to the back-end chip 2, the DSM unit 58 of the front-end chip 1 transmits a message structure that requests a callback notification to the back-end chip 2. Send to. The DSM unit 68 of the back-end chip 2 transmits a callback notification to the front-end chip 1 when the image layout unit 85 and the image decoding unit 84 complete the processing for the predetermined amount of data.

  Accordingly, the file system management unit 81, the image layout unit 85, and the image decoding unit 84 can appropriately execute the respective processes while synchronizing the processes with each other.

  As described above, the front end chip 1 and the back end chip 2 operate in cooperation with each other in the printer multi-function apparatus of FIG. Can be executed.

  As described above, in this embodiment, when the front-end chip 1 and the back-end chip 2 have write access to the status setting data 59 and 69 stored in the storage devices 13 and 23, the write update The subsequent status setting data 59 and 69 are transmitted and received. Therefore, the central processing unit 11 of the front-end chip 1 and the central processing unit 21 of the back-end chip 2 access the status setting data 59 and 69 stored in the respective storage devices 13 and 23 to perform predetermined processing. Can be executed. The central processing units 11 and 21 do not need to access the storage devices 13 and 23 of the other chip every time data is used. Further, the number of inter-chip communications by the two central processing units 11 and 21 can be reduced without relying on the shared RAM.

  In this embodiment, the central processing unit 11 of the front-end chip 1 and the central processing unit 21 of the back-end chip 2 mutually call back based on write access to the status setting data 59 and 69 of the storage devices 13 and 23. Send and receive message structures for notification. Thereby, the central processing units 11 and 21 can execute a task for requesting the callback notification based on the callback notification and using the status setting data 59 and 69 updated by the synchronization processing.

  In this embodiment, the central processing unit 11 of the front-end chip 1 and the central processing unit 21 of the back-end chip 2 execute a task based on the callback notification and then notify the completion of the callback execution. Send and receive body. Therefore, the tasks executed by the two central processing units 11 and 21 are executed in the same order as when those tasks are executed by one central processing unit.

  Further, the task of the front-end AP unit 51 of the front-end chip 1 and the task of the back-end AP unit 61 of the back-end chip 2 send and receive data and messages to each other using APIs provided to them. Therefore, the status setting data and message structure transmission / reception processing between the front-end chip 1 and the back-end chip 2 are hidden in the operation of transmitting and receiving messages between tasks. Therefore, as the front-end AP unit 51 and the back-end AP unit 61, a program that operates on a central processing unit that uses one memory space can be used. Software assets running on a central processing unit that uses one memory space can be diverted.

  As a result, the front-end AP unit 51 and the back-end AP unit 61 can be easily realized by using a program that realizes a plurality of functional tasks operable on one central processing unit by sending and receiving messages between tasks. A plurality of functional tasks operating on the multi-CPU device can be easily realized. Further, the front-end AP unit 51 and the back-end AP unit 61 can send and receive data and instructions without using a shared RAM that can be accessed by both the front-end chip 1 and the back-end chip 2.

  In addition, interrupt processing is used for sending and receiving messages between tasks between the front-end chip 1 and the back-end chip 2. Therefore, a general-purpose central processing unit having an interrupt processing function can be used as the front end chip 1 and the back end chip 2.

  The above embodiment is an example of a preferred embodiment of the present invention, but the present invention is not limited to this, and various modifications and changes can be made without departing from the scope of the invention. is there.

  In the above embodiment, the front end chip 1 and the back end chip 2 have the LVDSI / F 14, 24, and transmit and receive data using differential voltage signals. In addition to this, for example, the front-end chip 1 and the back-end chip 2 have a TTL (Transistor-Transistor Logic) I / F, and transmit and receive data using a TTL signal having a voltage of 0 to 5 V. Also good.

  In the above embodiment, the front-end chip 1 and the back-end chip 2 transmit and receive the contents of the inter-task message using the message structure illustrated in FIG. In addition, for example, the front-end chip 1 and the back-end chip 2 may send and receive intertask messages themselves. In the above embodiment, the contents of the inter-task message are transmitted / received by the message structure. In addition to this, for example, the information used for the so-called inter-task communication function such as the contents of the event flag is transmitted / received by the message structure. May be. Even in this case, the update of the status setting data 59 and 69 can be used as the data change timing, and the task can be executed using the data change timing as a trigger.

  In the above embodiment, the DSM unit 58 of the front-end chip 1 and the DSM unit 68 of the back-end chip 2 register the task management block 71 of the task that executes callback notification in the task registration data 60 and 70, Thereafter, a callback notification is executed based on the presence or absence of the registration. In addition to this, for example, the DSM units 58 and 68 provide, for example, a callback function presence / absence table different from the task registration data 60 and 70, and register a callback notification request in the callback function presence / absence table. You may make it perform callback notification based on the presence or absence of registration.

  In the above embodiment, the multi-CPU device is constituted by two IC chips, the front end chip 1 and the back end chip 2. In addition to this, for example, the multi-CPU device may be configured by three or more IC chips. The CPU unit having the central processing unit and the RAM may be an IC chip in which a plurality of sets are mounted in one IC chip. Furthermore, the multi-CPU device may be configured by an IC chip having a plurality of sets of CPU units and another IC chip.

  In the above-described embodiment, the case where the multi-CPU device is applied to a printer multifunction device is illustrated. In addition, for example, the multi-CPU device may be applied to a printer, a scanner, a digital camera, a projector, a mobile phone terminal, and other embedded devices that operate under computer control.

  The present invention can be used in a multifunction printer, a printer, a scanner, a digital camera, a projector, a mobile phone terminal, and other embedded devices that operate under computer control.

1 is a device configuration diagram showing a multi-CPU device according to an embodiment of the present invention. It is a figure which shows the stack structure of the function implement | achieved by the multi CPU apparatus of FIG. It is explanatory drawing which shows the data structure of the message structure which a DSM part produces | generates. It is a sequence diagram which shows the flow of a callback process. This is an initial state of the task registration data before registration of the callback function task A. The callback function task A is registered in the task registration data. This is a state in which a callback notification task to task A is registered. Task C is registered after the callback notification task. This is the state of the task registration data at the time of callback notification. This is the state of the task registration data at the time of callback execution completion notification. This is an example in which the multi-CPU device shown in FIG. 1 is applied to a multifunction printer.

Explanation of symbols

  3 Signal line (communication path), 11, 21 Central processing unit (central processing unit and other central processing units), 13, 23 Storage device (data storage unit, task storage unit), 59, 69 Status setting data (data) , 60, 70 Task registration data

Claims (4)

Data storage means for storing data;
Another central processing unit is connected via the communication path, and the data stored in the data storage unit is transferred to the other central processing unit via the communication path based on the data writing to the data storage unit. A central processing unit to transmit to,
A multi-CPU device comprising: Task storage means for storing a task to be executed by the central processing unit;
When there is a notification requesting a callback from the other central processing unit connected by the communication path, the central processing unit registers a task for executing the notification in the task storage unit, and sends it to the data storage unit. If there is a data write of, after sending the data after the write to the other central processing unit, executing notification for the callback based on the registration of the task storage means,
The multi-CPU device according to claim 1.   The central processing unit executes a task to be executed after execution of the task for executing the callback notification after the completion of the processing based on the callback notification from the other central processing unit is notified. The multi-CPU device according to claim 1, wherein: Writing data into the data storage means by a central processing unit connected to another central processing unit via a communication path;
Transmitting the data stored in the data storage means to another central processing unit based on the writing of the data;
A communication method between CPUs, comprising:

Images