JP2006345577A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set an output buffer circuit at output high impedance state without fail even when one of two power supplies of a semiconductor device is cut off. <P>SOLUTION: In an output circuit, a latch circuit composed of inverter circuits (2, 5) and MOS transistors (3, 6) is arranged in the next stage to gate circuits (1, 4) which accept a power supply voltage related to a 1st power supply voltage (EXVDD) as an operating power supply voltage, and a 2nd power supply voltage (VDDQ) is given as an operating power supply voltage for the latch circuit. An output buffer circuit (912) is driven according to the output of the latch circuit. Even when the 1st power supply voltage is cut off, a signal voltage in the stand-by state is held by the latch circuit which receives the 2nd power supply voltage as the operating power supply voltage, so the output buffer circuit can be kept in an output high impedance state without failure. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a configuration of an output circuit that drives an external bus signal line in accordance with an internal signal. More specifically, the present invention relates to a configuration of a signal output unit of a semiconductor device to which an output power supply voltage for signal output and an external power supply voltage for driving an internal circuit are separately applied.

  FIG. 11 is a diagram schematically showing a configuration of a main part of a conventional semiconductor device. The semiconductor device 900 includes an internal power supply circuit 901 that generates various internal voltages from an external power supply voltage EXVDD, a memory circuit 902 that operates according to various internal voltages from the internal power supply circuit 901, and an output power supply voltage VDDQ from the outside. It includes an output circuit 903 that receives the voltage and buffers the data read from the memory circuit 902 and outputs it to the outside.

  The internal power supply circuit 901 generates an internal power supply voltage voltage, an intermediate voltage, a reference voltage, and the like that are used as an operation power supply voltage in the memory circuit 902. However, in order to simplify the drawing, FIG. 11 representatively shows the peripheral power supply voltage VDDP generated by the internal power supply circuit 901. Usually, external power supply voltage EXVDD is 2.5 V or more, for example, and output power supply voltage VDDQ is 1.8 V, for example. When the external power supply voltage EXVDD is 2, 5V, the external power supply voltage EXVDD is used as the peripheral power supply voltage VDDP. In this case, the array power supply voltage used in the memory cell array included in memory circuit 902 is generated by stepping down external power supply voltage EXVDD. Here, in order to distinguish between the peripheral power supply voltage VDDP and the external power supply voltage EXVDD, the peripheral power supply voltage VDDP is shown.

  Memory circuit 902 includes a memory cell array, a row and column selection circuit for selecting a memory cell of the memory cell array, an internal data read circuit, and the like.

  Even if the output power supply voltage VDDQ fluctuates during the operation of the output circuit 903, the memory circuit 902 generates the internal power supply voltage generated from the external power supply voltage EXVDD by giving the output power supply voltage VDDQ exclusively to the output circuit 903. It can be stably operated according to VDDP or the like. Therefore, even when multi-bit data DQ is generated, the memory circuit 902 can be stably operated without being affected by fluctuations in the output power supply voltage VDDQ.

  Further, by giving the output power supply voltage VDDQ exclusively to the output circuit 903, the operation power supply voltage can be supplied to the output circuit 903 with a margin, and the output circuit 903 can be operated stably. .

  FIG. 12 is a diagram schematically showing a configuration of a portion related to 1-bit data output of the output circuit 903. 12, an output circuit 903 includes a NAND circuit 906 that receives internal read data RD and output permission signal OEM read from internal read circuit 905 included in memory circuit 902, internal read data RD and output permission signal OEM, Receiving gate circuit 907, level conversion circuit 908 for converting the amplitude of the output signal of NAND circuit 906 into output power supply voltage VDDQ level, and level conversion for converting the amplitude of the output signal of gate circuit 907 into external power supply voltage EXVDD level Circuit 909, inverter circuit 910 for inverting the output signal of level conversion circuit 909, and output buffer circuit 912 for driving output node 920 in accordance with the output signal of level conversion circuit 908 and the output signal of inverter 910.

  Internal read circuit 905 is included in memory circuit 902 shown in FIG. 11, and includes, for example, a preamplifier circuit, etc., receives peripheral power supply voltage VDDP as an operation power supply voltage, and generates internal read data RD having an amplitude of peripheral power supply voltage VDDP level. .

  NAND circuit 906 and gate circuit 907 receive peripheral power supply voltage VDDP as an operating power supply voltage. NAND circuit 906 outputs an H level signal when output permission signal OEM is at L level, and operates as an inverter when output permission signal OEM is at H level, and inverts internal read data RD.

  Gate circuit 907 outputs an H level signal when output permission signal OEM is at L level, and operates as a buffer circuit when output permission signal OEM is at H level, and generates an output signal in accordance with internal read data RD.

  Level conversion circuit 908 receives output power supply voltage VDDQ as an operation power supply voltage, and level conversion circuit 909 receives external power supply voltage EXVDD as an operation power supply voltage.

  These level conversion circuits 908 and 909 merely perform level (amplitude) conversion, and do not perform logical level conversion.

  Output buffer circuit 912 is connected between an output power supply node and output node 920 and receives at its gate an output signal of level conversion circuit 908 P channel MOS transistor (insulated gate field effect transistor) PQ, output node 920 N channel MOS transistor NQ connected to the ground node and receiving the output signal of inverter circuit 910 at its gate is included.

  Now, when output permission signal OEM is at L level, the output signals of NAND circuit 906 and gate circuit 907 are both at H level, the output signal of level conversion circuit 908 is the output power supply voltage VDDQ level, and the output signal of level conversion circuit 909 is Becomes the external power supply voltage EXVDD level. Inverter 910 receives external power supply voltage EXVDD as an operating power supply voltage, inverts the output signal of level conversion circuit 909, and the output signal of inverter circuit 910 becomes L level.

  Therefore, in output buffer circuit 912, MOS transistors PQ and NQ are both turned off, and output buffer circuit 912 is in an output high impedance state.

  When the output permission signal OEM becomes H level, the NAND circuit 906 operates as an inverter, while the gate circuit 907 operates as a buffer circuit. When internal read data RD is at H level, the output signal of NAND circuit 906 is at L level and the output signal of gate circuit 907 is at H level. Therefore, the output signal of level conversion circuit 908 becomes L level, the output signal of inverter circuit 910 becomes L level, and in output buffer circuit 912, MOS transistor PQ is turned on and MOS transistor NQ is turned off. In this state, output node 920 is driven to output power supply voltage VDDQ level via MOS transistor PQ.

  On the other hand, when internal read data RD is at L level, the output signal of NAND circuit 906 is at H level and the output signal of gate circuit 907 is at L level. Accordingly, the output signal of inverter 910 becomes external power supply voltage EXVDD level, MOS transistor PQ in output buffer circuit 912 is turned off, MOS transistor NQ is turned on, and output node 920 is connected to ground voltage level via MOS transistor NQ. It is driven up to. By applying an external power supply voltage level signal to the gate of MOS transistor NQ using inverter circuit 910, the current drive capability of MOS transistor NQ is increased, and output node 920 is discharged to the ground voltage level at high speed. .

  FIG. 13 is a diagram illustrating an example of the configuration of the level conversion circuit 908. In FIG. 13, level conversion circuit 908 includes an inverter 908a receiving output signal SIN of NAND circuit 906, and an N-channel MOS transistor connected between internal node NA and ground node and receiving NAND circuit output signal SIN at its gate. 908b, N-channel MOS transistor 908c connected between internal node NB and ground node and receiving the output signal of inverter 908a at its gate, connected between output power supply node and internal node NA, and its gate connected to internal node P channel MOS transistor 908d connected to NB and a P channel MOS transistor 908e connected between the output power supply node and internal node NB and having its gate connected to internal node NA are included. Output signal SOUT of level conversion circuit 908 is generated from internal node NB.

  When the signal SIN is at the H level, the MOS transistor 908b is turned on and the MOS transistor 908c is turned off. Therefore, internal node NA is discharged through MOS transistor 908b, and its voltage level is lowered. Accordingly, MOS transistor 908e is turned on to charge internal node NB, and the voltage level of internal node NB is set to the output power supply. Increase to voltage VDDQ level.

  When internal node NB reaches the output power supply voltage level, MOS transistor 908d is turned off. Therefore, signal SIN at peripheral power supply voltage VDDP level is converted to signal SOUT at output power supply voltage VDDQ level.

  On the other hand, when the signal SIN is at L level, the MOS transistor 908b is turned off and the MOS transistor 908c is turned on. In this state, internal node NB is discharged through MOS transistor 908c, and its voltage level is lowered. Accordingly, MOS transistor 908d is turned on to charge internal node NA to output power supply voltage VDDP level, and MOS transistor 908e is turned off accordingly. Therefore, in this state, signal SOUT from internal node NB is at L level.

  As described above, the level conversion circuit 908 converts the signal SIN having the amplitude of the peripheral power supply voltage VDDP level into a signal having the amplitude VDDQ level, and does not perform the logic level conversion.

  By using this level conversion circuit 908, the internal circuit can be driven at the peripheral power supply voltage VDDP level, and the output buffer circuit 912 can generate an output power supply voltage level signal.

  In the case where peripheral power supply voltage VDDP is equal to external power supply voltage EXVDD, if the output power supply voltage VDDQ is higher, the amplitude of the signal applied to output buffer circuit 912 is converted to the output power supply voltage level, Make falling characteristics equal. As a result, the rising / falling characteristics of the output buffer circuit 912 when driving the output node are made equal.

  FIG. 14 is a diagram schematically illustrating an example of the configuration of the data processing system. In the processing system shown in FIG. 14, a processing device 950, a semiconductor storage device 952 for storing data used by the processing device 950, and a memory 954 different from the semiconductor storage device 952 are interconnected via a bus 956. .

  Processing device 950 receives power supply voltages VDDL and VDDQ as operating power supply voltages. Semiconductor memory device 952 receives power supply voltages EXVDD and VDDQ as operating power supply voltages. Memory 954 receives power supply voltage VDDL as an operating power supply voltage. When processing device 950 transmits data to semiconductor memory device 952 via bus 956, the signal is transferred in accordance with output power supply voltage VDDQ, and the signal interface with semiconductor memory device 952 is adjusted.

  In such a data processing system, when the semiconductor storage device 952 is not accessed for a long period of time, the processing device 950 stops supplying the external power supply voltage EXVDD to at least the semiconductor storage device 952 via a power management device (not shown). . The processing device 950 executes processing using data stored in the memory 954.

  Therefore, since data / signals are transferred between the memory 954 and the processing device 950 via the bus 956, the semiconductor memory device 952 is supplied with the external power supply voltage EXVDD while the output power supply voltage VDDQ is turned on. Even when stopped, the output buffer circuit 912 shown in FIG. 12 is required to maintain the output high impedance state. In the case of a MOS transistor, when the gate-source voltage becomes equal to or lower than the absolute value of the threshold voltage, the MOS transistor is turned off. Therefore, for example, in the configuration shown in FIG. 13, even if peripheral power supply voltage VDDP generated from external power supply voltage EXVDD decreases as the external power supply voltage EXVDD stops being supplied, the peripheral power supply voltage VDDP becomes H level in the standby state. The set signal SIN is not discharged to the ground voltage level, the signal SIN is held at the intermediate voltage level, and similarly, the output signal of the inverter 908a may be held at the intermediate voltage level.

  In this case, when both MOS transistors 908b and 908c are turned on or turned off in level conversion circuit 908, the voltage levels of internal nodes NA and NB become indefinite, and level conversion circuit 908 Output signal SOUT is not held at the output power supply voltage VDDQ level but is held at the intermediate voltage level. When such a state occurs, it is conceivable that the MOS transistor PQ supplies current to the output node 920 in the output buffer circuit 912.

  Similarly, in FIG. 12, even if the supply of external power supply voltage EXVDD is stopped, the output signal of inverter 910 is not completely discharged to the ground voltage level, and the output signal of level conversion circuit 909 rises to the intermediate voltage level. Accordingly, the output signal of the inverter circuit 910 is held at the intermediate voltage level, and the discharge MOS transistor is turned on. Therefore, even in this state, in output buffer circuit 912, MOS transistor NQ is turned on to drive output node 920 to the ground voltage level, and output buffer circuit 912 does not enter the output high impedance state.

  In the semiconductor memory device 952, when the output buffer circuit 912 is set to a state different from the high impedance state, the external buffer circuit 912 outputs a signal / data transferred between the memory 954 and the processing device 950. There is a problem that the data has an adverse effect, and the signal / data cannot be accurately transferred between the processing device 950 and the memory 954.

  Even when the processing device 950 is connected to the semiconductor memory device 952 via the bus 956 and the processing device 950 and the memory 954 are connected via a bus different from the memory 954, the processing device 950 When the signal line of the bus connecting the semiconductor memory device 952 is terminated at a voltage level different from the output power supply voltage VDDQ, and the output buffer circuit 912 is set to a state different from the output high impedance state, A problem arises in that current flows between the output buffer circuit 912 and the termination voltage source, and current consumption increases.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that can reliably hold an output buffer circuit in an output high impedance state even when an external power supply voltage is cut off while an output power supply voltage is supplied. Is to provide.

  A semiconductor device according to a first aspect of the present invention receives a first power supply voltage as an operating power supply voltage, generates a first output drive signal according to at least an internal signal, and a second output drive signal generation circuit. The first latch circuit that receives and supplies the first power supply voltage as an operating power supply voltage, latches and transfers the first output drive signal, and the second power supply voltage as the operating power supply voltage, and according to the output signal of the first latch circuit It includes a first output transistor that drives a main output node coupled to the bus signal line and is rendered non-conductive when supply of the first power supply voltage is stopped.

  The semiconductor device according to the first aspect of the present invention further includes a second output drive signal generation circuit that receives the first power supply voltage as an operation power supply voltage and generates a second output drive signal according to at least an internal signal; A second latch circuit that receives the second power supply voltage as an operating power supply voltage and latches and transfers the second output drive signal; and is selectively rendered conductive according to at least the output signal of the second latch circuit. The output node is driven to a voltage level having a polarity different from that of the second power supply voltage, and includes a second output transistor which is rendered non-conductive in accordance with the output signal of the second latch circuit when supply of the first power supply voltage is stopped. The main output node is set to a high impedance state when supply of the first power supply voltage is stopped by the non-conduction state of the first and second output transistors.

  A semiconductor device according to a second aspect of the present invention receives a first power supply voltage as an operation power supply voltage, generates a first output drive signal according to at least an internal signal, and a second output drive signal generation circuit. The first latch circuit that receives and supplies the first power supply voltage as an operating power supply voltage, latches and transfers the first output drive signal, and the second power supply voltage as the operating power supply voltage, and according to the output signal of the first latch circuit It includes a first output transistor that drives a main output node coupled to the bus signal line and is rendered non-conductive when supply of the first power supply voltage is stopped.

  The first latch circuit receives the second power supply voltage as an operating power supply voltage and inverts the first output drive signal, and selectively inputs the inverter to the second power supply voltage according to the output signal of the inverter. A latch transistor coupled to a third power supply node having a different logic level is included.

  The semiconductor device according to a second aspect of the present invention further includes a second output drive signal generation circuit that receives the first power supply voltage as an operation power supply voltage and generates a second output drive signal according to at least an internal signal; A second latch circuit that receives the second power supply voltage as an operating power supply voltage and latches and transfers the second output drive signal; and is selectively rendered conductive according to at least the output signal of the second latch circuit. The output node is driven to a voltage level having a polarity different from that of the second power supply voltage, and includes a second output transistor which is rendered non-conductive in accordance with the output signal of the second latch circuit when supply of the first power supply voltage is stopped.

  Even when the supply of the first power supply voltage is cut off by providing a latch circuit that receives the second power supply voltage as the operation power supply voltage and driving the output transistor or the output drive circuit according to the output signal of the latch circuit, The latch circuit latches the state immediately before the first power supply voltage is cut off, and reliably holds the output transistor and the output drive transistor in the state immediately before the first power supply voltage is cut off, thereby maintaining the output high impedance state. be able to. As a result, when the first power supply voltage supply is cut off, the output circuit can be reliably set to the output high impedance state, and a signal / data collision can be prevented from occurring on the external bus.

[Embodiment 1]
1 schematically shows a configuration of an output circuit according to the first embodiment of the present invention. In FIG. In FIG. 1, an output circuit 903 is turned on when an inverter circuit 1 that receives an output signal of a NAND circuit 906, an inverter circuit 2 that receives an output signal of the inverter circuit 1, and an output signal of the inverter circuit 2 is at an H level. N channel MOS transistor 3 that drives input node ND of circuit 2 to the ground voltage level, inverter circuit 4 that receives the output signal of gate circuit 907, inverter circuit 5 that receives the output signal of inverter circuit 4, and inverter circuit 5 N channel MOS transistor 6 that conducts when the output signal is at H level and holds node NF at the ground voltage level, inverter circuit 7 that receives the output signal of inverter circuit 6, and the output node according to the output signals of inverter circuits 2 and 7 An output buffer circuit 912 for driving 920 is included.

  NAND circuit 906 receives peripheral power supply voltage VDDP as an operating power supply voltage, and receives internal read data RD and read permission signal OEM from internal read circuit 905 as input signals, as in the conventional case.

  Gate circuit 907 receives internal read data RD and read permission signal OEM as input signals, and receives peripheral power supply voltage VDDP as an operating power supply voltage.

  The peripheral power supply voltage VDDP may be at the same voltage level as the external power supply voltage EXVDD, or may be generated by stepping down the external power supply voltage EXVDD. In the description of the embodiment shown in FIG. 1, the case where the peripheral power supply voltage VDDP is generated by stepping down the external power supply voltage EXVDD will be described.

  The output signal of inverter circuit 2 is applied to the gate of P channel MOS transistor TP included in output buffer circuit 912, and the output signal of inverter circuit 7 is applied to the gate of N channel MOS transistor TN included in output buffer circuit 912. It is done.

  Inverter circuits 1 and 4 receive external power supply voltage EXVDD as an operating power supply voltage and invert the output signals of NAND circuit 906 and gate circuit 907, respectively. When the peripheral power supply voltage VDDP has a voltage level different from that of the external power supply voltage EXVDD, these inverter circuits 1 and 4 have a level conversion function or a level conversion circuit is disposed in front of them.

  Inverter circuits 1 and 4 may receive peripheral power supply voltage VDDP as an operating power supply voltage. Here, an indefinite state of the internal signal when the supply of external power supply voltage EXVDD is cut off will be described, and a circuit that receives an internal power supply voltage corresponding to this external power supply voltage as an operating power supply voltage and a circuit that receives output power supply voltage VDDQ as an operating power supply voltage In order to explain the stabilization of the signal at the boundary portion, inverter circuits 1 and 4 are shown to receive external power supply voltage EXVDD as the operating power supply voltage.

  Inverter circuits 2, 5 and 7 receive output power supply voltage VDDQ as an operating power supply voltage. Internal read circuit 905 receives peripheral power supply voltage VDDP as an operating power supply voltage.

  Consider a state where the supply of the external power supply voltage EXVDD is stopped while the output power supply voltage VDDQ is supplied as shown in FIG. Here, the supply of external power supply voltage EXVDD is stopped when the semiconductor memory device is in a standby state.

  Peripheral power supply voltage VDDP is generated from external power supply voltage EXVDD. Therefore, when the supply of external power supply voltage EXVDD is stopped, the voltage level of peripheral power supply voltage VDDP decreases accordingly. When the voltage level of peripheral power supply voltage VDDP falls to about the threshold voltage level of the MOS transistor of the constituent element, the circuit receiving peripheral power supply voltage VDDP as the operating power supply voltage becomes inoperable, and internal read data RD and output permission are set. The voltage level of the output signal of the peripheral circuit that outputs the signal OEM or the like becomes indefinite. For example, in NAND circuits 906 and 907, when the voltage level of the input signal reaches the threshold voltage level of the N-channel MOS transistor of those components, the signal applied to the gate of the N-channel MOS transistor in the on state The voltage level is about the threshold voltage level, the on-state N-channel MOS transistor is turned off, and the output signals of these NAND circuit 906 and gate circuit 907 are indefinite.

  In the inverter circuits 1 and 4 that receive external power supply voltage EXVDD as the operating power supply voltage in accordance with the output signal in the undefined state, the voltage level of the input / output signal is similarly undefined.

  In the standby state, output node ND of inverter circuit 1 is held at the ground voltage level by inverter circuit 2 and MOS transistor 3, and output node NF of inverter circuit 4 is maintained by inverter circuit 5 and MOS transistor 6. Is set to L level. Therefore, in this state, even if the supply of external power supply voltage EXVDD is cut off and the voltage at the input node of inverter circuits 1 and 4 becomes indefinite, output power supply voltage VDDQ is supplied, so inverter 2 and the MOS transistor 3 holds node ND at the ground voltage level, and node NF is held at the ground voltage level by inverter circuit 5 and MOS transistor 6. Therefore, even if NAND circuit 906, inverter circuit 1, gate circuit 907 and inverter circuit 4 become inoperable due to supply interruption of external power supply voltage EXVDD, internal nodes ND and NF are reliably held at the ground voltage level. be able to.

  In this state, the voltage level of output node NE of inverter circuit 2 is H level, and the voltage level of output node NG of inverter circuit 7 that receives the output signal of inverter circuit 5 is L level. MOS transistors TP and TN are both turned off, and output buffer circuit 912 can be maintained in a high impedance state even when supply of external power supply voltage EXVDD is interrupted.

  In FIG. 1, inverter circuits 1 and 4 may be inverter circuits with a level conversion function for generating a signal having an amplitude of output power supply voltage VDDQ level. Also in this configuration, when the output signals of the NAND circuit 906 and the gate circuit 907 are in an indefinite state, the input signal of the level conversion circuit is in an indefinite state, and the output signal of the level conversion circuit is in an indefinite state. Even in this case, by holding the output node of the level conversion circuit at the standby state voltage level with the latch circuit composed of the inverter and MOS transistor of the next stage, the output buffer circuit is reliably connected to the external power supply voltage EXVDD. When the supply is cut off, the output high impedance state can be set.

  Further, even when inverter circuits 1 and 4 receive peripheral power supply voltage VDDP as an operating power supply voltage, peripheral power supply voltage VDDP is a step-down voltage of the external power supply voltage, and similar effects can be obtained.

[Modification 1]
FIG. 3 schematically shows a configuration of a modification of the first embodiment of the present invention. In the configuration shown in FIG. 3, external power supply voltage EXVDD is supplied as an operating power supply voltage for operating the peripheral circuits. That is, the distribution of the power supply voltage when the external power supply voltage EXVDD is given as the peripheral power supply voltage VDDP is shown for confirmation. For example, when the external power supply voltage EXVDD is 2.5V and the output power supply voltage VDDQ is 1.8V, the external power supply voltage EXVDD is supplied to the peripheral circuit as an operation power supply voltage.

  Internal read circuit 10 receives external power supply voltage EXVDD as an operating power supply voltage and generates internal read data RD at the level of external power supply voltage EXVDD. NAND circuit 11 receiving output permission signal OEM and internal read data RD also receives external power supply voltage EXVDD as its operating power supply voltage. Gate circuit 12 receiving internal read data RD and output permission signal OEM also receives external power supply voltage EXVDD as an operating power supply voltage. The inverter circuit 13 that receives the output signal of the NAND circuit 11 receives the external power supply voltage EXVDD as the operating power supply voltage, and the inverter circuit 14 that receives the output signal of the gate circuit 12 also receives the external power supply voltage EXVDD as the operating power supply voltage. In this case, the inverter circuits 13 and 14 do not have a level conversion function. The other configuration of the output circuit 903 shown in FIG. 2 is the same as that of the output circuit 903 shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 2, when external power supply voltage EXVDD is used as an operating power supply voltage for the internal circuit, supply of external power supply voltage EXVDD is cut off and the output signals of inverter circuits 13 and 14 become indefinite. Even in the case, similarly to the configuration shown in FIG. 1, node ND is held at the voltage level (ground voltage level) in the standby state by inverter circuit 2 and MOS transistor 3, and node NF is connected to inverter circuit 5 and MOS transistor. The transistor 6 holds the voltage level in the standby state.

  Therefore, even when external power supply voltage EXVDD is used as an operating power supply voltage for the internal circuit, a latch circuit composed of inverter circuit 2 and MOS transistor 3 and a latch circuit composed of inverter circuit 5 and MOS transistor 6 are provided. By providing each of the output portions of inverter circuits 13 and 14 that receive external power supply voltage EXVDD as an operating power supply voltage, supply of external power supply voltage EXVDD is reliably cut off while output power supply voltage VDDQ is supplied. In addition, the output buffer circuit 912 can be held in the output high impedance state.

  As described above, according to the first embodiment of the present invention, the latch circuit that receives the output power supply voltage as the operation power supply voltage is arranged at the output stage of the circuit that receives the power supply voltage related to the external power supply voltage as the operation power supply voltage. Therefore, even when the supply of the external power supply voltage EXVDD is interrupted when the output power supply voltage is supplied, the output buffer circuit can be reliably held in the output high impedance state.

[Embodiment 2]
FIG. 4 shows a configuration of the output circuit according to the second embodiment of the present invention. In FIG. 4, external power supply voltage EXVDD is used as a peripheral power supply voltage for operating the internal circuit.

  In order to drive P channel MOS transistor TP of output buffer circuit 912, NAND circuit 11 that receives internal read data RD and output permission signal OEM, inverter circuit 13 that receives the output signal of NAND circuit 11, and the output of inverter circuit 13 An inverter circuit 2 for receiving signals is provided. In accordance with the output signal of inverter circuit 2, N channel MOS transistor 3 is provided to hold input node ND of inverter circuit 2 at the ground voltage level. The configuration of the portion for driving P channel MOS transistor TP shown in FIG. 4 is the same as the configuration shown in FIG.

  In order to drive N channel MOS transistor TN included in output buffer circuit 912, gate circuit 12 receiving internal read data RD and output permission signal OEM, and the gate of MOS transistor TN are driven according to the output signal of gate circuit 12. An inverter circuit 20 is provided. This inverter circuit 20 receives external power supply voltage EXVDD as an operating power supply voltage. By setting the gate voltage of output MOS transistor TN to external power supply voltage EXVDD level when conducting, the current driving capability of MOS transistor TN is increased, and the output node is discharged at high speed.

  In order to drive N channel MOS transistor TN, inverter circuit 21 that receives the output signal of gate circuit 12, inverter circuit 22 that receives the output signal of inverter circuit 21, and inverter circuit 20 according to the output signal of inverter circuit 22 An N channel MOS transistor 24 for driving output node NG to the ground voltage level and an N channel MOS transistor 23 for holding input node NH of inverter circuit 22 at the ground voltage level according to the output signal of inverter circuit 22 are provided.

  In the configuration shown in FIG. 4, the inverter circuit 2 and the MOS transistor 3 constitute a latch circuit. Therefore, even when the supply of external power supply voltage EXVDD is stopped in the standby state, output node NE of inverter circuit 2 is connected to output power supply by inverter circuit 2 and MOS transistor 3 as in the case of the first embodiment. The voltage VDDQ level can be maintained.

  Gate circuit 12 and inverter circuits 20 and 21 receive external power supply voltage EXVDD as an operating power supply voltage, and inverter circuit 22 receives output power supply voltage VDDQ as an operating power supply voltage. Therefore, even if supply of external power supply voltage EXVDD is interrupted, input node NH of inverter circuit 22 is held at the ground voltage level by inverter circuit 22 and MOS transistor 23, and output node NI of inverter circuit 22 It is held at the power supply voltage VDDQ level. Therefore, MOS transistor 24 is kept on, node NG is held at the ground voltage level regardless of the state of the output signal of inverter circuit 20, and MOS transistor TN of output buffer circuit 912 is reliably kept off. Is done.

  In the configuration shown in FIG. 4, an output buffer circuit 912 includes a latch circuit that receives output power supply voltage VDDQ as an operating power supply voltage at the output of inverter circuit 21 that receives external power supply voltage EXVDD as an operating power supply voltage. Both P channel MOS transistor TP and N channel MOS transistor TN can be held in the off state, and output node 920 can be set in the output high impedance state.

  In the above configuration, the peripheral power supply voltage VDDP may be generated from the external power supply voltage EXVDD and used as the operation power supply voltage of this peripheral circuit, as in the configuration shown in FIG. In the case of using this peripheral power supply voltage VDDP as the operating power supply voltage, peripheral power supply voltage VDDP is applied to the circuits other than inverter circuit 20 shown in FIG. 4 instead of external power supply voltage EXVDD. However, the inverter circuits 13, 20 and 21 are composed of inverters having a level conversion function.

  Even in the configuration in which the peripheral power supply voltage VDDP is generated by stepping down the external power supply voltage, since the peripheral power supply voltage VDDP is generated from the external power supply voltage EXVDD, a signal that may be indefinite is determined by the latch circuit. A state signal can be held.

  As described above, according to the second embodiment of the present invention, even when the gate of the MOS transistor for discharging the output node to the ground voltage level is driven by the signal having the amplitude of the external power supply voltage EXVDD level, the output node discharge is performed. By disposing a latch circuit that receives the output power supply voltage as the operating power supply voltage in the path for driving the gate of the MOS transistor TN to the ground voltage level, the discharge MOS transistor can be reliably secured even when the supply of the external power supply voltage EXVDD is cut off. The output buffer circuit can be reliably set to the output high impedance state.

[Embodiment 3]
FIG. 5 schematically shows a structure of a latch circuit according to the third embodiment of the present invention. The latch circuit shown in FIG. 5 latches an output signal of inverter IV1 that receives external power supply voltage EXVDD as an operating power supply voltage. The latch circuit receives the output power supply voltage VDDQ as an operation power supply voltage, and inverts the output signal of the inverter IV1, and the input node NJ of the inverter circuit IV2 is set to the ground voltage level according to the output signal of the inverter circuit IV2. An N channel MOS transistor QN to be driven is included. Inverter circuit IV2 and N channel MOS transistor QN generically represent the latch circuits shown in FIGS.

  The inverter circuit IV1 in the previous stage and the circuit in the previous stage of the inverter circuit IV1 receive the external power supply voltage EXVDD as the operating power supply voltage. Therefore, when external power supply voltage EXVDD is lowered to the threshold voltage Vth level of the N channel MOS transistor, the circuit portion receiving external power supply voltage EXVDD as the operation power supply voltage becomes inoperable. That is, in the CMOS circuit, unless the operating power supply voltage rises above the threshold voltage of the constituent MOS transistor, a path through which the operating current flows is not formed and the CMOS circuit cannot operate.

  For example, when the power supply is cut off when the output signal of the CMOS inverter circuit is at the H level, the discharging N-channel MOS transistor is in the off state and does not perform the discharging operation. On the other hand, in this state, the P-channel MOS transistor is turned off when the gate-source voltage reaches the threshold voltage. Even if the output signal decreases according to the voltage level of the power supply voltage, it does not decrease below the absolute value of the threshold voltage of the P-channel MOS transistor.

  Also, if the power supply is cut off when the output signal of the CMOS inverter circuit is at the L level, the P channel MOS transistor is turned on when the voltage signal decreasing speed is faster than the operating power supply voltage decreasing speed. As a result, the voltage level of the output signal is raised, the N-channel MOS transistor is turned off, and the voltage rise of the output signal cannot be discharged. At this time, even if the P-channel MOS transistor is turned off because the gate-source voltage becomes the absolute value of the threshold voltage, the output signal is disconnected from the operating power supply. It cannot be lowered with the power supply voltage, and the output signal is in a state where the voltage level is raised.

  Therefore, from the relationship between the decrease rate of the power supply voltage EXVDD and the change rate of the input / output signal of the inverter IV1, the output signal of the inverter circuit IV1 is at most the absolute value of the threshold voltage of the MOS transistor of the component (hereinafter, simply referred to as “the output voltage”) It is conceivable to reach the Vth level (referred to as threshold voltage). Inverter circuit IV2 is composed of a ratio circuit, and even if the signal voltage at output node NJ of inverter IV1 is at the threshold voltage Vth level, a signal at the voltage level of output power supply voltage VDDQ is reliably output. The size (β ratio) of the P channel MOS transistor and the N channel MOS transistor of the constituent elements is adjusted.

  That is, as shown in FIG. 6, generally, in a CMOS inverter circuit, the input logic threshold value is often set to a voltage level that is ½ of the operating power supply voltage, and is often composed of a ratioless circuit. In this case, if the output power supply voltage VDDQ is 1.8V, the input logic threshold value is VDDQ / 2, which is 0.9V. If the threshold voltage Vth is 0.8 V, as shown by the curve A in FIG. 6, when the input signal IN slightly exceeds the threshold voltage Vth level, the voltage of the output signal OUT is rapidly increased. The level drops. For example, when the output signal of inverter IV2 suddenly drops in accordance with the output signal of inverter circuit IV1, for example, drops to a voltage level ½ of output power supply voltage VDDQ, threshold voltage of N channel MOS transistor QN As a result, the voltage level of the output signal of inverter circuit IV2 drops to a voltage level close to that, and MOS transistor Q2 cannot be sufficiently turned on, and node NJ cannot be held at the ground voltage level.

  Further, when the node NJ is held at such an intermediate voltage level, a through current flows in the inverter circuit IV2. Therefore, this inverter circuit IV2 is constituted by a ratio circuit, the input logic threshold value is increased, and the input signal (signal voltage at node NJ) is at the threshold voltage Vth level as shown by curve B in FIG. Even so, the power supply voltage VDDQ level voltage is surely output.

  In general, the input logic threshold value VT and the size of the component MOS transistors are usually expressed by the following equations.

  Here, Vthn and Vthp indicate the threshold voltages of the N channel MOS transistor and the P channel MOS transistor, respectively, and βP and βN indicate the sizes (channel width and channel length) of the P channel MOS transistor and the N channel MOS transistor, respectively. The ratio is determined by the ratio of W / L).

  The coefficient βP is determined by the ratio of the channel width and the channel length of the P-channel MOS transistor, and the coefficient βN is determined by the ratio of the channel width and the channel length of the N-channel MOS transistor, so that the P-channel MOS transistor and the N-channel MOS The transistor size is adjusted to set its input logic threshold higher than normal. Thereby, even if the voltage level of node NJ rises because the circuit receiving external power supply voltage EXVDD in the previous stage becomes inoperable, the output signal of inverter circuit IV2 can be reliably set to output power supply voltage VDDQ level. Thus, MOS transistor QN can be reliably set to the on state, and node NJ can be held at the ground voltage level.

  Inverter IV1 shown in FIG. 5 receives external power supply voltage EXVDD as an operating power supply voltage. However, inverter IV1 may receive peripheral power supply voltage VDDP as an operating power supply voltage. However, in this case, it is necessary to arrange a level conversion circuit at the next stage of the inverter IV1.

  As described above, according to the third embodiment of the present invention, the inverter of the latch circuit that receives the output power supply voltage as the operating power supply voltage is configured by the ratio circuit, and the input logic threshold value is the MOS transistor. Even if it is about the threshold voltage, the output power supply voltage VDDQ is set to be judged as being an L level signal, and when the external power supply voltage is cut off, the input of the inverter of the latch circuit Even when the voltage level of the signal rises, the input signal can be reliably held at the L level, and the output buffer circuit can be held in the output high impedance state.

[Embodiment 4]
FIG. 7 shows a structure of the output circuit according to the fourth embodiment of the present invention. In the configuration shown in FIG. 7, external power supply voltage EXVDD is used as an operating power supply voltage for operating the internal circuit.

  7 is different from the output circuit shown in FIG. 4 in the following points. That is, instead of the inverter circuit 13 that receives the output signal of the NAND circuit 11, a NOR circuit 30 that receives the external power supply voltage input detection signal ZPOREX and the output signal of the NAND gate 11 is provided. The output signal of the NOR circuit 30 is applied to the inverter circuit 2 constituting the latch circuit. Further, instead of the inverter circuit 21 that receives the output signal of the gate circuit 12, a NOR circuit 32 that receives the external power supply voltage input detection signal ZPOREX and the output signal of the gate circuit 12 is provided. The output signal of the NOR circuit 32 is applied to the inverter circuit 22 constituting the latch circuit. The other configuration of the output circuit shown in FIG. 7 is the same as that of the output circuit shown in FIG. 4. Corresponding portions are allotted with the same reference numerals, and detailed description thereof is omitted.

  External power supply voltage input detection signal ZPOREX is maintained at the same voltage level as external power supply voltage VDDEX until external power supply voltage EXVDD is stabilized, and is set to L level when external power supply voltage EXVDD is stabilized. Therefore, when the external power supply voltage EXVDD is turned on, the NOR circuits 30 and 32 determine that the external power supply voltage turn-on detection signal EXVDD is H level, so that their output signals are set to L level and become indefinite. Can be prevented. When external power supply voltage EXVDD is stabilized, external power supply voltage input detection signal ZPOREX becomes L level, and NOR circuits 30 and 32 operate as inverter circuits.

  Since the output power supply voltage VDDQ is supplied when the external power supply voltage EXVDD is turned on, the node ND is held at the ground voltage level by the inverter circuit 2 and the MOS transistor 3. Similarly, node NH is held at the ground voltage level by inverter circuit 22 and MOS transistor 23. Even when the external power supply voltage EXVDD is turned on, the output signals of the NOR circuits 30 and 32 are held at the L level until the external power supply voltage input detection signal ZPOREX becomes the L level. It is possible to prevent the output signals of the NOR circuits 30 and 32 from being unstable when being turned on and adversely affecting the output signals of the inverter circuits 20 and 22.

  Therefore, after the external power supply voltage is cut off, when the external power supply voltage EXVDD is turned on again to access the semiconductor memory device, the output circuit shifts to a state different from the output high impedance state, and the data / An adverse effect on the signal can be reliably prevented.

  FIG. 8 is a diagram illustrating an example of a configuration of a part that generates the external power supply voltage input detection signal. In FIG. 8, the external power-on detection unit includes a power-on detection circuit 40 that detects the application of the external power supply voltage EXVDD, and an inverter circuit 42 that inverts the output signal POR of the power-on detection circuit 40. The inverter circuit 42 receives the external power supply voltage EXVDD as an operating power supply voltage, inverts the power-on detection signal output from the power-on detection circuit 40, and generates an external power supply voltage input detection signal ZPOREX.

  FIG. 9 is a signal waveform diagram showing an operation of the power-on detection unit shown in FIG. The operation of the external power-on detection unit shown in FIG. 8 will be briefly described below with reference to FIG.

  When external power supply voltage EXVDD is applied, the voltage level gradually rises according to the load of the external power supply line. The power-on detection circuit 40 has a well-known configuration, and when the external power is turned on, the output signal rises a little as the voltage level of the external power supply voltage increases, and is immediately grounded by the internal circuit (inverter circuit). Driven to the L level of the voltage level.

  While the output signal POR of the power-on detection circuit 40 is at the L level, the inverter circuit 42 increases the voltage level of the external power supply voltage input detection signal ZPOREX according to the voltage level of the external power supply voltage EXVDD.

  When external power supply voltage EXVDD reaches a predetermined voltage level or stabilizes, output signal POR of power-on detection circuit 40 rises to H level, and accordingly, external power supply voltage input detection signal ZPOREX from inverter circuit 40 becomes L Become a level.

  Therefore, when external power supply voltage EXVDD is applied, if external power supply voltage input detection signal ZPOREX exceeds the threshold voltage of the N-channel MOS transistor included in NOR circuits 30 and 32, NOR circuits 30 and 32 are surely connected. Are held at the L level. Therefore, when the power is turned on, the output signals of NOR circuits 30 and 32 can be reliably fixed at the L level, and the latch signal voltage of the latch circuit composed of the inverter circuit and the MOS transistor is not adversely affected.

  In the above description, the external power supply voltage EXVDD is used as the operating power supply voltage for the peripheral circuits. However, the peripheral power supply voltage VDDP obtained by lowering the external power supply voltage EXVDD may be used as the operation power supply voltage of the peripheral circuit. In the case of this configuration, as shown in parentheses in FIG. 7, the peripheral power supply voltage VDDP is applied as the operation power supply voltage instead of the external power supply voltage of the circuit excluding the inverter circuit 20. When this peripheral power supply voltage VDDP is used as the operating power supply voltage of the peripheral circuit, a peripheral power supply voltage input signal for detecting the input of the peripheral power supply voltage VDDP may be used instead of the external power supply voltage input detection signal ZPOREX.

  As described above, according to the fourth embodiment of the present invention, the power supply voltage input detection signal is given to the gate circuit that receives the voltage corresponding to the external power supply voltage in the previous stage of the latch circuit as the operation power supply voltage. When the external power supply voltage is turned on, the output signal can be held at a predetermined voltage level, and when the external power supply voltage is turned on, the latch operation of the latch circuit can be prevented from being adversely affected. Even at the time of return, the output buffer circuit can be set to the output high impedance state.

  In the above description, the operation when the external power supply voltage is turned on again while the output power supply voltage VDDQ is supplied has been described. However, at the time of power-on such as system reset, the output circuit can be reliably initialized to the output high impedance state even in the sequence in which the output power-supply voltage VDDQ is first turned on and then the external power-supply voltage EXVDD is turned on. Thus, it is possible to reliably prevent malfunction of the entire system and erroneous initialization of the semiconductor memory device.

[Embodiment 5]
FIG. 10 schematically shows a structure of a main portion of the output circuit according to the fifth embodiment of the present invention. In FIG. 10, inverter circuit IV2 and N channel MOS transistor QN constitute a half latch (latch circuit). The latch circuit composed of the inverter circuit IV2 and the MOS transistor QN may be a latch circuit in any part of the first to fourth embodiments. A level conversion circuit 52 that converts the amplitude of the internal signal to the output power supply voltage VDDQ level is provided in the previous stage of the latch circuit. This level conversion circuit 52 converts the amplitude of the output signal of the pre-stage gate circuit 50 that receives the internal power supply voltage (peripheral power supply voltage) VDDP as the operation power supply voltage. That is, a voltage lower than the output power supply voltage VDDQ is applied as an operation power supply voltage to the internal circuit. The configuration of the level conversion circuit 52 is the same as that of the level conversion circuit shown in FIG. Between input node and output node of level conversion circuit 52, transfer gate 54 formed of an N-channel MOS transistor receiving output power supply voltage VDDQ is arranged at the gate.

  The transfer gate 54 is a low threshold voltage transistor (L-Vth transistor) having a low threshold voltage Vthn. In the standby state, output node NK of level conversion circuit 52 is held at the ground voltage level by inverter circuit IV2 and MOS transistor QN.

  In this state, the supply of the external power supply voltage EXVDD is interrupted, the voltage level of the peripheral power supply voltage VDD is lowered accordingly, and the transfer gate 54 even when the voltage level of the output signal of the pre-stage gate circuit 50 becomes indefinite. Transmits the voltage (ground voltage level) of the output node NK of the level conversion circuit 52 to the output node of the pre-stage gate circuit 50 (input node of the level conversion circuit 52). Therefore, in the level conversion circuit shown in FIG. 13, when the node NB corresponds to the output node NK of the level conversion circuit 52, the output signal (SIN) of the preceding gate circuit 50 becomes indefinite and the MOS transistors 908b and 908c Even if the voltage level of the internal nodes (NA and NB) tends to change to the intermediate voltage level, the inverter node IV2 and the MOS transistor QN cause the output node NK of the level conversion circuit 52 to be at the ground voltage level. The rise of the internal node of the level conversion circuit 52 can be suppressed.

  Further, even when the internal node NA shown in FIG. 13 may be at an intermediate voltage level, the transfer gate 54 holds the signal SIN shown in FIG. 13 at the ground voltage level, which is reliably shown in FIG. MOS transistor 908b is set to an off state, internal node NA can be held at output power supply voltage VDDQ level, level conversion circuit 52 can be reliably held in a latched state, and a through current can be prevented from being generated. . Further, it is possible to prevent the output signal of the level conversion circuit 52 from rising to the intermediate voltage level and causing a through current to flow through the inverter IV2.

  Therefore, when the internal circuit operates by receiving peripheral power supply voltage VDDP having a voltage level lower than output power supply voltage VDDQ as the operation power supply voltage, even in the configuration in which level conversion circuit 52 is provided, inverter circuit IV2 and MOS transistor QN The configured latch circuit can reliably prevent the output signal of the level conversion circuit 52 from entering an indeterminate state when the supply of the external power supply voltage (peripheral power supply voltage) is interrupted, and the output buffer circuit is reliably output high. The impedance state can be set.

  Further, the transfer gate 54 can prevent the output signal of the pre-stage gate circuit 50 from entering an indefinite state.

  In the above description, the operation when the external power supply voltage is cut off is described. However, even when the external power supply voltage is reapplied, the input / output node of level conversion circuit 52 can be reliably held at the voltage level in the standby state.

  The configuration shown in FIG. 10 is applicable to the configuration in which the peripheral power supply voltage is generated by stepping down the external power supply voltage and used as the operation power supply voltage of the peripheral circuit in the configuration shown in the first to fourth embodiments. is there.

[Other configurations]
In the first to fifth embodiments, the latch circuit formed of the inverter circuit and the MOS transistor holds its input node at the ground voltage level. However, using an inverter circuit and a P-channel MOS transistor, the latch circuit may be configured to hold the voltage level of the input node at the output power supply voltage level. In this case, it is necessary to adjust the number of inverter stages so that both the P-channel MOS transistor TP and the N-channel MOS transistor TN are turned off in the output buffer circuit.

  In the above description, the configuration of the output circuit of the semiconductor memory device is described. However, in a general semiconductor device, the present invention can be applied if the power supply voltage that the internal circuit cuts off to the external power supply voltage is used as the operation power supply voltage and the output buffer circuit uses the dedicated power supply voltage. It is.

  As described above, according to the present invention, in the semiconductor device that receives the output power supply voltage used in the output circuit and the external power supply voltage used by the internal circuit, the circuit having the power supply voltage that depends on the external power supply voltage as the operation power supply voltage. The next stage is provided with a latch circuit that uses the output power supply voltage as the operating power supply voltage. Even when the external power supply voltage is reliably shut off with the output power supply voltage turned on, the internal node is held in the standby state. And the output circuit can be set to an output high impedance state.

  That is, the first output drive signal generated according to the internal signal and having the amplitude of the first power supply voltage level is latched and transferred by the latch circuit that receives the second power supply voltage as the operation power supply voltage. The gate voltage of the first output transistor that drives the output node is set according to the output signal, and even if the supply of the first power supply voltage is cut off, the first latch circuit ensures that the first output transistor The gate voltage can be maintained at the same voltage level as in the standby state, and the first output transistor can be reliably maintained in the off state.

  The second output drive signal having the amplitude of the first power supply voltage level generated according to the internal signal is latched and transferred by the second latch circuit, and the second output transistor is transferred to the second latch. By driving according to the output signal of the circuit, the second output transistor can be reliably maintained in the OFF state even when the supply of the first power supply voltage is interrupted.

  In addition, by configuring the output drive circuit with the second output transistor that drives the output node according to the output signal of the latch circuit, the output node can be reliably output when the first power supply voltage is cut off with a simple circuit configuration. High impedance state can be set.

  And driving the output drive circuit to a reference voltage level according to the output signal of the latch circuit, an auxiliary drive circuit for generating a signal having the same logic level as the second output drive signal, and an output node of the auxiliary drive circuit; By driving the output node with the second output transistor according to the voltage of the output node of the auxiliary drive circuit, the gate voltage of the second output transistor can be maintained at the external power supply voltage level, and the output node can be driven with a large current driving capability. In the configuration for driving the output node, the output node can be stably set to the output high impedance state when the supply of the first power supply voltage is interrupted.

  By setting the input logic threshold value of the first latch circuit higher than the first power supply voltage level at which the first output drive signal generation circuit becomes inoperable, the operation is surely disabled. Even when the output voltage of the first output drive signal generation circuit may be held at the intermediate voltage level, the output node of the first output drive signal generation circuit is reliably connected to the reference voltage level by the inverter. The latch state can be maintained stably. Further, no through current is generated in the inverter, and an increase in current consumption can be suppressed.

  Similarly, by configuring the second latch circuit with an inverter circuit whose input logic threshold is higher than the second power supply voltage level at which the second output drive signal generation circuit becomes inoperable. Even when the first power supply voltage is cut off, the output signal of the inverter circuit can be held at a predetermined voltage level, and the latch operation can be performed reliably. In addition, the input node of the latch circuit can be prevented from reaching the intermediate voltage level, and a through current can be prevented from occurring in the latch circuit.

  Further, by using a circuit for detecting the first power supply voltage input and generating the first output drive signal in accordance with the first power supply detection signal, the voltage level of the internal node when the external power supply voltage is applied. Can be prevented from entering an indefinite state, and the latch voltage level by the latch circuit can be reliably maintained even when the external power supply voltage is turned on.

  By generating the second output drive signal in accordance with the first power supply voltage input detection signal, it is possible to prevent the second output drive signal from becoming indefinite when the second power supply voltage is input. Can cause the latch circuit to latch.

  In addition, a level conversion circuit for converting the first power supply voltage into a signal having an amplitude of the output power supply voltage level is arranged before the latch, and a transfer gate for receiving the first power supply voltage at the input / output node of the level conversion circuit. Therefore, even when the first power supply voltage is turned off, the level conversion circuit can reliably maintain the voltage level of the internal node at the predetermined voltage level in accordance with the output signal of the latch circuit. It is possible to prevent a through current from occurring in the circuit and to prevent the level conversion circuit output signal from entering an indefinite state.

  Similarly, in the configuration in which the level conversion circuit is provided in the previous stage of the second latch circuit, the output node of this level conversion circuit is connected by the transfer gate that receives the second power supply voltage at the gate, so that the first power supply It is possible to prevent the output signal of the level conversion circuit from becoming indefinite when the voltage is turned on or shut off.

  By applying the present invention to a circuit that interfaces between circuit devices having different power supply voltages, current consumption can be reduced.

It is a figure which shows the structure of the output circuit according to Embodiment 1 of this invention. FIG. 2 is a signal waveform diagram showing an operation of the output circuit shown in FIG. 1. It is a figure which shows the structure of the output circuit according to the modification of Embodiment 1 of this invention. It is a figure which shows the structure of the output circuit of Embodiment 2 of this invention. It is a figure which shows roughly the structure of the principal part of the output circuit according to Embodiment 3 of this invention. FIG. 6 is a diagram schematically showing input / output characteristics of the inverter circuit shown in FIG. 5. It is a figure which shows the structure of the output circuit according to Embodiment 4 of this invention. It is a figure which shows schematically the structure of the part which produces | generates the power-on detection signal shown in FIG. It is a signal waveform diagram which shows the operation | movement of the power-on detection part shown in FIG. It is a figure which shows roughly the structure of the principal part of the output circuit according to Embodiment 5 of this invention. It is a figure which shows schematically the whole structure of the conventional semiconductor device. FIG. 12 schematically shows a configuration of the output circuit shown in FIG. 11. It is a figure which shows an example of a structure of the level conversion circuit shown in FIG. It is a figure which shows the structure of the conventional data processing system roughly.

Explanation of symbols

  1, 2, 4, 5 Inverter circuit, 3, 6 MOS transistor, 11 NAND circuit, 7, 13, 14 Inverter circuit, 12 Gate circuit, 20, 21, 22 Inverter circuit, 23, 24 MOS transistor, 30, 32 NOR Circuit, 40 power-on detection circuit, 42 inverter circuit, 50 pre-stage gate circuit, 52 level conversion circuit, 54 transfer gate, IV1, IV2 inverter circuit, QN, TP, TN MOS transistor, 906 NAND circuit, 907 gate circuit, 912 output Buffer circuit.

Claims (2)

A first output drive signal generation circuit which receives the first power supply voltage as an operation power supply voltage and generates a first output drive signal according to at least an internal signal;
A first latch circuit that receives a second power supply voltage as an operating power supply voltage, and latches and transfers the first output drive signal;
Receiving the second power supply voltage as an operating power supply voltage, driving a main output node coupled to a bus signal line in accordance with an output signal of the first latch circuit, and stopping supply of the first power supply voltage; A first output transistor that is rendered non-conductive in accordance with an output signal of the first latch circuit;
A second output drive signal generation circuit which receives the first power supply voltage as an operation power supply voltage and generates a second output drive signal according to at least the internal signal;
A second latch circuit that receives the second power supply voltage as an operating power supply voltage, latches and transfers the second output drive signal, and drives the main output node in accordance with at least the output signal of the second latch circuit; An output drive circuit configured to selectively conduct according to an output signal of the second latch circuit and drive the main output node to a voltage level having a polarity different from that of the second power supply voltage. And a second output transistor that is rendered non-conductive in accordance with an output signal of the second latch circuit when supply of the first power supply voltage is stopped, and the main output node has the first power supply voltage A semiconductor device which is set to a high impedance state by the non-conduction state of the first and second output transistors when supply is stopped. A first output drive signal generating circuit for receiving a first power supply voltage as an operating power supply voltage and generating a first output drive signal according to at least an internal signal; and a second power supply voltage as an operating power supply voltage; The first latch circuit latches and transfers the output drive signal of the first inverter, and the first latch circuit receives the second power supply voltage as an operation power supply voltage and inverts the first output drive signal. And a latch transistor for selectively coupling the input of the inverter to a third power supply node having a logic level different from that of the second power supply voltage in accordance with an output signal of the inverter, and further comprising the second power supply voltage as an operating power supply. The first power supply voltage is received as a voltage and drives a main output node coupled to a bus signal line in accordance with an output signal of the first latch circuit. Time of stopping supply, the first output transistor being a non-conductive state in accordance with the latch output signal of said first latch circuit,
A second output drive signal generation circuit which receives the first power supply voltage as an operation power supply voltage and generates a second output drive signal according to at least the internal signal;
A second latch circuit that receives the second power supply voltage as an operating power supply voltage, latches and transfers the second output drive signal, and drives the main output node in accordance with at least the output signal of the second latch circuit; An output drive circuit configured to selectively conduct according to an output signal of the second latch circuit and drive the main output node to a voltage level having a polarity different from that of the second power supply voltage. And a second output transistor that is turned off in accordance with an output signal of the second latch circuit when the supply of the first power supply voltage is stopped.

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