JP2006345046A - Image decoding circuit, image decoding system, and electronic apparatus mounted therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem of a low restoring force of an image because decoding processing is terminated at a point of time when a code error is detected in the case of using a hardware decoder to decode compressed coded image data. <P>SOLUTION: In an image decoding circuit 100 for decoding coded image data, error detection circuits 14, 18, 22 detect code errors during decoding of the coded image data. A restart marker searching circuit 28 searches an identification code denoting a position of an independent region permitting closed decoding in a region appearing next after a coding error is detected. A supplement circuit 30 supplements prescribed dummy images between a position from which the code error is detected and a position from which the identification code is searched. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image decoding circuit for decoding compressed encoded image data, an image decoding system, and an electronic apparatus equipped with the image decoding circuit.

  Image data compression-coded in a format such as JPEG (Joint Photographic Experts Group) or MPEG (Moving Picture Experts Group) is widely used. Code errors occur in such encoded image data due to various factors such as noise being superimposed during communication. When image data including a code error is decoded, a display image including a portion different from the original image is displayed, or the decoding process is stopped halfway. On the other hand, a technique for restoring encoded image data is used. For example, Patent Literature 1 discloses a program for restoring encoded image data including a code error.

On the other hand, encoded image data is used in various electronic devices such as PCs and mobile phones. In such an electronic device, in order to reduce the processing of the host processor, a dedicated hardware decoder for decoding encoded image data may be mounted.
JP 2002-27254 A

  When encoded image data including a code error is decoded by a hardware decoder, the decoding process ends when the code error is detected, and all subsequent processes are left to the host processor. Therefore, when a code error is detected, the load on the host processor increases, and the purpose of providing a separate hardware decoder tends to be overlooked. Further, if the host processor does not perform the repair process, even if there is normal data after the code error is detected, the image at the decoding stage at the time of detection is displayed. For example, only half of the image may be displayed.

  The present invention has been made in view of such circumstances, and an object of the present invention is to improve the recoverability of encoded image data including errors when using an image decoding circuit configured with hardware resources. An image decoding circuit, an image decoding system, and an electronic device equipped with the image decoding circuit are provided.

  In order to solve the above-described problem, an image decoding circuit according to an aspect of the present invention includes an independent region that can be decoded within a region and a dependent region that is decoded using difference information from another region. An image decoding circuit for decoding encoded image data including an error detection circuit for detecting a code error during decoding of the encoded image data, and a position of an independent region that appears next after the code error is detected And a replenishment circuit for replenishing a predetermined dummy image between a location where the identification code is retrieved from a location where the code error is detected.

  According to this aspect, by mounting the search circuit and the supplement circuit on the image decoding circuit configured with hardware resources, it is possible to improve the recoverability of encoded image data including errors.

  The error detection circuit may notify the host processor when a code error is detected, and the search circuit and the supplement circuit may start operation upon receiving an instruction from the host processor. When the error detection circuit detects a code error, the decoding process may be interrupted and an instruction from the host processor may be waited.

  According to this aspect, when the dedicated image decoding circuit and the host processor perform the decoding process in cooperation, the scale of the image decoding circuit can be suppressed while suppressing the load applied to the host processor.

  The error detection circuit may detect whether a code not included in the code table necessary for entropy decoding is included in the encoded image data. The error detection circuit may detect whether or not there is an error in the position or order of the restart marker indicating the location of the independent area. The error detection circuit may detect whether or not the number of elements of each block exceeds a specified number of elements. The error detection circuit may detect whether the encoded image data includes a marker that is not supported by the image decoding circuit.

  Yet another aspect of the present invention is an image decoding system. This image decoding system includes an image decoding circuit according to the above-described aspect, and a host processor that requests the image decoding circuit to decode encoded image data. According to this aspect, the load applied to the host processor can be suppressed by performing the image restoration process using the search circuit and the supplement circuit in the image decoding circuit.

  The host processor may instruct the image decoding circuit to restart the decoding process when receiving a notice of completion of supplementation of the dummy image from the image decoding circuit. According to this aspect, after the image decoding circuit supplements the dummy image, the decoding of the image data of the part determined to be normal can be resumed.

  Yet another embodiment of the present invention is an electronic device. This electronic device is an electronic device equipped with the image decoding system of the above-described aspect, and includes a display unit that displays an image decoded by the image decoding system. According to this aspect, since the load on the host processor regarding image decoding is small, other applications can be stably executed.

  It should be noted that any combination of the above-described components and a representation of the present invention converted between an apparatus, a method, a system, a computer program, etc. are also effective as an aspect of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, when using the image decoding circuit comprised with the hardware resource, the recoverability of the encoding image data containing an error can be improved.

  FIG. 1 is a block diagram showing a configuration of an image decoding system 500 in the embodiment of the present invention. The image decoding system 500 includes an image decoding circuit 100 and a CPU 200. The image decoding circuit 100 and the CPU 200 are connected by a bus. The image decoding circuit 100 is a hardware resource that decodes encoded image data based on a certain rule and restores the original image. The image decoding circuit 100 may be configured to be integrated on a semiconductor substrate. Details of the image decoding circuit 100 will be described later.

  The CPU 200 controls the entire electronic device mounted. With respect to image decoding, in order to request the image decoding circuit 100 to decode encoded image data CI input from a communication interface (not shown) or a recording medium, the encoded image data CI is output to the image decoding circuit 100. Also, the decoded image DI decoded by the image decoding circuit 100 is received and output to a display unit (not shown). In addition to the exchange of image data, the image decoding circuit 100 and the CPU 200 have a function of exchanging control signals for recovery processing when a code error is detected during decoding. Details of this exchange of control signals will also be described later.

  FIG. 2 is a block diagram illustrating details of the image decoding circuit 100 in the embodiment. In the following, an example in which the image decoding circuit 100 is a dedicated hardware resource for decoding JPEG-compressed encoded image data will be described. The image decoding circuit 100 includes a marker detection circuit 12, an entropy decoding circuit 16, an assembly circuit 20, an inverse quantization circuit 24, an inverse DCT (Discrete Cosine Transform) circuit 26, a restart marker search circuit 28, and a supplement circuit 30.

  The marker detection circuit 12 detects a marker from the bit stream of the input encoded image data CI. The markers include SOI (Start Of Image), EOI (End OF Image), and a restart marker described later. In JPEG, it is described in 16 bits and starts with “11111111”. Based on the detected marker, the marker detection circuit 12 uses the start position and end position of the image in the stream, the end position of the ECS (Entropy-Coded Segment), etc. as control signals, and the subsequent entropy decoding circuit 16, assembly circuit 20, and inverse Notify the quantization circuit 24 and the inverse DCT circuit 26.

  The marker detection circuit 12 includes a first error detection circuit 14. When the first error detection circuit 14 detects an NG marker that cannot be processed other than the marker that can be used in the image decoding circuit 100, the first error detection circuit 14 notifies the CPU 200 to that effect and interrupts at least the entropy decoding circuit 16 and the assembly circuit 20. Instruct.

  The first error detection circuit 14 also informs the CPU 200 when the modulo value of a restart marker described later is invalid, and when the restart marker is detected before the normal position and cannot be detected at the normal position. Notice. Further, when an EOI (End OF Image) marker is detected before the normal position, the CPU 200 is notified of this. In any case, at least the assembly circuit 20 and the entropy decoding circuit 16 are instructed to interrupt the processing. Since the interval between restart markers and the number of frame elements are given as header information, it can be easily determined in the same manner as the number of block elements.

  The entropy decoding circuit 16 decodes the entropy-encoded image data with reference to a code table given in advance. For example, Huffman encoded image data is decoded with reference to a predetermined Huffman table. The entropy decoding circuit 16 includes a second error detection circuit 18. The second error detection circuit 18 compares the entropy code described in the code table with the entropy code in the stream, and detects a code that does not exist in the code table. If detected, the CPU 200 is notified of this, and at least the marker detection circuit 12 and the assembly circuit 20 are instructed to interrupt the processing.

  The assembly circuit 20 assembles the entropy-decoded bit string in units of blocks. In order to reduce the amount of calculation, the image is divided into blocks and encoded. For example, a unit block is composed of vertical 8 × horizontal 8 = 64. Hereinafter, this example will be described. The block represents the direct current component of the DCT coefficient in the upper left corner, and the other DCT coefficients represent the alternating current component. As it approaches the lower right corner, the DCT coefficient of the high frequency component is arranged from the DCT coefficient of the low frequency component. In order to give priority to the low-frequency component, scanning is performed zigzag from the upper left corner and encoded. On the contrary, the assembly circuit 20 assembles the DCT coefficients in a zigzag manner.

  The assembly circuit 20 includes a third error detection circuit 22. The third error detection circuit 22 notifies the CPU 200 of the fact that each constructed block exceeds the prescribed number of elements, or exceeds 64 in the above-described example, and processes at least the marker detection circuit 12 and the entropy decoding circuit 16. Instruct to interrupt.

  The inverse quantization circuit 24 inversely quantizes the DCT coefficients assembled in block units with reference to a quantization table given prior to the DCT coefficients. The inverse DCT circuit 26 restores a partial image corresponding to each block by performing inverse DCT on the inversely quantized coefficient. Then, if the blocks constituting the unit frame are combined, a decoded original image is obtained. When this series of decoding processes is performed for each of the Y component, the Cb component, and the Cr component, a color image can be restored. Instead of the Y component, Cb component and Cr component, the R component, G component and B component may be used, or another display system may be used.

  When the restart marker search circuit 28 is requested to search for the restart marker by the CPU 200, the restart marker search circuit 28 searches for the next restart marker appearing in the marker detection circuit 12 and returns the search result to the CPU 200. The replenishment circuit 30 replenishes the dummy image between the replenishment start position and the end position instructed by the CPU 200. As the dummy image, for example, plain image data such as blue or black can be transmitted.

  The CPU 200 issues at least three types of instructions. That is, the next restart marker search instruction, dummy image transmission instruction, and decoding restart instruction. When the CPU 200 issues a search instruction for the next restart marker to the restart marker search circuit 28, the period until the restart marker search circuit 28 searches for the next restart marker, the marker detection circuit 12 and the entropy decoding circuit 16 And instructs the assembly circuit 20 to resume decoding. The decoding restart instruction is issued to at least the marker detection circuit 12, the entropy decoding circuit 16, and the assembly circuit 20.

  Next, details of the restart marker will be described. In JPEG, when the DCT coefficient is encoded, the DC component of each block is often close in value to the adjacent block. Therefore, the blocks after the reference block are represented by difference information from the previous block. The It is encoded by a DPCM (Differential Pulse Code Modulation) method or the like. The AC component is encoded independently for each block.

  If an error occurs in the DC component of the reference block, the DC component of the subsequent blocks will become an error. Therefore, blocks including basic data to be used as a reference when encoding with difference information are provided at predetermined intervals. The restart marker represents the position of the block serving as the re-reference. The predetermined interval can be freely set by the designer. The restart marker is also described with 16 bits, starts with “111111111101”, and the modulo value is described with the remaining 4 bits. The modulo value indicates the remainder when an integer is divided by an integer.

  FIG. 3 shows an image in which a restart marker is set. In the image of FIG. 3, the block is composed of 6 × 8 × 42. The block MB1 in the upper left corner is a reference block. In this image, one restart marker is set for every five blocks. Accordingly, eight restart markers are set. The lower 4 bits of the restart marker are described by a modulo value of 8, and a value of 0 to 7 is described. The restart marker increments from 0 to 7, and returns to 0 when it reaches 7. In FIG. 3, it is described as RST0 to RST7.

  FIG. 3 shows a state where an error has occurred in the encoded image data stream and a bit string similar to the bit string of the restart marker RST5 appears by chance. The restart marker RST5a indicates an accidental appearance due to an error, and the restart marker RST5b indicates a normal one. As described above, when the third error detection circuit 22 detects a restart marker RST5a that is different from the normal order, the third error detection circuit 22 notifies the CPU 200 accordingly. Thereafter, the restart marker search circuit 28 can detect the restart marker RST2 when searching for the next restart marker in accordance with an instruction from the CPU 200. Thereby, it can be confirmed that the restart marker RST5a is an error.

  FIG. 4 shows an image obtained by decoding encoded image data including an error. FIG. 4A is an image that has been subjected to the restoration processing of the present embodiment, and FIG. 4B is an image that has been decoded by an image decoding circuit that is not equipped with a circuit for restoration of the present embodiment. . In the image of FIG. 4A, the dummy image D is replenished between the position where the error is detected and the next restart marker by the repair processing of the present embodiment. On the other hand, in FIG. 4B, the decoding process ends at the position where the error is detected.

  FIG. 5 is a flowchart for explaining the restoration processing of the image decoding system 500 in the embodiment. First, when any of the first error detection circuit 14, the second error detection circuit 18 and the third error detection circuit 22 detects an error (S10), the CPU 200 is notified (S12). The CPU 200 instructs the restart marker search circuit 28 to search for the next restart marker (S14). When the next restart marker is searched and detected (Y in S16), the restart marker search circuit 28 notifies the CPU 200 (S18).

  When receiving the notification of successful detection from the restart marker search circuit 28, the CPU 200 instructs the replenishment circuit 30 to send the dummy image D between the error detection position and the detected restart marker (S20). When the supplement of the dummy image is completed, the supplement circuit 30 notifies the CPU 200 (S22). When receiving the replenishment completion notification from the replenishment circuit 30, the CPU 200 instructs the entire image decoding circuit 100 to resume the decoding process (S24).

  As described above, according to the present embodiment, it is possible to improve recoverability when decoding encoded image data including errors such as partial data errors or including non-standard identification codes. Can do. Moreover, since error detection, restart marker detection, and dummy image transmission are configured by hardware, highly flexible repair processing can be realized without imposing a heavy load on the host processor. .

  Even if the restart marker cannot be detected in step S16 (N in S16), the start marker search circuit 28 notifies the CPU 200 of the restart marker search failure (S26). Since the CPU 200 cannot confirm that there is a normal part in the data after the error detection, the CPU 200 finishes the restoration process of the encoded image data and prepares the entire image decoding circuit 100 to prepare for the decoding of the next encoded image data. Instruct (S28).

  FIG. 6 shows a configuration of an electronic apparatus 700 equipped with the image decoding system 500 in the present embodiment. The electronic device 700 includes a battery 710, a communication unit 720, a recording unit 730, an image decoding system 500, and a display unit 740. Elements not related to image decoding are omitted. The electronic device 700 mainly includes portable devices such as a mobile phone, a digital camera, and a portable game machine. The image decoding system 500 decodes the encoded image data supplied from the communication unit 720 or the recording unit 730 and outputs the decoded image to the display unit 740.

  The image decoding system 500 is suitable for use in a field in which when the encoded image data is decoded by software, it becomes a limiting factor for the entire mounted system. The portable electronic device 700 can be said to be the field. For example, it is difficult for a host processor mounted on the portable electronic device 700 to operate at a high frequency due to factors such as battery driving. In order to decode the encoded image data at a high speed, it is suitable to perform it with hardware. Decoding with software is a limiting factor for other high-priority applications such as communication, and is likely to cause communication errors. As described above, when the image decoding system 500 of the above-described embodiment is applied to a portable electronic device, it contributes to saving power consumption and stabilizing the system. Of course, this point is not limited to portable devices, but also applies to PCs and the like.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the above embodiment, an example in which encoded image data compressed in the JPEG format is decoded has been described. In this regard, the present invention is not limited to the JPEG format, and can be applied to encoded image data in which restart markers are set at predetermined intervals. For example, even in the MPEG format, if restart markers are set at predetermined intervals, the present invention can be applied not only to repair processing within a frame but also to repair processing across frames.

  In the above-described embodiment, the CPU 200 may generate each instruction based on the software determination process by a hardware control circuit, and may be mounted on the image decoding circuit 100. Although this leads to an increase in the circuit scale of the image decoding circuit 100, the load on the host processor can be further reduced.

  In the embodiment, the example in which the three error detection circuits including the first error detection circuit 14, the second error detection circuit 18, and the third error detection circuit 22 are mounted has been described. In this regard, if at least one is mounted, the application range of the present invention is achieved. In particular, it is desirable to mount at least the second error detection circuit 18. This is because the process of detecting that data not described in the Huffman table is included is particularly important in the error detection process. Of course, by mounting the first error detection circuit 14 and the third error detection circuit 22, it is possible to detect an error that has been accidentally changed to the same bit string as the marker, etc., and to improve the accuracy of error detection. it can.

It is a block diagram which shows the structure of the image decoding system in embodiment of this invention. It is a block diagram which shows the detail of the image decoding circuit in embodiment. It is a figure which shows the image in which the restart marker was set. It is a figure which shows the image which decoded the encoding image data containing an error. It is a flowchart for demonstrating the repair process of the image decoding system in embodiment. It is a figure which shows the structure of the electronic device carrying the image decoding system in embodiment.

Explanation of symbols

  12 marker detection circuit, 14 first error detection circuit, 16 entropy decoding circuit, 18 second error detection circuit, 20 assembly circuit, 22 third error detection circuit, 24 inverse quantization circuit, 26 inverse DCT circuit, 28 restart marker Search circuit, 30 supplementary circuit, 100 image decoding circuit, 200 CPU, 300 display unit, 500 image decoding system, 700 electronic device, 710 battery, 720 communication unit, 730 recording unit, 740 display unit.

Claims (9)

An image decoding circuit that decodes encoded image data including an independent region that can be decoded within a region and a dependent region that is decoded using difference information from another region,
An error detection circuit for detecting a code error during decoding of the encoded image data;
A search circuit for searching for an identification code indicating a position of an independent region that appears next after the code error is detected;
A replenishment circuit for replenishing a predetermined dummy image between the location where the identification code is searched from the location where the code error is detected;
An image decoding circuit comprising: The error detection circuit notifies the host processor when a code error is detected,
2. The image decoding circuit according to claim 1, wherein the search circuit and the supplementary circuit start an operation in response to an instruction from the host processor.   3. The image decoding circuit according to claim 2, wherein when the error detection circuit detects a code error, the decoding process is interrupted and an instruction from the host processor is waited.   The image according to any one of claims 1 to 3, wherein the error detection circuit detects whether a code that is not included in a code table necessary for entropy decoding is included in the encoded image data. Decoding circuit.   5. The image decoding circuit according to claim 1, wherein the error detection circuit detects whether or not there is an error in a position or order of a restart marker indicating the location of the independent area. 6.   6. The image decoding circuit according to claim 1, wherein the image decoding circuit is integrated on the same semiconductor substrate. An image decoding circuit according to any one of claims 1 to 6,
A host processor that requests the image decoding circuit to decode the encoded image data;
An image decoding system comprising:   8. The image decoding system according to claim 7, wherein the host processor instructs the image decoding circuit to resume decoding processing when receiving a notice of completion of supplementation of dummy images from the image decoding circuit. 9. An electronic device equipped with the image decoding system according to claim 7 or 8,
An electronic apparatus comprising: a display unit that displays an image decoded by the image decoding system.

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