JP2006340527A - Abnormality detection method and device of battery pack - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an abnormality detection method and device capable of achieving protection against overcharge/overdischarge with a simple structure, by detecting a circuit failure even if an OR circuit or an AND circuit fails. <P>SOLUTION: This abnormality detection device comprises abnormality detection control circuits 11(1)-11(n) connected to a battery pack 18, the OR circuit 12 and the AND circuit 13 into which the outputs from the abnormality detection control circuit 11(1)-11(n) are inputted, and OR circuit 12 and the AND circuit 13, a matching circuit 14 that inputs the outputs from the abnormality detection control circuit 11(1)-11(n) and outputs a signal that indicates normality (matching) when input signals all match. The abnormality (overcharge/overdischarge) of the battery pack 18 is judged by each output of the OR circuit 12, the AND circuit 13 and the matching circuit 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an assembled battery abnormality detection method and apparatus, and more particularly, to an assembled battery abnormality detection method and apparatus that protects an overcharge / discharge of an assembled battery used in a hybrid vehicle.

2. Description of the Related Art Conventionally, a battery pack abnormality detection device that detects a battery battery overcharge or overdischarge abnormality is known.
FIG. 5 is a block diagram showing a configuration of a conventional assembled battery abnormality detection device. As shown in FIG. 5, the abnormality detection device 1 includes abnormality detection control circuits 2 (1) to 2 (n) (only four are shown in the figure), an OR circuit 3, an AND circuit 4, a switching circuit 5, A CPU 6 and a total voltage detection circuit 7 are included, and an abnormality of the assembled battery 8 is detected. The assembled battery 8 is configured by connecting n cells 8a (1) to 8a (n) (only four in the drawing) that can be charged and discharged in series, and a positive electrode terminal and a negative electrode terminal of each cell. Are connected to each of the abnormality detection control circuits 2 (1) to 2 (n).

  The abnormality detection control circuits 2 (1) to 2 (n) have a reference voltage source 9a and an abnormality detection circuit 9b (only one is shown in the figure, and the others are not shown). The voltage Vsa is output to the abnormality detection circuit 9b as a reference for the voltage between the terminals of the corresponding cells 8a (1) to 8a (n). The abnormality detection circuit 9b compares the result of comparing the first predetermined voltage Vsa × α converted from the input from the reference voltage source 9a and the voltage between the terminals of the cell with the OR circuit 3 and the AND circuit 4 when overcharge is detected. Output.

  For example, when the abnormality detection circuit 9b detects that the inter-terminal voltage of the cell has risen from the first predetermined voltage Vsa × α, it outputs an H (High) level signal indicating abnormality (overcharge). Further, when it is detected by comparing that the voltage between the terminals of the cell has dropped below the first predetermined voltage Vsa × α, an L (Low) level signal indicating normality is output.

  In addition, the abnormality detection circuit 9b converts the comparison value to compare with the voltage between the terminals of the cell when overcharge is detected, and compares the result with the second predetermined voltage Vsa × β. Output to circuit 4. For example, when the abnormality detection circuit 9b detects that the inter-terminal voltage of the cell has risen above the second predetermined voltage Vsa × β, it outputs an H level signal indicating normality. Further, when it is detected by comparing that the voltage between the terminals of the cell has dropped below the second predetermined voltage Vsa × β, an L level signal indicating an abnormality (over discharge) is output.

  6A is an explanatory diagram showing a graph of the output of the abnormality detection circuit when overcharge is detected when an abnormality is detected by the abnormality detection device of FIG. 5, and FIG. 6B is an explanatory diagram showing the abnormality detection circuit when overdischarge is detected. It is explanatory drawing which shows an output with a graph. As shown in FIG. 6, when the cell voltage (Vb) is equal to or higher than Vsa × α, the abnormality detection circuit 9b outputs an H level (abnormal, that is, overcharge), and the cell voltage (Vb) is Vsa × α. In the following cases, L level (normal) is output (see (a)). The abnormality detection circuit 9b outputs an H level (normal) when the cell voltage (Vb) is equal to or higher than Vsa × β, and an L level (abnormal) when the cell voltage (Vb) is equal to or lower than Vsa × α. Is output (see (b)).

The logical sum circuit 3 indicates an abnormality (overcharge) via the switching circuit 5 when any one of the abnormality detection control circuits 2 (1) to 2 (n) is inputted at the time of overcharge detection. An H level signal is output to the CPU 6. Further, when all of the abnormality detection control circuits 2 (1) to 2 (n) are L level signals, the L level signal indicating normality is output to the CPU 6.
The AND circuit 4 indicates an abnormality (overdischarge) via the switching circuit 5 when any one of the abnormality detection control circuits 2 (1) to 2 (n) is inputted at the time of overdischarge detection. An L level signal is output to the CPU 6. Further, when all of the abnormality detection control circuits 2 (1) to 2 (n) are H level signals, an H level signal indicating normality is output to the CPU 6.

  The CPU 6 performs charge / discharge control of the assembled battery 8 based on the voltage value of the assembled battery 8 input from the total voltage detection circuit 7, but the cell 8 a (1) is calculated by the control logic from the input signal from the switching circuit 5. ) To 8a (n), when it is determined that an abnormality (overcharge / overdischarge) has occurred, charging / discharging of the assembled battery 8 is prohibited.

  That is, when the signal input from the switching circuit 5 when the overcharge is detected is at the H level, the cell is abnormal (overcharge), and when the signal is at the L level, the cell is normal (not overcharge). If the signal input from the switching circuit 5 at the time of overdischarge detection is L level, the cell is abnormal (overdischarge), and if it is H level, the cell is normal (not overdischarge). to decide. When both the overcharge detection time and the overdischarge detection time are normal, the CPU 6 determines that the cell is normal and controls charging / discharging of the assembled battery 8 to protect overcharge and overdischarge.

  FIG. 7 is a flowchart showing a flow of control processing by the abnormality detection apparatus of FIG. As shown in FIG. 7, when control is performed by the conventional assembled battery abnormality detection device 1, first, after overcharge detection setting is performed (step S <b> 1), whether or not the input of the switching circuit 5 is “L level”. Is determined (step S2). When the input of the switching circuit 5 is “L level” (yes), after overdischarge detection setting is performed (step S3), it is determined whether or not the input of the switching circuit 5 is “H level” (step S4). When the input of the switching circuit 5 is “H level” (yes), the process returns to step S1 and the process is repeated.

  If the input of the switching circuit 5 is not "L level" in step S2 (no), the overcharge state is determined and the charge is prohibited (step S5), and then the process proceeds to step S3 to perform overcharge detection setting. In step S4, when the input of the switching circuit 5 is not "H level" (no), it is determined as an overdischarge state and discharge is prohibited (step S6), and then the process returns to step S1 and the process is repeated.

That is, the conventional assembled battery abnormality detection device 1 has a configuration in which an abnormality output circuit for detecting abnormality (overcharge / overdischarge) of an assembled battery composed of a plurality of cells is composed of an OR circuit and an AND circuit. Have.
As a device for detecting such an abnormality of an assembled battery, for example, an “assembled battery abnormality detecting device” (see Patent Document 1) is known.
JP 2004-312836 A

  However, in the above-described conventional abnormality detection device, when a failure occurs such that the OR circuit 3 outputs an L level when overcharge is detected, the abnormality detection control circuits 2 (1) to 2 (n) are abnormal ( Even if an H level signal indicating overcharge) is output, an L level signal indicating normality is output from the switching circuit 5 to the CPU 6. That is, in the conventional abnormality detection device, it is determined that the cell voltage is normal despite being abnormal (overcharge), and control is performed so as not to stop charging, so that protection against overcharge is performed. There is no.

  In addition, when a failure occurs such that the AND circuit 4 outputs an H level when overdischarge is detected, an L level signal indicating that the abnormality detection control circuits 2 (1) to 2 (n) are abnormal (overdischarge) is output. Even when output, the switching circuit 5 outputs an H level signal indicating normality to the CPU 6. That is, in the conventional abnormality detection device, it is judged that the cell voltage is normal despite being abnormal (overdischarge), and control is performed so as not to stop the discharge, so that protection against overdischarge is performed. There is no.

That is, if the abnormality detection circuit of a single cell fails for some reason and the output of the logical sum circuit or logical product circuit is fixed to a normal value, the abnormal voltage of the cell cannot be detected, and overcharge / overcharge It was inevitable that the battery would be discharged.
SUMMARY OF THE INVENTION An object of the present invention is to provide an abnormality detection method for an assembled battery that can realize protection against overcharge / discharge with a simple configuration by detecting a circuit failure even if an OR circuit or an AND circuit fails. And providing an apparatus.

  In order to achieve the above object, an abnormality detection method for an assembled battery according to the present invention determines an abnormality based on an OR circuit to which an output from an abnormality detection control circuit connected to the assembled battery is input and an output from the AND circuit. A first process that performs an output and an output from the abnormality detection control circuit receives a second signal that outputs a signal indicating normality (match) when all the input signals match. A process, and a process of determining an abnormality (overcharge / overdischarge) of the assembled battery from two processing results of the first process and the second process.

  An abnormality detection apparatus for an assembled battery according to the present invention includes an abnormality detection control circuit connected to the assembled battery, an OR circuit and an AND circuit to which an output from the abnormality detection control circuit is input, and the OR circuit. And an output from the abnormality detection control circuit in the same manner as the logical product circuit, and a coincidence circuit that outputs a signal indicating normality (coincidence) when all the input signals coincide with each other, the logical sum circuit, An abnormality (overcharge / overdischarge) of the assembled battery is determined based on the outputs of the AND circuit and the coincidence circuit.

According to the present invention, the first process determines an abnormality based on the output from the OR circuit and the AND circuit to which the output from the abnormality detection control circuit connected to the assembled battery is input, and the second process When the output from the abnormality detection control circuit is input and all the input signals match, the abnormality is determined by the output from the coincidence circuit that outputs a signal indicating normality (coincidence), and the first process and the second process From these two processing results, the abnormality (overcharge / overdischarge) of the assembled battery is determined.
For this reason, even if a logical sum circuit or a logical product circuit fails, it is possible to realize protection against overcharge / discharge with a simple configuration by detecting a circuit failure.
The assembled battery abnormality detection apparatus according to the present invention can realize the assembled battery abnormality detection method.

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an assembled battery abnormality detection device according to an embodiment of the present invention. As shown in FIG. 1, the abnormality detection device 10 includes abnormality detection control circuits 11 (1) to 11 (n) (only four are shown in the figure), an OR circuit 12, an AND circuit 13, a coincidence circuit 14, A switching circuit 15, a CPU 16, and a total voltage detection circuit 17 are included, and an abnormality of the assembled battery 18 is detected. The assembled battery 18 is configured by connecting n cells 19 (1) to 19 (n) (only four are shown in the figure) that can be charged / discharged in series, and a positive terminal and a negative terminal of each cell. Are connected to each of the abnormality detection control circuits 11 (1) to 11 (n).

  The abnormality detection control circuits 11 (1) to 11 (n) have a reference voltage source 20 and an abnormality detection circuit 21 (only one is shown in the figure, and the others are not shown). The voltage Vsa is output to the abnormality detection circuit 21 as a reference for the voltage between the terminals of the corresponding cells 19 (1) to 19 (n). The abnormality detection circuit 21 compares the result of comparing the first predetermined voltage Vsa × α obtained by converting the input from the reference voltage source 20 and the voltage between the terminals of the cell with the OR circuit 12 and the AND circuit 13 when overcharge is detected. Output.

  For example, the abnormality detection circuit 21 outputs an H (High) level signal indicating abnormality (overcharge) when detecting that the voltage between the terminals of the cell has risen above the first predetermined voltage Vsa × α. Further, when it is detected by comparing that the voltage between the terminals of the cell has dropped below the first predetermined voltage Vsa × α, an L (Low) level signal indicating normality is output.

  Further, the abnormality detection circuit 21 converts the comparison value to compare with the voltage between the terminals of the cell when overcharge is detected, and compares the result with the second predetermined voltage Vsa × β. Output to the circuit 13. For example, when the abnormality detection circuit 21 detects that the inter-terminal voltage of the cell has risen above the second predetermined voltage Vsa × β, it outputs an H level signal indicating normality. Further, when it is detected by comparing that the voltage between the terminals of the cell has dropped below the second predetermined voltage Vsa × β, an L level signal indicating an abnormality (over discharge) is output.

  The abnormality detection circuit 21 outputs an H level (abnormality, that is, overcharge) when the cell voltage (Vb) is Vsa × α or more, and an L level when the cell voltage (Vb) is Vsa × α or less. (Normal) is output (see FIG. 6, (a)). The abnormality detection circuit 21 outputs an H level (normal) when the cell voltage (Vb) is equal to or higher than Vsa × β, and an L level (abnormal, when the cell voltage (Vb) is equal to or lower than Vsa × α. That is, overdischarge) is output (see FIG. 6, (b)).

The logical sum circuit 12 indicates an abnormality (overcharge) via the switching circuit 15 when any one of the abnormality detection control circuits 11 (1) to 11 (n) is inputted at the time of overcharge detection. An H level signal is output to the CPU 16. Further, when all of the abnormality detection control circuits 11 (1) to 11 (n) are L level signals, an L level signal indicating normality is output to the CPU 16.
The AND circuit 13 indicates an abnormality (overdischarge) via the switching circuit 15 when any one of the abnormality detection control circuits 11 (1) to 11 (n) is input upon detection of overdischarge. An L level signal is output to the CPU 16. Further, when all of the abnormality detection control circuits 11 (1) to 11 (n) are H level signals, an H level signal indicating normality is output to the CPU 16.

  The CPU 16 performs charge / discharge control of the assembled battery 18 on the basis of the voltage value of the assembled battery 18 input from the total voltage detection circuit 17, but the cell 19 (1) is calculated from the input signal from the switching circuit 15 by the control logic. ) To 19 (n), when it is determined that an abnormality (overcharge / overdischarge) has occurred, charging / discharging of the assembled battery 18 is prohibited.

  That is, when the signal input from the switching circuit 15 at the time of overcharge detection is at the H level, the CPU 16 indicates that the cell is abnormal (overcharge), and when the signal is at the L level, the cell is normal (not overcharge). If the signal input from the switching circuit 15 at the time of overdischarge detection is L level, the cell is abnormal (overdischarge), and if it is H level, the cell is normal (not overdischarge). to decide. When both the overcharge detection time and the overdischarge detection time are normal, the CPU 16 determines that the cell is normal and controls charging / discharging of the assembled battery 18 to protect overcharge and overdischarge.

This abnormality detection device 10 has a coincidence circuit 14, and the output of the abnormality detection circuit 21 is not only inputted to the logical sum circuit 12 and the logical product circuit 13 but also inputted to the coincidence circuit 14 in the same manner.
The coincidence circuit 14 outputs an H level signal indicating normality (coincidence) to the CPU 16 when all the input signals from the abnormality detection control circuits 11 (1) to 11 (n) coincide. In other words, when the abnormality detection control circuits 11 (1) to 11 (n) all input normal level L signals to the coincidence circuit 14 when overcharge is detected, the CPU 16 outputs an H level signal indicating normality (coincidence). Output to. However, if even one coincidence circuit 14 is input with an H level signal indicating abnormality (overcharge), an L level signal indicating abnormality (mismatch) is output to the CPU 16.

Further, when the abnormality detection control circuits 11 (1) to 11 (n) all input normal-level H signals to the coincidence circuit 14 when overdischarge is detected, the CPU 16 outputs normal-level (coincidence) high-level signals. Output to. However, if at least one L level signal indicating abnormality (overdischarge) is input to the coincidence circuit 14, an L level signal indicating abnormality (mismatch) is output to the CPU 16.
The CPU 16 generates an abnormality (overcharge / overdischarge) in the cells 19 (1) to 19 (n) by the calculation by the control logic from the input signal from the switching circuit 15 and the input signal from the coincidence circuit 14. If it is determined that the battery pack 18 is charged, charging / discharging of the assembled battery 18 is prohibited.

  FIG. 2 is a flowchart showing a flow of control processing by the abnormality detection apparatus of FIG. As shown in FIG. 2, when control is performed by the assembled battery abnormality detection device 10, first, overcharge detection setting is performed (step S <b> 101), and then it is determined whether or not the input of the switching circuit 15 is “L level”. (Step S102). When the input of the switching circuit 15 is “L level” (yes), it is determined whether or not the input of the coincidence circuit 14 is “H level” (step S103). When the input of the coincidence circuit 14 is “H level” (yes), overdischarge detection setting is performed (step S104).

  Thereafter, it is determined whether or not the input of the switching circuit 15 is at “H level” (step S105). When the input of the switching circuit 15 is “H level” (yes), it is determined whether or not the input of the coincidence circuit 14 is “H level” (step S106). When the input of the coincidence circuit 14 is “H level” (yes), the process returns to step S101 and the process is repeated.

  If the input of the switching circuit 15 is not “L level” in step S102 (no), and if the input of the coincidence circuit 14 is not “H level” (no) in step S103, it is determined that there is an overcharge state with an abnormality. Then, after prohibiting charging (step S107), the process proceeds to step S104 to perform overcharge detection setting. Further, when the input of the switching circuit 15 is not “H level” at step S105 (no) and when the input of the coincidence circuit 14 is not “H level” at step S106 (no), an abnormal overdischarge state is detected. In step S108, the process returns to step S101 and the process is repeated.

  That is, the CPU 16 determines that the input signal from the switching circuit 15 is at L level and the input signal from the coincidence circuit 14 is at H level when overcharge is detected. However, when the input signal from the switching circuit 15 is at the H level or the input signal from the coincidence circuit 14 is at the L level, it is determined that the cell is abnormal (overcharge) and charging of the assembled battery 18 is prohibited. In order to protect against overcharge. Therefore, in the case of a failure in which the logical sum circuit 12 outputs an L level, it is determined that the output of the coincidence circuit 14 is abnormal (overcharge) by outputting an L level indicating an abnormality. Realize protection.

The CPU 16 determines that the input signal from the switching circuit 15 is at the H level when the overdischarge is detected and the input signal from the coincidence circuit 14 is at the H level. However, if the input signal from the switching circuit 15 is at the L level or the input signal from the coincidence circuit 14 is at the L level, it is determined that the cell is abnormal (overdischarge) and the discharge of the assembled battery 18 is prohibited. In order to protect against overdischarge. Accordingly, in the case of a failure in which the AND circuit 13 outputs an H level, the output of the coincidence circuit 14 is determined to be abnormal (over discharge) by outputting an L level indicating abnormality, and the over discharge is detected. Realize protection.
Furthermore, by appropriately performing the control logic, it is possible to judge overcharge / overdischarge / circuit failure and limit charging / discharging in the event of a circuit failure, so that charging / discharging is not prohibited without discrimination. Charge / discharge control of the assembled battery 18 can be realized.

  3 is a flowchart (part 1) showing a flow of control processing for determining a circuit failure by the abnormality detection device of FIG. 1, and FIG. 4 is a flow of control processing for determining a circuit failure by the abnormality detection device of FIG. It is the flowchart (the 2) which shows. As shown in FIGS. 3 and 4, when control is performed by the battery pack abnormality detection device 10, first, it is determined whether or not the input value of the total voltage detection circuit 17 is “overcharge value or less” (step S <b> 201). . As a result of the determination, if the input value of the total voltage detection circuit 17 is “less than the overcharge value” (yes), after the overcharge detection setting is performed (step S202), is the input of the switching circuit 15 “L level”? It is determined whether or not (step S203). As a result of the determination, if the input of the switching circuit 15 is “L level” (yes), overcharge is not detected (overcharge detection = none) (step S204).

Thereafter, it is determined whether or not the input of the coincidence circuit 14 is “H level” (step S205). As a result of the determination, if the input of the coincidence circuit 14 is “H level” (yes), it is determined that there is no abnormality (abnormality = none) (step S206).
Next, it is determined whether there is overcharge detection (a) or not (b) and whether there is an abnormality (c) or not (d) (step S207).

  If the input value of the total voltage detection circuit 17 is not “overcharge value or less” in step S201 (no), the overcharge state is determined and charge inhibition processing is performed (step S208), and then the process proceeds to step S201. Return. In step S203, when the input of the switching circuit 15 is not “L level” (no), overcharge is detected (overcharge detection = present) (step S209), and the process proceeds to step S205. In step S205, if the input of the coincidence circuit 14 is not “H level” (no), it is determined that there is an abnormality (abnormality = present) (step S210), and then the process proceeds to step S207.

  As a result of the determination in step S207, if “overcharge detection = (a) and abnormality = (c)”, the overcharge state is determined and charge prohibition processing is performed (case 1), and “overcharge detection = In the case of (b) and abnormality = (c) ”, it is determined that there is a circuit failure and the charge restriction process is performed (case 2).“ Overcharge detection = (a) and abnormality = (d) ” In this case, it is determined that the battery is in an overcharge state, and charging prohibition processing is performed (case 3). If “overcharge detection = (b) and abnormality = (d)”, it is determined that the battery is normal (case 4).

  After any one of the cases 1 to 4, it is determined whether or not the input value of the total voltage detection circuit 17 is “over discharge value or more” (step S211). As a result of the determination, if the input value of the total voltage detection circuit 17 is “over charge value or more” (yes), after the overdischarge detection setting is performed (step S212), is the input of the switching circuit 15 “H level”? It is determined whether or not (step S213). As a result of the determination, if the input of the switching circuit 15 is “H level” (yes), overdischarge is not detected (overdischarge detection = none) (step S214).

Thereafter, it is determined whether or not the input of the coincidence circuit 14 is at “H level” (step S215). As a result of the determination, if the input of the coincidence circuit 14 is “H level” (yes), it is determined that there is no abnormality (abnormality = none) (step S216).
Next, it is determined whether there is overdischarge detection (a) or not (b) and whether there is an abnormality (c) or not (d) (step S217).

  In step S211, if the input value of the total voltage detection circuit 17 is not “over discharge value” (no), it is determined as an over discharge state and discharge prohibition processing is performed (step S218), and then the process proceeds to step S201. Return. If the input of the switching circuit 15 is not “H” level in step S213 (no), overdischarge is detected (overdischarge detected = present) (step S219), and the process proceeds to step S215. In step S215, if the input of the coincidence circuit 14 is not “H level” (no), it is determined that there is an abnormality (abnormality = present) (step S220), and the process proceeds to step S217.

  As a result of the determination in step S217, if “overdischarge detection = (a) and abnormality = (c)”, it is determined as an overdischarge state and discharge inhibition processing is performed (case 5), and “overdischarge detection = In the case of (b) and abnormality = (c) ”, it is determined that there is a circuit failure and discharge restriction processing is performed (case 6).“ Overdischarge detection = (a) and abnormality = (d) ” In this case, it is determined that the state is an overdischarge state and discharge prohibition processing is performed (case 7). When “overdischarge detection = (b) and abnormality = (d)”, it is determined that the state is normal (case 8).

After any process from Case 5 to Case 8, the process returns to Step S201 and the process is repeated.
That is, when overcharge is detected, the CPU 16 compares and determines whether or not the voltage value of the entire assembled battery 18 is equal to or higher than the overcharge value from the input signal from the total voltage detection circuit 17. Judging the state of charge, the charging of the battery pack 18 is prohibited. On the other hand, if it is not equal to or higher than the overcharge value, it is determined that the voltage of the entire assembled battery 18 is normal, and it is subsequently determined whether an abnormality (overcharge) has occurred in the cells 19 (1) to 19 (n). .

  The CPU 16 stores “overcharge detected = present” when the input signal from the switching circuit 15 is at the H level, and stores “overcharge detected = none” when the input signal is at the L level. Further, “abnormality = present” is stored when the input signal from the coincidence circuit 14 is L level, and “abnormality = none” is stored when the input signal is H level.

  In the case of “overcharge detection = present” and “abnormality = present” (case 1), the OR circuit 12 detects an abnormality (overcharge) and the coincidence circuit 14 detects an abnormality (mismatch). Therefore, it is determined that the battery is overcharged (no circuit failure) and charging of the battery pack 18 is prohibited. In the case of “overcharge detection = none” and “abnormality = present” (case 2), the coincidence circuit 14 is abnormal even though the logical sum circuit 12 detects normality (no overcharge). Since (mismatch) is detected, it is determined that there is a circuit failure in the OR circuit 12 or the coincidence circuit 14, and charging of the assembled battery 18 is limited.

  In the case of “overcharge detection = present” and “abnormality = none” (case 3), the coincidence circuit 14 is normal even though the OR circuit 12 detects an abnormality (overcharge) ( Match). Since the voltage value of the entire assembled battery 18 is determined to be normal from the input signal of the total voltage detection circuit 10, all of the cells 19 (1) to 19 (n) are not overcharged. Therefore, since it is contradiction that the coincidence circuit 14 detects normality (coincidence), it can be determined that the coincidence circuit 14 has failed. Therefore, it is determined that the battery is overcharged (there is a circuit failure) from “overcharge detected = present”, which is the output of the switching circuit 15, and charging of the assembled battery 18 is prohibited.

  In the case of “overcharge detection = none” and “abnormality = none” (case 4), the OR circuit 12 detects normal (no overcharge) and the match circuit 14 detects normal (match) Therefore, it is determined that the battery is in a normal state (no circuit failure), and charging of the battery pack 18 is not limited.

  Further, when overdischarge is detected, the CPU 16 compares the input signal from the total voltage detection circuit 17 to determine whether or not the voltage value of the entire assembled battery 18 is equal to or lower than the overdischarge value. Therefore, the discharge of the assembled battery 18 is prohibited. If it is equal to or higher than the overdischarge value, it is determined that the voltage of the assembled battery 18 as a whole is normal, and it is subsequently determined whether an abnormality (overdischarge) has occurred in the cells 11 (1) to 11 (n).

  The CPU 16 stores “overdischarge detected = present” when the input signal from the switching circuit 15 is at the L level, and stores “overdischarge detected = none” when the input signal is at the H level. Further, “abnormality = present” is stored when the input signal from the coincidence circuit 14 is L level, and “abnormality = none” is stored when the input signal is H level.

  In the case of “overdischarge detection = present” and “abnormality = present” (case 5), the AND circuit 13 detects an abnormality (overdischarge), and the coincidence circuit 14 detects an abnormality (mismatch). Therefore, it is determined that the battery is overdischarged (no circuit failure), and discharge of the battery pack 18 is prohibited. In the case of “overdischarge detection = none” and “abnormality = present” (case 6), the coincidence circuit 14 is abnormal even though the AND circuit 13 detects normality (no overdischarge). Since (mismatch) is detected, it is determined that there is a circuit failure in the logical product circuit 13 or the coincidence circuit 14, and the discharge of the assembled battery 18 is limited.

  In the case of “overdischarge detection = present” and “abnormality = none” (case 7), the coincidence circuit 14 is normal even though the AND circuit 13 detects an abnormality (overdischarge). Match). Since the voltage value of the entire assembled battery 18 is determined to be normal from the input signal of the total voltage detection circuit 17, all of the cells 19 (1) to 19 (n) are not overdischarged. Accordingly, since it is contradiction that the matching circuit 14 detects normality (matching), it can be determined that the matching circuit 14 has failed. From this, it is judged from the output of the switching circuit 15 “overdischarge detected = present” that the battery is overdischarged (there is a circuit failure), and the discharge of the assembled battery 18 is prohibited.

  That is, the CPU 16 performs an operation based on the control logic from the two input signals from the logical sum circuit 12 and the logical product circuit 13 and the input signal from the coincidence circuit 14, and determines that an abnormality has occurred in the assembled battery 18. In this case, it functions as a determination means for prohibiting charging / discharging of the assembled battery 18.

  In this way, by inputting the abnormal output signal to the coincidence circuit 14 and outputting it to the CPU 16, it is possible to detect that the abnormality detection circuit 21 is out of order with a simple configuration. By performing the failure detection, it is possible to detect a circuit failure even if the logical sum circuit 12 or the logical product circuit 13 breaks down. Therefore, protection against overcharge / overdischarge of the assembled battery 18 can be guaranteed. it can. In addition, the output of the abnormality detection circuit 21 and the output of the coincidence circuit 14 are input to the CPU 16 and processed by the control logic to determine the type of abnormality of overcharge / overdischarge / circuit failure, and the circuit failure In this case, it is possible to achieve efficient charge / discharge control of the assembled battery 18 without restricting charge / discharge indiscriminately by restricting charge / discharge.

Thus, according to the present invention, in the first process, an abnormality is determined by each of the outputs from the OR circuit and the AND circuit to which the output from the abnormality detection control circuit connected to the assembled battery is input, By the processing of 2, the output from the abnormality detection control circuit is input, and when all the input signals match, the abnormality is determined by the output from the matching circuit that outputs a signal indicating normality (matching), and the first processing and Since an abnormality (overcharge / overdischarge) of the assembled battery is determined from the two processing results of the second processing, by detecting a circuit failure even if the logical sum circuit or the logical product circuit fails, Protection against overcharge / discharge can be realized with a simple configuration.
The assembled battery abnormality detection apparatus according to the present invention can realize the assembled battery abnormality detection method.

It is a block diagram which shows the structure of the abnormality detection apparatus of the assembled battery which concerns on one embodiment of this invention. It is a flowchart which shows the flow of the control processing by the abnormality detection apparatus of FIG. FIG. 3 is a flowchart (part 1) illustrating a flow of control processing for determining a circuit failure by the abnormality detection device of FIG. 1. FIG. 3 is a flowchart (No. 2) showing a flow of a control process for determining a circuit failure by the abnormality detection device of FIG. 1. It is a block diagram which shows the structure of the conventional abnormality detection apparatus of an assembled battery. 5A is an explanatory diagram showing a graph of the output of the abnormality detection circuit when overcharge is detected, and FIG. 5B is a graph showing the output of the abnormality detection circuit when overdischarge is detected. It is explanatory drawing shown. It is a flowchart which shows the flow of the control processing by the abnormality detection apparatus of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Abnormality detection apparatus 11 (1) -11 (n) Abnormality detection control circuit 12 OR circuit 13 AND circuit 14 Matching circuit 15 Switching circuit 16 CPU
17 Total voltage detection circuit 18 Battery pack 19 (1) to 19 (n) Cell 20 Reference voltage source 21 Abnormality detection circuit

Claims (6)

A first process for determining an abnormality based on an output from an OR circuit and an AND circuit to which an output from an abnormality detection control circuit connected to the assembled battery is input;
A second process for determining an abnormality based on an output from a coincidence circuit that outputs a signal indicating normality (coincidence) when the output from the abnormality detection control circuit is inputted and all the input signals coincide;
An assembled battery abnormality detection method comprising: determining an abnormality (overcharge / overdischarge) of the assembled battery from two processing results of the first process and the second process.   2. The assembled battery according to claim 1, wherein charging and discharging of the assembled battery is prohibited when it is determined from the two processing results of the first process and the second process that an abnormality has occurred in the assembled battery. Anomaly detection method.   It is determined from the two processing results of the first processing and the second processing whether the type of abnormality is overcharge / overdischarge / circuit failure, and charging / discharging is limited when a circuit failure occurs. Item 6. An abnormality detection method for an assembled battery according to Item 1. An abnormality detection control circuit connected to the battery pack;
An OR circuit and an AND circuit to which an output from the abnormality detection control circuit is input; and
Similar to the logical sum circuit and the logical product circuit, the output from the abnormality detection control circuit is input, and when all the input signals match, it has a matching circuit that outputs a signal indicating normality (match),
An assembled battery abnormality detection device that determines abnormality (overcharge / overdischarge) of the assembled battery based on outputs of the logical sum circuit, the logical product circuit, and the coincidence circuit.   When it is determined that an abnormality has occurred in the assembled battery by performing an operation based on control logic from the input signal from the logical sum circuit and the logical product circuit and the input signal from the coincidence circuit, The assembled battery abnormality detection device according to claim 4, further comprising a determination unit that prohibits charging / discharging of the battery pack.   6. The assembled battery abnormality detection device according to claim 5, wherein in the calculation by the control logic, it is determined whether the type of abnormality is overcharge / overdischarge / circuit failure, and charging / discharging is limited when the circuit failure occurs. .

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