JP2006340211A - Motion compensation prediction apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motion compensation prediction apparatus in which motion compensation prediction processing is performed at high speed by interpolating pixels of 1/2 precision and pixels of 1/4 precision between horizontally or vertically continuous integer pixels through one time of pipeline processing. <P>SOLUTION: A motion compensation prediction apparatus for performing motion compensation prediction of decimal precision comprises: a pixel interpolation section 47 for applying FIR filter processing to horizontally or vertically continuous integer pixels to simultaneously interpolate pixels of 1/2 precision and pixels of 1/4 precision between adjacent two integer pixels within one clock; a frame memory 48 for recording the pixels of decimal precision interpolated by the pixel interpolation section 47; and a motion compensation prediction section 49 for performing motion compensation prediction using the pixels of decimal precision recorded in the frame memory 48. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a motion compensation prediction apparatus that performs motion compensation prediction with decimal precision, and more particularly to a technique for interpolating ¼ precision pixels.

  In recent years, digitalization of AV information has progressed and devices capable of digitizing and handling video signals are becoming widespread. Since a video signal has an enormous amount of information, encoding is generally performed while reducing the amount of information in consideration of recording capacity and transmission efficiency. As a video signal encoding technique, an international standard established by a working group called MPEG (Moving Picture Experts Group) is widely used.

  In MPEG, motion compensation prediction using a motion vector is used. Motion-compensated prediction is a method of efficiently compressing by detecting how elements reflected between consecutive frames have moved. That is, an encoded image is divided into processing units called macroblocks of 16 pixels in the vertical direction × 16 pixels in the horizontal direction, and the correlation with the block to be encoded is within a predetermined search range in the reference image that is temporally related. Detect high block position. The movement amount of the macroblock on the reference image is a motion vector. By encoding the encoding target block using the difference value between the encoded image and the reference image together with the motion vector, the information amount of the encoded image can be reduced.

  The accuracy of the motion vector is determined by the standard. MPEG1 and MPEG2 employ ½ precision, but MPEG4 and MPEG4AVC employ ¼ precision to improve encoding efficiency (see Non-Patent Document 1, for example). By interpolating a pixel at the decimal position of the reference image and performing a matching process with the macroblock of the encoded image, a motion vector with a decimal precision can be obtained.

  FIG. 7 is an explanatory diagram of pixel interpolation in the case of performing motion compensated prediction with 1/4 accuracy in MPEG4AVC. Circles indicate integer pixels, triangles indicate ½ precision pixels, and squares indicate ¼ precision pixels. In the following description, when a pixel with ¼ precision is referred to together with its precision position, it is referred to as “a pixel at ¼ position”, “a pixel at 2/4 position” or “a pixel at 3/4 position”.

  First, a 6-tap FIR (Finite Impulse Response) filter process is performed on the integer pixel to generate a ½ precision pixel. For example, when generating a pixel b with 1/2 precision, 6-tap FIR filter processing is performed on the integer pixels E, F, G, H, I, and J. As an example of a 6-tap FIR filter coefficient, (1, -5, 20, 20, -5, 1) // 32 is defined. // means a division with rounding (rounding off).

  Next, 2-tap FIR filter processing is performed on adjacent integer pixels and 1/2 precision pixels, or 1/2 precision pixels and 1/2 precision pixels to generate 1/4 precision pixels. To do. For example, when generating a quarter precision pixel a, a 2-tap FIR filter process is performed on the integer pixel G and the half precision pixel b. As an example of a 2-tap FIR filter coefficient, (1, 1) // 2 is defined.

FIG. 8 is an explanatory diagram of a conventional pixel interpolation method.
FIGS. 8A and 8B show a state in which half-tap pixels are generated by performing 6-tap FIR filter processing on integer pixels. In FIGS. 8B and 8C, 2-tap FIR filter processing is performed on adjacent integer pixels and 1/2 precision pixels, or 1/2 precision pixels and 1/2 precision pixels. This shows how quarter-precision pixels are generated. In FIGS. 8A, 8B, and 8C, for convenience of explanation, the area E is drawn with different sizes, but each area E is an area having the same size.

FIG. 9 is an explanatory diagram of the flow of conventional pixel interpolation processing.
That is, after the half precision pixels 101, 102, 103, and 104 are interpolated by pipeline processing, the quarter precision pixels 201, 202, 203, 204, 205, and 206 are interpolated by pipeline processing. It represents the situation. This figure shows a state where pixels with decimal precision are interpolated in the horizontal direction, but the same applies when pixels with decimal precision are interpolated in the vertical direction.

  FIG. 10 is a configuration diagram of an image encoding device in MPEG4 AVC. Hereinafter, the conventional image coding using the 1/4 compensated motion compensated prediction will be described with reference to FIG.

  The image on which intra coding is performed is supplied to the motion compensation prediction unit 49, where intra prediction is performed. The intra-predicted image is supplied to the orthogonal transform unit 41 and orthogonally transformed with respect to the blocks in the frame. The orthogonally transformed image is supplied to the quantization unit 42 and quantized with the set quantization value. The quantized image is supplied to the entry-pe encoder 43, entropy-coded, and output.

  On the other hand, an image on which inter coding is performed is supplied to the motion compensation prediction unit 49, and motion compensation prediction is performed. A reference image is required for inter coding. As the reference image, an image that has already been orthogonally transformed by the orthogonal transformation unit 41 and quantized by the quantization unit 42 is used. The quantized image is supplied to the inverse quantization unit 44 and inversely quantized. The inversely quantized image is supplied to the inverse orthogonal transform unit 45 and subjected to inverse orthogonal transform. The inversely quantized image is supplied to the loop filter 46 according to the setting, deblocked, and supplied to the pixel interpolation unit 47.

  FIG. 11 is a configuration diagram of a conventional pixel interpolation unit 47, and an interpolation operation will be described with reference to this diagram.

  First, integer pixels are supplied to the ½ pixel generation unit 51. The ½ pixel generation unit 51 generates ½ precision pixels by performing 6-tap FIR filter processing on the integer pixels. The generated half-precision pixels are recorded in the frame memory 48 together with the integer pixels. Only ½ precision pixels and integer pixels, or ½ precision pixels recorded in the frame memory 48 are supplied to the ¼ pixel generation unit 52. The ¼ pixel generation unit 52 generates ¼ precision pixels by performing 2-tap FIR filter processing on these pixels. The generated ¼ precision pixels are recorded in the frame memory 48.

FIG. 12 is a circuit configuration diagram of the ½ pixel generation unit 51.
The sequentially supplied integer pixels are delayed for a predetermined time by the delay circuit. Each pixel value of the delayed integer pixel is multiplied by an FIR filter coefficient (1, -5, 20, 20, -5, 1), and the sum is rounded (16 is added to the sum). Divide by 32 (5-bit shift). The generated half-precision pixel is recorded in the frame memory 48.

FIG. 13 is a circuit configuration diagram of the ¼ pixel generation unit 52.
The ¼ pixel generation unit 52 is supplied with only ½ precision pixels and integer pixels or ½ precision pixels recorded in the frame memory 48. The sum of the pixel value of the ½ precision pixel and the pixel value of the integer pixel is rounded off (1 is added to the sum) and divided by 2 (1 bit shift). The generated ¼ precision pixels are recorded in the frame memory 48.

When the pixels with decimal precision are interpolated and recorded in the frame memory 48 in this way, the motion compensation prediction unit 49 uses the previously input encoded image and the reference image supplied from the frame memory 48. Then, a matching process is performed for each macroblock to create a motion vector and difference data. The motion vector is supplied as it is to the entry-pe encoder 43 and encoded. The difference data is orthogonally transformed by the orthogonal transformation unit 41, quantized by the quantization unit 42, encoded by the entropy coding unit 43, and output.
“Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T recommendation, H.264 / ISO / IEC 14496-10 AVC)” 8.4.2.2 Fractional sample interpolation process pp.119-123 Joint Video Team ( JVT) of ISO / IEC MPEG and ITUT VCEG, JVT-G050, Mar. 2003.

  As shown in FIG. 9, in order to interpolate a ¼ precision pixel between integer pixels continuous in the horizontal or vertical direction by the conventional image encoding device, first, the integer pixel is read from the frame memory 48. , 6-tap FIR filter processing must be performed to generate ½ precision pixels and recorded in the frame memory 48. Then, it is necessary to read out the ½ precision pixels recorded in this way from the frame memory 48, apply a 2-tap FIR filter process to generate ¼ precision pixels, and record them in the frame memory 48.

  However, according to such a procedure, it is not possible to interpolate ½ precision pixels and ¼ precision pixels by pipeline processing, so there is a problem that the processing speed cannot be increased. In addition, since there is a delay in the generation time of the ½ precision pixel and the ¼ precision pixel, there is a problem that the motion compensation prediction cannot be pipelined and the processing speed cannot be increased.

  The present invention has been made in view of such problems, and performs one-time pipeline processing on pixels of 1/2 accuracy and pixels of 1/4 accuracy between integer pixels that are continuous in the horizontal or vertical direction. It is an object of the present invention to provide a motion compensation prediction apparatus capable of performing motion compensation prediction processing at a high speed by performing interpolation at the above.

  In order to achieve the above object, a motion compensated prediction apparatus according to the present invention is a motion compensated prediction apparatus that performs decimal precision motion compensated prediction, and performs filtering processing on integer pixels that are continuous in a horizontal or vertical direction. Pixel interpolating means for interpolating ½ precision pixels and ¼ precision pixels between two adjacent integer pixels in one clock at a time, and decimal precision pixels interpolated by the pixel interpolating means And motion compensation prediction means for performing motion compensation prediction using. In other words, the pixel interpolation means interpolates the first ½ precision pixel, and then the second ½ precision that continues in the horizontal or vertical direction with respect to the first ½ precision pixel. Before interpolating the first pixel, the quarter precision pixel adjacent to the first half precision pixel is interpolated. As a result, half-precision pixels and quarter-precision pixels are interpolated by one pipeline processing between integer pixels that are continuous in the horizontal or vertical direction, so that motion compensation prediction processing can be performed at high speed. Is possible.

  Specifically, the pixel interpolating means interpolates a pixel at a ½ position by performing a 6-tap filter process on the integer pixel, and the interpolated pixel at the ½ position and the ½ position A pixel is interpolated at a 1/4 position by applying a 2-tap filter process to one of the integer pixels adjacent to the pixel, and the interpolated pixel at the 1/2 position is adjacent to the pixel at the 1/2 position. A pixel is interpolated at a 3/4 position by applying a 2-tap filter process to the other of the integer pixels to be performed. Accordingly, it is possible to interpolate a ½ precision pixel and a ¼ precision pixel together between two adjacent integer pixels.

  Further, the pixel interpolating means performs 1/4 tap processing on the integer pixel by performing a 6-tap filter process with a filter coefficient of (1, -5, 52, 20, -5, 1) // 64. A pixel is interpolated at a position, and a 6-tap filter process with a filter coefficient of (1, -5, 20, 20, -5, 1) // 32 is performed to interpolate the pixel at a 1/2 position and filter A pixel is interpolated at a 3/4 position by applying a 6-tap filter process with a coefficient of (1, -5, 20, 52, -5, 1) // 64. This also makes it possible to interpolate ½ precision pixels and ¼ precision pixels together between two adjacent integer pixels.

  Here, the pixel interpolation means performs filtering on integer pixels that are continuous in one of the horizontal and vertical directions, so that a ½ precision pixel and a ¼ precision pixel are provided between two adjacent integer pixels. And then interpolating ½ precision pixels and ¼ precision pixels together by filtering the integer pixels that are continuous in the other in the horizontal and vertical directions, By filtering the half-precision pixels that are continuous in the other of the horizontal and vertical directions, the half-precision pixels and the quarter-precision pixels are collectively interpolated. For example, when performing pixel interpolation processing in the vertical direction after performing pixel interpolation processing in the horizontal direction, pixel interpolation is performed using not only integer pixels but also previously generated half-accuracy pixels in the vertical direction. Processing is performed. As a result, the processing speed can be further increased.

  The pixel interpolating means interpolates the remaining 1/4 precision pixels by performing a 2-tap filter process on the 1/2 precision pixels. As a result, the remaining ¼ precision pixels are interpolated, and the pixels are interpolated at all decimal precision positions.

  Further, the motion compensation prediction unit performs motion compensation prediction by reading the decimal precision pixels in the order of spatial arrangement. As a result, in motion compensated prediction, matching processing with an encoded image can be pipelined, and the motion compensated prediction processing is speeded up.

  The present invention can be realized not only as such a motion compensation prediction apparatus, but also as a motion compensation prediction method using steps characteristic of the motion compensation prediction apparatus. It can also be realized as a program for causing a computer to execute steps. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM or a transmission medium such as the Internet.

  Each functional block in the block diagram is typically realized as an LSI which is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them. The name used here is LSI, but it may also be called IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

  Further, the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible. An FPGA (Field Programmable Gate Array) that can be programmed after the manufacture of the LSI or a reconfigurable processor that can reconfigure the connection and setting of the circuit cells inside the LSI may be used.

  Further, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology. Biotechnology can be applied.

  As described above, according to the motion compensated prediction apparatus according to the present invention, a ½ precision pixel and a ¼ precision pixel are obtained by one pipeline process between integer pixels that are continuous in the horizontal or vertical direction. It is possible to interpolate. In motion compensated prediction, since there is no delay in the generation time of adjacent ½ precision pixels and ¼ precision pixels, it is possible to read out decimal precision reference images successively in the order of spatial arrangement. is there. As a result, the matching process with the encoded image can be pipelined, and the motion compensation prediction process is speeded up.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The configuration of the image coding apparatus according to the first embodiment is the same as that of the conventional image coding apparatus (FIG. 10), although the functions of the pixel interpolation unit 47 and the motion compensation prediction unit 49 are different. Hereinafter, only the difference of the configuration of the image encoding device of the present invention from the conventional image encoding device will be described.

  FIG. 1 is a configuration diagram of the pixel interpolation unit 47 of the present invention. The pixel interpolation unit 47 of the present invention includes a fractional pixel batch generation unit 81 that collectively generates ½ precision pixels and ¼ precision pixels, and a remaining ¼ precision pixel (described later). And a 1/4 pixel generation unit 52 for generation.

  That is, the integer pixels are supplied to the decimal pixel batch generation unit 81 in the order of the horizontal or vertical direction. The fractional pixel batch generation unit 81 collectively performs a 6-tap FIR filter process and a 2-tap FIR filter process to generate a ½ precision pixel and a ¼ precision pixel together. The generated ½ precision pixel and ¼ precision pixel are recorded in the frame memory 48 together with the integer pixels.

  The ½ precision pixels recorded in the frame memory 48 are supplied to the ¼ pixel generation unit 52. The ¼ pixel generation unit 52 generates a ¼ precision pixel by performing a 2-tap FIR filter process on the ½ precision pixel. The generated ¼ precision pixels are recorded in the frame memory 48.

FIG. 2 is a circuit configuration diagram of the decimal pixel batch generation unit 81 according to the first embodiment.
The sequentially supplied integer pixels are delayed for a predetermined time by the delay circuit. Each pixel value of the delayed integer pixel is multiplied by the FIR filter coefficient (1, -5, 20, 20, -5, 1), and the sum is rounded off and divided by 32. The generated half-precision pixels are recorded in the frame memory 48 and supplied to the adders P1 and P2.

  One adder P1 is supplied with integer pixels in addition to half-precision pixels. As a result, the sum of the pixel value of the ½ precision pixel and the pixel value of the integer pixel is rounded off and divided by two. The generated pixel at the 1/4 position is recorded in the frame memory 48.

  The same applies to the other adder P2. That is, the sum of the pixel value of the half precision pixel and the pixel value of the integer pixel is rounded off and divided by two. The generated pixel at the 3/4 position is recorded in the frame memory 48.

FIG. 3 is an explanatory diagram of the flow of pixel interpolation processing of the present invention.
A half precision pixel and a quarter precision pixel are interpolated by pipeline processing. Here, the decimal precision pixels that are collectively generated for each clock are surrounded by a dotted rectangle. That is, the ½ precision pixel 11 and the ¼ precision pixels 21 and 22 are collectively generated by the first clock and interpolated between adjacent integer pixels. At the next clock, the ½ precision pixel 12 and the ¼ precision pixels 23 and 24 are collectively generated. At the next clock, the ½ precision pixel 13 and the ¼ precision pixels 25 and 26 are generated. Are generated in a batch.

  Here, the flow of interpolating pixels with decimal precision in the horizontal direction has been described, but the same applies to the vertical direction. However, in the case of interpolating decimal precision pixels in the vertical direction, not only integer pixels but also previously generated half precision pixels are read from the frame memory 48. That is, as will be described below, the processing speed is further increased by interpolating decimal precision pixels not only between integer pixels but also between ½ precision pixels.

4 and 5 are explanatory diagrams of the flow of pixel interpolation processing of the present invention.
As shown in FIG. 4A, only integer pixels exist in the initial state. First, as shown in FIG. 4B, the decimal precision pixels are collectively interpolated for one column L1 in the horizontal direction. Since the manner in which a small number of pixels are interpolated is as described with reference to FIG. 3, detailed description thereof is omitted here. Thereafter, as shown in FIGS. 4C to 4F, the decimal precision pixels are sequentially batch-interpolated sequentially for each of the columns L2 to L5 in the horizontal direction.

  Next, the decimal precision pixels are collectively interpolated for the vertical line L6. The method of collectively interpolating the decimal precision pixels for this row L6 is also as described with reference to FIG. Next, the decimal precision pixels are collectively interpolated for the vertical line L7. That is, the decimal precision pixels are interpolated between the previously generated half precision pixels. The method of collectively interpolating the decimal precision pixels for this row L7 is as described with reference to FIG. 3 except that half precision pixels are used instead of integer pixels. Thereafter, as shown in FIGS. 5C to 5J, decimal precision pixels are sequentially interpolated sequentially for each of the columns L8 to L14 in the vertical direction.

  Then, the remaining 1/4 precision pixels are interpolated. That is, in the state where the decimal interpolation of pixels in the horizontal direction and the vertical direction is completed, as shown in FIG. 5 (J), the area where interpolation of the quarter precision pixels such as the area A10 is not completed. Exists. Therefore, the ¼ pixel generation unit 52 reads out ½ precision pixels recorded in the frame memory 48 and interpolates ¼ precision pixels as shown in FIG. That is, a ¼ precision pixel is interpolated between the two pixels using a ½ precision pixel in the area A1. The same applies to the areas A2 and A3. As a result, as shown in FIG. 5L, when all the remaining 1 / 4-accuracy pixels are interpolated and recorded in the frame memory 48, the pixel interpolation process ends.

  Next, the motion compensation prediction unit 49 reads out decimal precision pixels (reference images) from the frame memory 48, performs matching processing with the encoded image, and determines a motion vector. At this time, without waiting for all the decimal precision pixels to be generated, the pixels are read out from the frame memory 48 in the order of the spatial arrangement generated by the pixel interpolation unit 47, and the matching process proceeds.

  As described above, according to the image coding apparatus of the first embodiment, a half-precision pixel and a quarter-precision pixel are connected to a single pipeline between integer pixels that are continuous in the horizontal or vertical direction. It is possible to interpolate by processing. Further, in motion compensation prediction, since there is no delay in the generation time of adjacent 1/2 precision pixels and 1/4 precision pixels, the decimal precision reference images generated by the pixel interpolation unit 47 are arranged in the spatial arrangement order. It is possible to read continuously. As a result, the matching process with the encoded image can be pipelined, and the motion compensation prediction process is speeded up.

  In addition, although the structure which applied this invention to the image coding apparatus was illustrated here, this invention is not limited to this. That is, as long as the apparatus includes a pixel interpolation unit and a motion compensation prediction unit, the present invention can be applied.

  In addition, although the half precision pixel and the quarter precision pixel are illustrated here as the decimal precision pixels, the present invention is not limited to this. That is, the present invention can also be applied when interpolating other decimal precision pixels.

(Embodiment 2)
In the first embodiment, a ¼ precision pixel is generated by performing a 2-tap filter process on a ½ precision pixel and an integer pixel. Therefore, although a half precision pixel and a quarter precision pixel can be interpolated by one pipeline process, a quarter precision pixel is generated until a half precision pixel is generated. I can't do it. That is, although not particularly mentioned in the first embodiment, when generating a ¼ precision pixel (see FIG. 2), an integer is used to match the timing at which the ½ precision pixel is generated. It is necessary to delay the pixels for a predetermined time before supplying them to the adders P1 and P2.

Hereinafter, only differences between the second embodiment and the first embodiment will be described.
In the second embodiment, a 6-tap filter process is performed only on integer pixels to generate ¼ precision pixels. Specifically, by adopting (1, -5, 52, 20, -5, 1) // 64 as the FIR filter coefficient, a pixel at a 1/4 position is generated, and as the FIR filter coefficient, (1 , −5, 20, 52, −5, 1) // 64, the pixel at the 3/4 position is generated. Even with such a simple technique, it is possible to generate substantially the same pixels as the quarter-accuracy pixels generated in the first embodiment.

FIG. 6 is a circuit configuration diagram of the decimal pixel batch generation unit 81 according to the second embodiment.
The method of generating a ½ precision pixel is the same as that in the first embodiment. That is, the sequentially supplied integer pixels are delayed by a predetermined time by the delay circuit. Each pixel value of the delayed integer pixel is multiplied by an FIR filter coefficient (1, -5, 20, 20, -5, 1), and the sum is rounded (16 is added to the sum). Divide by 32 (5-bit shift). The generated half-precision pixel is recorded in the frame memory 48.

  The method for generating the pixels at the 1/4 position is the same as the method for generating the pixels with 1/2 accuracy except that the FIR filter coefficients are different. That is, the sequentially supplied integer pixels are delayed by a predetermined time by the delay circuit. Each of the pixel values of the delayed integer pixels is multiplied by the FIR filter coefficient (1, -5, 52, 20, -5, 1), and the sum is rounded (32 is added to the sum). Divide by 64 (6 bit shift). The generated pixel at the 1/4 position is recorded in the frame memory 48.

  The method for generating a pixel at the 3/4 position is the same as the method for generating a pixel with 1/2 accuracy except that the FIR filter coefficients are different. That is, the sequentially supplied integer pixels are delayed by a predetermined time by the delay circuit. Each of the delayed integer pixel pixel values is multiplied by the FIR filter coefficients (1, -5, 20, 52, -5, 1) and the sum is rounded (32 is added to the sum). Divide by 64 (6 bit shift). The generated pixel at the 1/4 position is recorded in the frame memory 48.

  As described above, in the second embodiment, by adopting a simple method of adopting a new FIR filter coefficient, a 6-tap filter process is performed only on integer pixels to generate a quarter precision pixel. It is possible to do. In this way, it is possible to generate a ¼ precision pixel without waiting for a ½ precision pixel to be generated, so that the processing can be further speeded up.

  The motion compensated prediction apparatus according to the present invention moves at high speed by interpolating ½ precision pixels and ¼ precision pixels between integer pixels that are continuous in the horizontal or vertical direction by a single pipeline process. The present invention can be applied to applications such as an image encoding device that needs to perform compensation prediction processing.

Configuration diagram of pixel interpolation unit of the present invention Circuit configuration diagram of decimal pixel batch generation unit in the first embodiment Explanatory drawing of the flow of pixel interpolation processing of the present invention Explanatory drawing of the flow of pixel interpolation processing of the present invention Explanatory drawing of the flow of pixel interpolation processing of the present invention Circuit configuration diagram of decimal pixel batch generation unit in the second embodiment Explanatory drawing of 1/4 precision pixel interpolation in MPEG4AVC Illustration of conventional pixel interpolation method Explanatory drawing of the flow of conventional pixel interpolation processing Configuration diagram of image coding apparatus using motion compensated prediction Configuration of conventional pixel interpolation unit Circuit configuration diagram of 1/2 pixel generator Circuit configuration diagram of 1/4 pixel generator

Explanation of symbols

DESCRIPTION OF SYMBOLS 40 Image coding apparatus 41 Direct transformation part 42 Quantization part 43 Entropy encoding part 44 Inverse quantization part 45 Inverse orthogonal transformation part 46 Loop filter 47 Pixel interpolation part 48 Frame memory 49 Motion compensation prediction part 51 1/2 pixel production | generation part 52 1/4 Pixel Generation Unit 81 Decimal Pixel Batch Generation Unit

Claims (10)

A motion compensated prediction apparatus that performs motion compensated prediction with decimal precision,
Pixels that collectively interpolate ½ precision pixels and ¼ precision pixels between two adjacent integer pixels in one clock by performing filtering on integer pixels that are continuous in the horizontal or vertical direction. Interpolation means;
A motion compensation prediction apparatus comprising: motion compensation prediction means for performing motion compensation prediction using pixels with decimal precision interpolated by the pixel interpolation means. The pixel interpolating unit interpolates the first ½ precision pixel, and then performs a second ½ precision pixel continuous in a horizontal or vertical direction with respect to the first ½ precision pixel. The motion compensated prediction apparatus according to claim 1, wherein a quarter precision pixel adjacent to the first half precision pixel is interpolated before the interpolation. The pixel interpolating means interpolates a pixel at a 1/2 position by applying a 6-tap filter process to the integer pixel,
Interpolating the pixel at the 1/4 position by applying a 2-tap filter process to the interpolated pixel at the 1/2 position and one of the integer pixels adjacent to the 1/2 position pixel,
A pixel is interpolated at a 3/4 position by performing a 2-tap filter process on the interpolated pixel at the 1/2 position and the other of the integer pixels adjacent to the 1/2 position pixel. The motion compensation prediction apparatus according to claim 1. The pixel interpolation means interpolates a pixel at a 1/4 position by applying a 6-tap filter process with a filter coefficient of (1, -5, 52, 20, -5, 1) // 64 to the integer pixel. And
Interpolating a pixel at 1/2 position by applying a 6-tap filter process with a filter coefficient of (1, -5, 20, 20, -5, 1) // 32
The pixel is interpolated at a 3/4 position by applying a 6-tap filter process with a filter coefficient of (1, -5, 20, 52, -5, 1) // 64. Motion compensated prediction device. The pixel interpolating unit applies a filtering process to integer pixels that are continuous in one of the horizontal and vertical directions, and collectively applies ½ precision pixels and ¼ precision pixels between the two adjacent integer pixels. And interpolate
By filtering the integer pixels that are continuous in the other direction in the horizontal and vertical directions, the half-precision pixels and the quarter-precision pixels are interpolated at the same time, and the other in the horizontal and vertical directions are continuous. The motion compensated prediction apparatus according to claim 1, wherein the half precision pixel and the quarter precision pixel are collectively interpolated by performing filtering on the half precision pixel. 6. The motion compensated prediction apparatus according to claim 5, wherein the pixel interpolation means interpolates the remaining 1/4 precision pixels by performing a 2-tap filter process on the 1/2 precision pixels. The motion compensation prediction apparatus according to claim 1, wherein the motion compensation prediction unit performs motion compensation prediction by reading the decimal precision pixels in the order of spatial arrangement. A motion compensation prediction method for performing motion compensation prediction with decimal precision,
Pixels that collectively interpolate ½ precision pixels and ¼ precision pixels between two adjacent integer pixels in one clock by performing filtering on integer pixels that are continuous in the horizontal or vertical direction. An interpolation step;
A motion compensation prediction method, comprising: a motion compensation prediction step that performs motion compensation prediction using the decimal precision pixels interpolated in the pixel interpolation step. A program for performing motion compensation prediction with decimal precision,
Pixels that collectively interpolate ½ precision pixels and ¼ precision pixels between two adjacent integer pixels in one clock by performing filtering on integer pixels that are continuous in the horizontal or vertical direction. An interpolation step;
A program for causing a computer to execute a motion compensation prediction step of performing motion compensation prediction using pixels with decimal precision interpolated in the pixel interpolation step. An integrated circuit that performs motion compensation prediction with decimal precision,
Pixels that collectively interpolate ½ precision pixels and ¼ precision pixels between two adjacent integer pixels in one clock by performing filtering on integer pixels that are continuous in the horizontal or vertical direction. Interpolation means;
An integrated circuit, comprising: motion compensation prediction means for performing motion compensation prediction using pixels with decimal precision interpolated by the pixel interpolation means.

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