JP2006337163A - Programmable circuit and processor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute as the need arises with each logic constitution in an ordinary operation mode after mounting a device on a substrate. <P>SOLUTION: In a programmable device or a device for changing dynamically a logic constitution of data processing, a route delay test capable of corresponding to connection between processor elements changed according to the logic constitution is mounted beforehand on the device. A route delay test is executed to an practically effective route based on information of the logic constitution from inside the route delay test. Replacement of the logic constitution or optimization of an operation frequency is performed based on the route delay test result to a target frequency corresponding to connection between the processor elements. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to optimization of path delay change accompanying a configuration change of a programmable circuit that dynamically changes the configuration.

  One of the semiconductor integrated circuits is a programmable circuit that realizes various functions required by changing logical configuration information. The programmable circuit contains a plurality of processor elements, which are the minimum processing unit, and the circuit configuration can be programmed at the time of use so that the connection relationship between these processor elements can be realized as desired. Compared with a circuit having a different function, the logic configuration can be flexibly supported. However, in the programmable circuit, since the connection of the processor element changes for each logical configuration, there is also the aspect that the delay time differs for each logical configuration information. Therefore, there is a trade-off between realizing different functions and changing the delay time, but in the past, avoiding the complications caused by considering changes in the delay time, deliberately limiting the degree of freedom of the logical configuration and specifying An approach has been taken to create logical configuration information so as to keep the timing. Under such restrictions, the followings are known as conventional techniques related to the devised programmable circuit and the path delay test for detecting the delay time change.

  First, as a patent document related to a programmable circuit whose logic configuration can be changed, an array type processor (see, for example, Patent Document 1), and a data path switching type processor by extending an instruction length (for example, see Patent Document 2). However, all of these have restrictions on the connection between processor elements when creating logical configuration information, and when the logical configuration information is changed, the change in the worst value of the delay time between processor elements is automatically performed. There is no function to detect or correct.

  Further, as a patent document related to a path delay test for determining pass / fail with respect to a delay time, an operating frequency using a path delay test that does not use a tester (for example, Patent Document 3) and a path delay test that uses a scan test mechanism. Is suitable for a circuit that changes the connection between processor elements (see Patent Document 4), a test pattern generation method for recognizing an inactive path (see, for example, Patent Document 5), and the like. There is no technique for path delay testing during normal operation.

JP 2001-314881 A (first page, second page, FIGS. 4 and 5) JP2003-228518A (first page, second page, FIG. 5, FIG. 12) JP-A-11-174125 (first page, second page, FIG. 1) JP-A-2004-157090 (first page, second page, FIGS. 1 and 3) JP-A-9-127212 (page 4, FIG. 1)

  In the conventional technology, when a programmable device or a device that dynamically changes the logical configuration of data processing is used, the effective path actually used changes for each logical configuration information. As the actual effective path changes, the location of the actual critical path also changes, so it is difficult to search and set the operating conditions such as the frequency corresponding to the actual critical path automatically or semi-automatically. there were. This was caused by the following three problems.

  The first problem is that the delay time of the signal transmission path changes according to the connection status of the programmable path switch indicated by the logical configuration information. The second problem is the path indicated by the logical configuration information. It is necessary to search for the conditions for operating the switch connection conditions under the optimum conditions. The third problem is that a lot of wiring is used for the connection between the processor elements because the path switch is frequently used for mounting. It is.

  First, as a problem to deal with the problem that the delay time of the signal transmission path changes according to the connection status of the path switch, the location of severe path delay is recognized in a form corresponding to the logical configuration information that is changed at any time. It is necessary. Here, as one of methods for recognizing a severe path delay, a path delay test can be cited. The path delay test is usually performed for the purpose of performance guarantee with respect to the specification of the device itself at the time of manufacture. Conventionally, when such a programmable device is used, logical configuration information that is a connection status of a path switch is often created according to the specification performance of the selected device. In other words, it is common to design the mapping to satisfy the function according to the frequency and processing performance target determined in advance by the selected device, with area restriction etc., and low power consumption according to the logical configuration information There is usually no test mechanism used for performance optimization, including optimization and reduction of operating rate. For this reason, when searching for a delay error by performing a path delay test during normal operation, it is necessary to collate both logical configuration information and physical mapping information in advance, so that the delay time between processor elements is severe. Identify the connection and add a test circuit for path delay test to the worst delay part of the logical configuration based on this logical configuration information, or temporarily operate a test operation such as scanning to compare the expected value You have to rely on the processing to do. For this reason, when a delay change is involved in the connection between the processor elements, the configuration method between the processor elements is limited by the cycle time restriction due to the operating frequency.

  Next, the problem corresponding to the problem of searching for the optimum operating condition according to the connection status of the path switch is a mechanism for easily exploring the limit of delay performance corresponding to the logical configuration information developed in the programmable device during normal operation It is necessary to implement. In general, a device path delay test is often performed using a tester, and this test often involves a scanning operation. The path delay test with scan operation uses a method involving clock control and shift operation, which destroys the data in the flip-flops connected to the scan chain, so that the device is mounted on the board or in the normal operation mode. It is not suitable as a path delay test sometimes performed. Conventionally, programmable devices are generally used to optimize and map the logic according to the target frequency of the logic configuration information, and no delay test corresponding to the logic configuration information is performed. . Assuming that the critical path can be grasped based on the logical configuration information for several types of replaceable logical configuration information, if the path delay test is performed in the normal operation mode, the critical point of delay performance is set to the critical path. It is necessary to take measures such as adding a path delay test mechanism for searching to the logical configuration information and then sweeping the frequency targeted by the logical configuration information. However, adding logical configuration information for path delay testing is difficult at the time of mapping or preparing different test procedures for each logical configuration, so there is a possibility of switching during normal operation. It is difficult to use for the purpose of performing an operation frequency search for certain arbitrary logical configuration information. In addition, when problems related to devices such as logical configuration information and individual variations of devices become complex factors, it is desirable to have a mechanism for delayed exploration even after mounting on a substrate.

  A problem corresponding to the problem of using a large number of wirings for connection between processor elements is that it is necessary to add a test mechanism such as a path delay test without increasing the wirings between the processor elements. Originally, in programmable devices, a lot of unused path wiring already exists as connections between processor elements so that various logic configuration information can be handled. In addition to this wiring, circuit addition to connect to many areas is the area of the device This is a direct cause of the increase. For example, if the expected value is generated on the premise of data transmission on the sending side when testing the data transfer to the processor element that performs processing, the wiring from the data sending side will be prepared in duplicate. It appears as an area increase due to the increase. In order to increase the speed of the path delay test by the scan operation so that it can be used even in the normal operation mode, parallel scan paths are effective. However, the number of wirings increases with the parallelization.

  The present invention has been made in view of the above problems, and uses a tester to investigate the performance of a path delay between processor elements according to the logical configuration actually used, and a special operation mode such as a scan mode. It is an object of the present invention to provide a programmable circuit and a processor element that can be implemented as needed in individual logical configurations in a normal operation mode after mounting a device on a board.

  The programmable circuit of the present invention is a programmable circuit capable of switching a logical configuration, and includes a plurality of processor elements that are processing units for realizing a function, and the processor elements for realizing the function by combining the processor elements. A path delay test is performed in which a delay test is performed on an arbitrary connection path among connection paths between a logical configuration instruction unit that specifies an interconnection and an effective processor element that is changed according to the logical configuration instruction unit. A path delay test execution unit for generating a path delay test pattern for an individual path formed by logical configuration information, and a path delay test pattern created by the test pattern generation unit. A selection circuit for transmitting to the target path of the path delay test, A path delay test result determination unit that determines a path delay test result of an individual path by comparing a test pattern received via the target path of the path delay test with an expected value; and An expected value generation unit that generates an expected value to be input to the result determination unit.

  The processor element of the present invention includes a first flip-flop that receives data from upstream of a communication path, an expected value generation unit that generates an expected value for a path delay test upstream of the communication path, and an output of the first flip-flop. Data is transmitted to the downstream of the communication path, a result determination unit of the path delay test that compares the expected value generated by the expected value generation unit, a test pattern generation unit that generates a path delay test pattern downstream of the communication path, and And a selector that selectively sets either the test pattern generated by the test pattern or the processing result in the processor element during normal operation to the second flip-flop.

  In the programmable circuit that performs the path delay test between the processor elements according to the logical configuration information according to claim 1, a tester is used to investigate the performance of the path delay between the processor elements according to the actually used logical configuration. Rather than using a special operation mode such as a scan mode, the device can be implemented as needed in each logical configuration in the normal operation mode after the device is mounted on the board.

  In addition, by configuring a similar worst delay configuration between the processor elements in advance and performing a path delay test for empty processor elements other than those used for the logical configuration, It is possible to test the feasibility of communication between processor elements with respect to the maximum delay in the logical configuration.

  In addition, when a tester is used for a device test at the time of manufacturing, the test with the maximum delay can be specified, so that it is easy to perform a test on the performance of the device itself. Furthermore, even after mounting the device on the board, the delay performance corresponding to the logical configuration information mapping to the actual programmable circuit can be tested, so it is possible to check the operation considering both individual differences of devices and the logical configuration. become.

  In a programmable circuit that performs a path delay test between processor elements in accordance with the logical configuration information according to claim 2, the clock timing is set based on the result of the pass / fail result in the path delay test. It is possible to automatically search for a frequency at which the designated logical configuration can operate.

  Further, by using together the setting method of the operating frequency controlled by software or dedicated hardware, it is possible to rationalize and simplify the optimal operating frequency setting in terms of power consumption and operating efficiency.

  Furthermore, according to the present invention, since error information can be obtained immediately with good responsiveness, it becomes possible to automatically perform logical configuration selection according to timing control information.

  A programmable circuit that performs a path delay test between processor elements according to the logic configuration information according to claim 3 selects a part of a path that is effectively used by the logic configuration information and performs the path delay test. Things are possible. Conversely, if a path delay test is not required for processor elements that are not used as a logical configuration by the logical configuration information or where there is no obvious worst-case delay, mask the path delay test results based on the logical configuration information. Or control to stop the operation of the path delay test circuit.

  By using the processor element according to claim 4, by providing each processor element of the processor element group with a path delay test pattern generator having the same function, the path of the connection between the processor elements throughout the processor element group of the programmable circuit A common pattern is used for the test pattern used in the delay test. As a result, since the test pattern generation unit and the expected value generation unit can be separately arranged, it is possible to configure a test circuit that does not require extra wiring such as a scan path and an expected value transfer path. Further, since the path delay test can be performed without depending on scanning, it is not necessary to mount an extra wiring path at the time of mounting, and a path delay test that does not require a procedure for setting a value and time is possible.

  In addition, since the data input and data output of the processor element can be separated from the normal data processing, the data output of the processor element can be tested even if there is no vector regarding the operation rate during the test using the tester. It is also possible to perform a preliminary investigation of the operating frequency dependency in a manner that imitates the influence of the operating rate by operating the data processing in the processor element in a pseudo manner while keeping the selected state on the vector side.

  By using the processor element according to the fifth aspect, it is possible to use both the test pattern generation unit and the expected value generation unit, and it can be expected that the circuit amount is reduced and the path delay test is simplified.

Embodiments of the present invention will be described below.
Here, the processor of the present invention is based on the premise that a programmable switch including a flip-flop in the data transfer path is also handled as a kind of processor element. The reason for this will be described with reference to FIG. 12 and subsequent figures. When the programmable switch includes a flip-flop, the insertion point of the path delay test circuit can be handled in the same manner as the processor element, and the programmable switch does not include the flip-flop. This is because it can be considered a derivative of the circuit shown in the first claim claimed by the present invention.

An embodiment of the present invention is shown in FIG.
In FIG. 1, as a mechanism for performing a path delay test on a path determined based on logical configuration information, a system that generates a path delay test pattern as a data transmission side, and a data transfer error at the data reception side An example is shown in which a system for independently determining the value by comparing expected values is provided.
That is, the processor corresponding to the control of the programmable circuit that realizes certain logical configuration information by the logical configuration instruction unit (100) that controls the entire processor element that controls the combination of paths of all the processor elements based on the logical configuration information. The control information (125) of the element is transmitted to each processor element. A path delay test from the processor element 0 (101) on the transmitting side to the processor element 8 (109) on the receiving side is determined according to the control information (125) of the processor element that realizes certain logical configuration information. It is assumed that the target route (126) is temporarily established.

  In the system for generating a path delay test pattern on the data transmission side, the contents of the transmission side flip-flop (112) in the processor element 0 are the data processing unit in the processor element 0 when the normal logic operation is performed. The result processed in (110) is selected by the output data selector (111) in the processor element 0. When the path delay test operation is performed, the test pattern generation unit (113) arranged in the vicinity of the processor element 0 Is selected by the output data selector (111) in the processor element 0.

  Next, as a system for judging data transfer errors by comparing expected values on the data receiving side according to operating conditions such as frequency, the target path of the path delay test established when the logic operation is started in the processor element Assume that the expected value is compared with (126). That is, on the basis of the control information (125) of the processor element from which the path delay test target path (126) is selected, the input data selector (117) in the processor element 8 as the path delay test target inputs the input data. The data is received and received by the reception side flip-flop (118) in the processor element 8. Next, the output value of the flip-flop (118) and the output value of the path delay test expected value generation unit (123) to be subjected to the path delay test are determined by the path delay test result determination unit (122) to be the path delay test target. By comparing, it is possible to test whether or not the data of the transmission side flip-flop (112) in the processor element 0 has been transferred to the target path (126) of the path delay test without error.

  The path delay test trigger information is also generated by the logic configuration instruction unit (100) and distributed as one of the control signals to the path delay test unit (124) distributed throughout the programmable circuit. The test pattern generation unit (113) And the path delay test expected value generation unit (123) to be the path delay test target of the data receiving side processor element 8 and the path delay test result determination unit (122) to be the path delay test target are guaranteed.

  Here, in the present invention, the path delay test unit (124) is basically distributed according to the arrangement state of the processor elements. However, as the path delay test mechanism, in order to avoid an increase in circuit amount, a plurality of path delay test units (124) are provided. It is also possible to adopt a configuration in which the processor element shares the path delay test unit (124).

  In addition, as a test execution method, in order to utilize the test pattern itself as an expected value, a separate path is not provided and propagated, but the test pattern generation unit (113) during the test operation and the path subject to the path delay test A method of comparing expected values based on the one-to-one correlation of the delay test expected value generation unit (123) is adopted. The path delay test unit (124) does not assume a scan operation and does not necessarily require an operation mode change to the test mode, so that a path delay test result can be obtained immediately. This method has the advantage that path delay tests can be executed in parallel for paths that are not used during normal operation.

  As a specific test pattern generator and expected value generator, it is possible to use a simple circuit that only generates common toggle information, or by using a common pseudo-random number generator, etc. It is also possible to carry out complex pattern tests. Further, as an alternative to the dedicated circuit for generating these patterns, a circuit in the processor element such as an arithmetic circuit or a counter may be temporarily used.

In addition, it is possible to perform control without performing a path delay test on a path that is apparently not used by control information (125) of a processor element that realizes certain logical configuration information. That is, the path (127) from the processor element 0 (101) on the transmission side to the processor element 1 (102) where the transmission path is not established by the control information (125) of the processor element is the control information (125 of the processor element). ) Based on the path delay test. In other words, the system that performs the path delay test of the reception-side flip-flop (115) in the processor element 1 that is not subject to the path delay test for which the transmission path is not established is not used as an actual path and expects an error in data transfer. It is a system that does not need to be judged by value comparison. The route delay test result determination unit (120) that is not subject to the route delay test of the processor element 1 and the route delay test result that is not subject to the route delay test are the entire route delay test results. It is not reflected in the result of.
As for the timing of the path delay test, the logical configuration information is analyzed in advance before the actual operation processing is input, and the logical configuration information is simulated in a timing that is likely to be strict or by using an unused element. It is possible to consider an execution form in which the path delay test can be executed in advance for the created connection and the operation frequency can be adjusted to the operating frequency corresponding to the logical configuration information before or after the start of the arithmetic processing.

  Another embodiment of the present invention is shown in FIG. FIG. 2 shows an example in which effective routes are selected based on programmable logic configuration information, effective results are aggregated, and operation timing is optimized.

  That is, a path delay test target path between the transmitting-side processor element 0 (101) and the receiving-side processor element 8 (109) by the logical configuration instruction unit (100) that controls the combination of paths between the processor elements. (126) shall be determined.

  Here, at the time of normal logic operation, the data processing unit (110) in the processor element 0 (101) on the transmission side operates according to the control information (203) of the data processing unit of the processor element 0, and the data processing in the processor element 0 The data processed by the unit (110) passes through the output data selector (111) in the processor element 0, the transmission side flip-flop (112) in the processor element 0, and the input data selector (117) in the processor element 8. The signal is received by the reception side flip-flop (118) in the processor element 8. The received data is processed by the data processing unit (119) in the processor element 8 after the next cycle. At this time, control information (203) of the data processing unit of the processor element 0 on the transmission side, control information (204) of the output data selector of the processor element 0, and control information (205) of the input data selector of the processor element 8 on the reception side ), And the control information (206) of the data processing unit of the processor element 8 selects a communication path for normal logic operation, and the control information (207) of the path delay test unit is the path delay test unit ( The path delay test operation in the target path (126) of the path delay test of 124) is suppressed.

  Next, during the path delay test operation, the control information (204) of the output data selector of the processor element 0 is set to the path delay test pattern selection state, and the selection state of the input data selector (117) in the processor element 8 on the receiving side is logically changed. Fix according to the configuration information. The path delay test unit (124) shown in FIG. 1 is distributed according to the arrangement state of the processor elements, and the control information (207) of the path delay test unit is the target processor element 0 (101). ) And the path delay test operation between the processor element 8 (109), the test pattern generation unit (113), the path delay test expected value generation unit (123) that is the path delay test target of the processor element 8, and the path The path delay test result determination unit (122) to be a delay test target is controlled. Obtained by the path delay test result determination unit (122) as the path delay test target based on the path delay test expected value information (212) generated by the path delay test expected value generation unit (123) as the path delay test target. The route delay test result information (211) is summed up by the route delay test result summation unit (200), and is used as route delay test summation result information (209), which is used as control information for the entire delay device.

  When timing adjustment is performed based on the path delay test tabulation result information (209), the timing control unit (201) converts it into timing control information (208). The timing control information (208) is transferred to the clock control unit (202), performs timing control according to the conditions specified by the timing control information (208), and distributes it to each part as a clock signal (210). For example, if the path delay test result is in error, lower the operating frequency by changing the PLL division ratio until the path delay test result no longer causes an error so that the timing required for the path delay is increased. Control. If the path delay test result is not in error, control is performed to increase the operating frequency for speeding up the processing and shorten the timing required for the path delay.

  Further, when it is desired to change to a circuit configuration with different logical configuration information using the path delay test total result information (209) as a trigger, feedback control to the logical configuration instruction unit is performed. For example, when a clock cycle is fixed in a specific frequency region as an operation condition, if an error situation is detected in the path delay test tabulation result information (209), a logical configuration that is inferior in processing performance but easy in operation in terms of timing It is possible to adopt a control method in which information is selected again, the circuit configuration is reconfigured, and processing is executed thereafter.

A preferred embodiment as claimed in claim 3 of the present invention is shown in FIG.
FIG. 3 excludes a path delay test result corresponding to a path that exists on the device but is not used based on programmable logic configuration information, and uses only the path delay test for an effective path to optimize the operating frequency. The suppression control to do is shown.

  That is, according to the example of FIG. 3, when the output of the processor element 0 (101) is not selected as the input information of the processor element 1 (102) from the logical configuration instruction unit according to certain logical configuration information, these processor elements Since the route between 0 (101) and processor element 1 (102) is not used and is recognized as a connection route (127) that is not subject to the route delay test, the route delay information between these connections takes timing into account. There is no need to do. When such logical configuration information is used, the logical configuration instruction unit controls the selection status of the route to which the path delay test is applied and the mask status of the path delay test result. For example, for the connection path (127) that is not subject to the path delay test, the control information (203) of the data processing unit of the processor element 0 on the transmission side, the control information (204) of the output data selector of the processor element 0, and the reception The path selection is controlled to be inactive by control information (301) of the input data selector of the processor element 1 and control information (302) of the data processing unit of the processor element 1 on the side. The test pattern generation unit (113) related to the corresponding route in the route delay test unit (124) shown in FIG. 1, the route delay test result determination unit (120) that is not subject to the route delay test, and the route delay test subject The path delay test is not performed or the path delay test result is masked in the path delay test expected value generation unit (121) and the path delay test result totaling unit (200) of FIG. Only the required path delay test result is transmitted to the logical configuration instruction unit (100) and the timing control unit (201). Feedback of control information to the logical configuration instruction unit (100) and the clock control unit (202) is performed in the same manner as in FIG.

  FIG. 4 illustrates one method of using the logical configuration information for realizing the control of FIG. 3, and the path delay test result determination unit (120) that is not subject to the path delay test of the processor element 1 in FIG. A configuration example is shown.

  That is, the expected value comparison unit (400) uses the received data (402) and the path delay test expected value information (304) by the reception side flip-flop (115) in the processor element 1 that is not subject to the path delay test. At this time, the operation and stop of the expected value comparison unit (400) are controlled by the path delay test enable control information (403). In addition, the test result mask mechanism (401) that suppresses the output of the expected value comparison unit (400) based on the path delay test enable control information (403) is used, and the pass / fail of the test result is indicated according to the implementation status of the path delay test. . Route delay test result information (303) corresponding to the implementation status is collected in the route delay test result totaling unit (200).

  FIG. 5 explains another method of using the logical configuration information for realizing the control of FIG. 3, and shows a configuration example of the path delay test result totaling unit (200) in FIG. The path delay test result suppression control of FIG. 4 is performed on the path delay test result totaling unit (200) side.

  That is, in order to perform the mask processing of the test result for each path, the path delay test result mask circuit (501) of the processor element 0 and the processor element 1 of the processor element 1 are used as a mask mechanism corresponding to the path delay test result determination unit in each processor element. A path delay test result mask circuit (502) and a path delay test result mask circuit (503) of the processor element n are provided. The path delay test result (505) of the processor element 0, the path delay test result (507) of the processor element 1, and the path delay test result (509) of the processor element n are respectively path delay test enable information (504) of the processor element 0. The path delay test enable information (506) of processor element 1 and the path delay test enable information (508) of processor element n are mask-controlled, and only the effective path delay test result is route delay by the result totaling processing unit (500). Assume that test results can be aggregated. Valid route delay test tabulation result information (209) is transmitted to the logical configuration instruction unit (100) or the timing control unit (201).

Another embodiment of the present invention is shown in FIG.
FIG. 6 shows an example of the configuration of a processor element that facilitates an effective path delay test of the programmable device of the present invention.

That is, a processor element (600) constituting a reconfigurable programmable device includes a system of a path delay test result determination unit (607) and an expected value generation unit (607) for a path from the upstream side of the communication path, and at the same time A system of a test pattern generation unit (608) for the downstream path of the communication path after the own element (600) is provided independently. FIG. 6 shows an example in which the processor element (600) has a local processor element control unit (601) for controlling the path delay test inside the processor element.
The data sent from the upstream side of the communication path specifies the connection path between the processor elements by the input data selector (602) and is stored in the reception side flip-flop (603). A path delay test result determination unit (607) and an expected value generation unit (608) determine whether the result of the path delay test is acceptable.

  The test pattern sent to the downstream side of the communication path is generated by the test pattern generation unit (609) of the path delay test, not the data from the data processing unit (604) selected during the normal logic operation by the output data selector (605). Data is selected and stored in the transmission side flip-flop (606) to form a path delay test pattern.

Another preferred embodiment according to claim 4 of the present invention is shown in FIG.
FIG. 7 shows an example of the configuration of a processor element that facilitates the path delay test of the present invention. 6 shows an example of control when a portion corresponding to the data processing unit (604) shown in FIG. 6 is divided into a data processing unit A (703) and a data processing unit B (705). That is, the data stored in the receiving flip-flop (704) when the path delay test is performed on the data sent from the upstream side of the communication path in the processor element (700) constituting the reconfigurable programmable device. In order to propagate changes, the data processing unit is not the logical configuration instruction unit (100) shown in FIG. 1 but the local processor element control unit (701) for controlling the path delay test for each individual component. A (703) is controlled to instruct route fixing. Further, the processing performed during propagation of the data processing unit A (703) solves the correlation in the expected value generation unit (709) or the path delay test result determination unit (708), and generates a test pattern from the upstream side of the communication path. Allows comparison of expected values without propagation. For example, when the route of the data processing unit A (703) is fixed and the logical inversion of the expected value occurs, the expected value generation unit (709) or the route based on the pattern generated by the expected value generation unit (709) The expected value is logically supplemented by supplementing the logical operation executed in the path to the receiving flip-flop (704), such as pattern inversion in the delay test result judging unit (708).
The test pattern generation unit (710) corresponds to the test pattern generation unit (609) illustrated in FIG.

Another embodiment of the present invention is shown in FIG.
FIG. 8 shows an example of the configuration of a processor element that facilitates the path delay test of the present invention. Compared to FIGS. 6 and 7, the points of the test pattern set and the data capture point of the path delay test are as follows. It is characterized in that it is overlapped by the final reception / transmission combination flip-flop (805) in the processor element (800). In this case, since the test pattern set and data capture cannot be performed simultaneously, the test pattern set and data capture are controlled exclusively. That is, when the test pattern is set, the output data selector (804) selects the data on the test pattern generation unit (806) side and sets the test data in the reception / transmission combined use flip-flop (805). At the time of data capture, the input data selector (802) and the data processing unit (803) are fixed to a specific path related to execution, and the output data selector (804) is selected on the input data side. By comparing the output of the reception / transmission combined use flip-flop (805) with the value generated by the expected value generation unit (808) after the next cycle, the path delay test result determination unit (807) performs the path delay test. Get results.

Another embodiment of the present invention is shown in FIG.
FIG. 9 shows an example of the configuration of a processor element that facilitates the path delay test of the present invention. Compared with FIGS. 6, 7, and 8, points of the test pattern set of the path delay test and data capture are shown. This point is characterized in that it is overlapped by the first reception / transmission combination flip-flop (904) in the processor element (900). In this case, since the test pattern set and data capture cannot be performed simultaneously as in FIG. 8, the test pattern set and data capture are controlled exclusively. That is, when the test pattern is set, the output data selector (903) selects the data on the test pattern generation unit (906) side and sets the test data in the reception / transmission combined use flip-flop (904). In addition, when the path delay test is performed after the next cycle, the data processing unit (905) is fixed to a specific path related to execution, and at the time of data capture, the input data selector (902) is fixed to a specific path related to execution. The output data selector (903) is selected on the input data side while being fixed to the path. By comparing the output of the reception / transmission combined use flip-flop (905) with the value generated by the expected value generation unit (908) after the next cycle, the path delay test result determination unit (907) Get results.

FIG. 10 shows an example in which the preferred embodiment described in claim 1 is applied using another embodiment of the present invention.
FIG. 10 shows an example in which an arithmetic unit having two data inputs is used as the data processing unit (604) based on the configuration of the processor element shown in FIG. 6 as an example of the configuration of the processor element.

  That is, the processor element control information (125) is transmitted to the processor element group (1000) from the processor element control unit (100) that controls combinations of paths of all the processor elements, and the connection between the processor elements is determined. . Here, consider the case where the connection status of (1001 to 1009) as the processor element is as shown in FIG. For the longest route (1010) in the effective route, the test pattern generation unit (113) passes through the effective route (1010), and the route delay test expected value generation unit (123) and the route delay test are subject to the route delay test. The path delay test is performed using the system up to the target path delay test result determination unit (122).

  When it is known that the maximum delay is the route (1010), or when there is no problem even if the route delay test of another effective route (for example, 1011) is ignored, the route delay test result of the maximum delay route (1010) Control that allows a path delay test to be focused only on the processor element is possible by the processor element control unit (100) that controls the combination of paths of all the processor elements.

Another embodiment of the present invention is shown in FIG.
FIG. 11 shows an example of the configuration of a processor element that facilitates the path delay test of the present invention. Compared with the example shown in FIG. 6, the configuration of the processor element (1100) includes parts corresponding to the test pattern generation unit (608) and the expected value generation unit (607), the test data generation unit and the expected value generation unit. Is shared as a test pattern generation unit (1101) sharing the same. In a programmable device composed of equivalent processor elements, a logical structure with an equivalent processing unit is often used repeatedly. For this reason, in the path delay test logic implemented simultaneously with the processor element according to claim 4, the correlation between the test pattern and the expected value is often maintained originally, and the test pattern is generated based on this correlation. And the expected value generation unit can be mounted as the same component. This implementation of the processor element (1100) contributes to circuit volume reduction.

  Some programmable devices and devices that dynamically change the logical configuration have a structure as shown in FIG. 12 in which a programmable switch for switching connection between processor elements is an independent arrangement unit. In FIG. 12, as an example, a configuration including nine processor elements and four programmable switches is shown.

  Programmable switches including flip-flops can be classified into any of the processor elements described in FIGS. 6, 7, 8, and 9 in terms of the circuit configuration at the position of the path delay test circuit. For example, the programmable switch (1300) including the flip-flop described in FIG. 13 corresponds to the programmable switch (1210) in FIG. Here, the programmable switch (1300) includes three transmission-side processor elements 0 (1201), processor element 1 (1202), processor element 2 (1203), and three reception-side processor elements 3 (1204), Since it operates as a switch for switching the connection between the processor element 4 (1205) and the processor element 5 (1206), the configuration shown in FIG. 8 can be applied to the input unit in which the connection status changes, and the output unit in which the connection status changes is illustrated in FIG. Nine configurations can be applied.

  Further, a programmable switch that does not include a flip-flop inside FIG. 14 includes a multiplexer in the path delay test target path (126) of the data transmission side processor element 0 (101) and the data reception side processor element 8 (109) in FIG. It can be treated as a special example of FIG. 2 including a demultiplexer. That is, as shown in FIG. 14, when the portion corresponding to the programmable switch (1210) of FIG. 12 is a programmable switch (1400) having a configuration that does not include a flip-flop, a path delay test circuit is inserted into the programmable switch unit. There is no need. The route is fixed according to the logical configuration information, and a route delay test for an effective connection between the processor elements may be performed.

  Furthermore, if the two programmable switches with or without flip-flops described above are connected in multiple stages, they should be treated as equivalent to a multistage processor element or as a derivative based on the above assumptions. Can do.

It is a figure which shows the structure for the effective path | route delay test between processor elements. It is a figure which shows the timing control based on the effective path | route delay test between processor elements. It is a figure which shows the path | route delay test with respect to an invalid path | route, and suppression of timing control. It is a figure which shows the expected value comparison suppression and mask control with respect to the path | route delay test location of an invalid path | route. It is a figure which shows the mask control of the test result with respect to the invalid path | route with respect to a timing control part. It is a figure which shows the structure of the processor element which performs the path | route delay test with respect to an effective path | route. It is a figure which shows the structure of the processor element which performs the path | route delay test with respect to an effective path | route. It is a figure which shows the structure of the processor element which performs the path | route delay test with respect to an effective path | route. It is a figure which shows the structure of the processor element which performs the path | route delay test with respect to an effective path | route. It is a figure which shows the example in the case of implementing a path | route delay test using the processor element of the said FIG. It is a figure which shows the pattern generator which shared the expected value generation of the data from upstream, and the circuit of the test pattern downstream. It is a figure which shows the programmable device which has a programmable switch part as a component. It is a figure which shows the programmable switch part and processor element part containing a flip-flop. It is a figure which shows the programmable switch part and processor element part which do not contain a flip-flop.

Explanation of symbols

100: Logical configuration instruction unit 101: Processor element 0
102: Processor element 1
103: Processor element 2
104: Processor element 3
105: Processor element 4
106: Processor element 5
107: Processor element 6
108: Processor element 7
109: Processor element 8
110: Data processing unit 111 in processor element 0: Output data selector 112 in processor element 0 112: Transmission-side flip-flop 113 in processor element 0: Test pattern generation unit 114: Input data selector 115 in processor element 1: Processor Reception side flip-flop 116 in element 1: Data processing unit 117 in processor element 1: Input data selector 118 in processor element 8: Reception side flip-flop 119 in processor element 8: Data processing unit 120 in processor element 8 : Path delay test result determination unit 121 that is not subject to path delay test: Path delay test expected value generation unit 122 that is not subject to path delay test 122: Path delay test result determination unit 123 that is subject to path delay test: Path delay test Target path delay test expectation value generation unit 124: Path delay test unit 125 distributed in the entire programmable circuit 125: Processor element control information 126: Path delay test target path 127: Path delay test non-target path 200: Path Delay test result totaling unit 201: timing control unit 202: clock control unit 203: control information of data processing unit of processor element 0 204: control information of output data selector of processor element 0 205: input data selector of processor element 8 Control information 206: Control information of the data processing unit of the processor element 8 207: Control information of the path delay test unit 208: Timing control information 209: Path delay test total result information 210: Clock signal 211: Path delay test result information 212: Path Delay test Waiting value information 301: Control information of input data selector of processor element 1 302: Control information of data processing unit of processor element 1 303: Path delay test result information 304: Path delay test expected value information 400: Expected value comparison unit 401: Test result mask mechanism 402: Received data 403: Path delay test enable control information 500: Result totaling processing unit 501: Path delay test result mask circuit of processor element 0 502: Path delay test result mask circuit of processor element 1 503: Processor Path delay test result mask circuit for element n 504: Path delay test enable information for processor element 0 505: Path delay test result for processor element 0 506: Path delay test enable information for processor element 1 507: Processor element Path delay test result 508 of processor element n: path delay test enable information 509 of processor element n: path delay test result 600 of processor element n: processor element 601: controller in processor element 602: input data selector 603: reception side flip-flop 604: Data processing unit 605: Output data selector 606: Transmission side flip-flop 607: Result judgment unit 608: Expected value generation unit 609: Test pattern generation unit 700: Processor element 701: In-processor element control unit 702: Input data selector 703 : Data processing part A
704: Reception side flip-flop 705: Data processing unit B
706: Output data selector 707: Transmission-side flip-flop 708: Result determination unit 709: Expected value generation unit 710: Test pattern generation unit 800: Processor element 801: Processor element internal control unit 802: Input data selector 803: Data processing unit 804 : Output data selector 805: reception / transmission combined use flip-flop 806: result determination unit 807: expected value generation unit 808: test pattern generation unit 900: processor element 901: processor element internal control unit 902: input data selector 903: output data selector 904 : Reception / transmission combined use flip-flop 905: Data processing unit 906: Result determination unit 907: Expected value generation unit 908: Test pattern generation unit 1000: Processor element group 1001: Processor element 0
1002: Processor element 1
1003: Processor element 2
1004: Processor element 3
1005: Processor element 4
1006: Processor element 5
1007: Processor element 6
1008: Processor element 7
1009: Processor element 8
1010: Longest path 1011 in the effective path 1011: Effective path 1012: Test result information 1100 for path delay test target: Processor element 1101: Test pattern generation unit sharing test data generation unit and expected value generation unit: Programmable with processor element Processor element group 1201 consisting of switches: Processor element 0
1202: Processor element 1
1203: Processor element 2
1204: Processor element 3
1205: Processor element 4
1206: Processor element 5
1207: Processor element 6
1208: Processor element 7
1209: Processor element 8
1210: Programmable switch 0
1211: Programmable switch 1
1212: Programmable switch 2
1213: Programmable switch 3
1300: Programmable switch including flip-flop 1400: Programmable switch not including flip-flop

Claims (5)

In a programmable circuit capable of switching the logical configuration,
A plurality of processor elements that are processing units for realizing the functions;
A logical configuration instruction unit for designating interconnection between the processor elements for realizing a function by combining the processor elements;
A path delay test execution unit that performs a delay test on an arbitrary connection path among the effective connection paths between the processor elements that are changed according to the logical configuration instruction unit;
The path delay test execution unit includes a test pattern generation unit that generates a pattern of a path delay test for the individual path formed by the logical configuration information;
A selection circuit for transmitting a path delay test pattern created by the test pattern generation unit to a target path of a path delay test;
A path delay test result determination unit that determines a path delay test result of an individual path by comparing a test pattern received via the target path of the path delay test with an expected value;
An expected value generation unit that generates an expected value to be input to the result determination unit of the path delay test. A programmable circuit that performs a path delay test between the processor elements under arbitrary operating conditions for each logical configuration information,
A path delay test result totaling unit that counts the determination results of individual path delay tests sent from the path delay test result determination unit as a result of the entire programmable circuit;
A timing control unit for instructing timing adjustment based on the counting result of the result counting unit;
The programmable circuit according to claim 1, further comprising: a clock control unit that adjusts a clock cycle based on an instruction from the timing control unit. A programmable circuit that performs a path delay test between the processor elements under arbitrary operating conditions for each logical configuration information,
Based on the logical configuration information, the path delay test is performed by selecting a path by applying a path delay test to an arbitrary path, instructing non-application, or by masking the path delay test result for an arbitrary path delay test target path. The programmable circuit according to claim 1, further comprising a path delay test unit to be implemented. In the programmable circuit that performs a path delay test between processor elements corresponding to an arbitrary operation condition for each logical configuration information, the processor element implemented as a processing unit,
A first flip-flop that receives data from upstream of the communication path;
An expected value generator for generating an expected value for a path delay test upstream of the communication path;
A path delay test result determination unit that compares the output of the first flip-flop and the expected value generated by the expected value generation unit;
A test pattern generation unit for generating a path delay test pattern downstream of the communication path;
A second flip-flop for transmitting data downstream of the communication path;
A processor element comprising: a selector that selectively sets either the test pattern generated by the test pattern or the processing result in the processor element during normal operation to the second flip-flop.   The processor element according to claim 4, further comprising a pattern generation unit that serves as both the test pattern generation unit and the expected value generation unit.

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