JP2006332259A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent gate insulating film breakdown of a MOS transistor by a protection circuit using a pn junction diode formed in such a way that the pn junction diode possesses lower junction breakdown voltage than the destructive breakdown voltage of the gate insulated film. <P>SOLUTION: The pn junction diode element for circuit protection comprises a p-well region 23 formed in a p-type semiconductor board 21, and an n-type diffusion layer 24 formed in the upper part of the p-type semiconductor board 21 in contact with the p-well region 23. The p-well region 23 forms a pn junction interface between adjoining the n-type diffusion layer 24 in the substrate surface. The p-type, and n-type impurities concentration in this pn junction interface are C2 and C1, respectively. Since these are higher than the impurities concentration C3 of the p-wel region 23 in the bottom of the n-type diffusion layer 24, the junction breakdown voltage falls in comparison with the usual pn junction. It can be used as a protection element by connecting this pn junction diode element as a protection element with an input-and-output circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a pn junction diode element for protecting a semiconductor integrated circuit from electrostatic breakdown and a method for manufacturing the same.

  In a semiconductor device, the electrostatic breakdown voltage is improved by installing a protection circuit on an input pad or an input / output pad in order to prevent electrostatic breakdown. The protection circuit is composed of a diode having a pn junction and a normally-off transistor.

  For example, FIG. 8 shows a conventional example in which a pn junction is used as a protection circuit. FIG. 8 shows an input protection circuit formed using diodes D1 and D2 as protection elements. One end of the protective resistor R1 is connected to the signal input terminal 51 connected to the input pad to delay propagation of the surge voltage from the signal input terminal 51 to prevent an excessive current from flowing. Further, pn junction diodes D1 and D2 are provided in series as discharge elements for releasing electric charges between the power supply terminal 52 and the ground terminal 53. Here, the cathode of the pn junction diode D 1 is connected to the power supply terminal 52, and the anode of the pn junction diode D 2 is connected to the ground terminal 53. Therefore, the pn junction diodes D1 and D2 are connected between the power supply terminals 52 and 53 in the reverse direction. When a surge voltage is applied to the signal input terminal 51, the charge is quickly discharged to the power supply terminal 52 or the ground terminal 53 by the reverse avalanche breakdown or forward current of the pn junction diodes D1 and D2, and the protected circuit 54 is protected. Further, by inserting an internal resistor R2 between the protective resistor R1 and the protected circuit 54, it is made difficult for the surge voltage to propagate to the protected circuit 54 (see, for example, Patent Document 1).

  FIG. 9 shows an inverter circuit which is one of typical protected circuits. As shown in FIG. 9, a PMOS transistor Q1 and an NMOS transistor Q2 are connected in series between a power supply terminal 52 and a ground terminal 53, and the gates of the PMOS transistor Q1 and NMOS transistor Q2 are connected in common to an input signal terminal 55, and the drain Are connected to the output signal terminal 56 in common. The input / output protection circuit configured as shown in FIG. 8 functions as an input protection circuit when connected to the input signal terminal 55, and functions as an output protection circuit when connected to the output signal terminal 56. Since the function and operation of the protection circuit are the same for both the input unit and the output unit, they will be described as “input / output protection circuit”. However, a resistor is often not added when used as an output protection circuit.

FIG. 10 is a partial enlarged cross-sectional view of the pn junction diode D2 of the diode-type input / output protection circuit shown in FIG. On the p-type semiconductor substrate 61, a p-well region 62 into which p-type impurities of about 10 ¹⁷ / cm ³ are introduced is formed. An n-type diffusion layer 63 into which an n-type impurity of about 10 ²⁰ / cm ³ is introduced is formed in part of the upper portion of the p-well region 62. The n-type diffusion layer 63 is surrounded by the element isolation oxide film 65 and is electrically isolated from other elements. A silicide layer 64 is formed on the n-type diffusion layer 63. Silicide layer 64 is connected to metal wiring 69 through tungsten 68 in contact hole 67 provided in interlayer insulating film 66.

Although not shown in FIG. 10, the pn junction diode D1 has the same structure as the pn junction diode D2. The pn junction diode D1 has a structure in which the p-well region 62 in FIG. 10 is replaced with an n-well region and the n-type diffusion layer 63 is replaced with a p-type diffusion layer. In this case, the impurity concentrations of the n-well region and the p-type diffusion layer are about 10 ¹⁷ / cm ^{3 and} about 10 ²⁰ / cm ³ , respectively.
JP-A-11-121750 (pages 3-5, 31-35)

  However, in the above-described conventional example, as the miniaturization progresses, the thickness of the gate insulating film of the MOS (Metal Oxide Semiconductor) transistor used in the semiconductor device becomes thinner, thereby making it thinner than the pn junction diode constituting the input / output protection circuit. However, the withstand voltage of the gate insulating film of the MOS transistor of the protected circuit becomes lower, and there is a problem that the pn junction diode becomes useless as a protection circuit.

  In FIG. 8, the thickness of the gate insulating film of the MOS transistor connected from the signal input terminal 51 connected to the input pad via the protective resistor R1 and the internal resistor R2 is conventionally about 10 nm, about 12V. It had a breakdown pressure. On the other hand, the junction of the pn junction diodes D1 and D2 constituting the input / output protection circuit had a breakdown voltage of about 10V. Therefore, since the breakdown voltage of the gate insulating film is higher than the pn junction breakdown voltage, a current flows through the pn junction before the gate insulating film is broken, and as a result, the semiconductor device is prevented from being broken.

  However, with the miniaturization of the semiconductor device, the gate insulating film is also thinned from about 10 nm to about 7 nm. As the film thickness decreases to 7 nm, the breakdown voltage of the gate insulating film decreases to about 8.4V. On the other hand, the pn junction breakdown voltage remains approximately 10 V, and the pn junction breakdown voltage exceeds the breakdown voltage of the gate insulating film. Thus, even if an input / output protection circuit using a pn junction diode is provided, the gate insulating film is destroyed, and the pn junction diode is no longer useful as a protection circuit.

  In view of such circumstances, the present invention provides a highly reliable semiconductor device resistant to electrostatic breakdown and a method for manufacturing the same by simply forming a pn junction diode capable of protecting a thin gate insulating film. The purpose is that.

  In a semiconductor device having a pn junction diode element according to the present invention, a semiconductor region of a certain conductivity type (p well region or n well region) is formed in a semiconductor substrate in the pn junction diode element, and the surface of the semiconductor substrate is further formed. A diffusion layer region having a conductivity type (p-type or n-type) different from that of the semiconductor region is formed on the side. The bottom surface of the diffusion layer region is in contact with the semiconductor region. On the other hand, the semiconductor region extends to the surface of the semiconductor substrate on the side surface of the diffusion layer region. At least part of the surface of the semiconductor substrate, the diffusion layer region and the semiconductor region are in contact with each other to form a pn junction. The impurity concentration of the semiconductor region on the surface of the semiconductor substrate is higher than the impurity concentration of the semiconductor region at the bottom surface of the diffusion layer region (the junction depth position of the diffusion layer region with respect to the semiconductor region).

That is, the present invention is a semiconductor device having a pn junction diode element, and the pn junction diode element is adjacent to a diffusion layer region formed on a semiconductor substrate and at least a part of side surfaces and a bottom surface of the diffusion layer region. A semiconductor region having a conductivity type different from the conductivity type of the diffusion layer region,
The diffusion layer region and the semiconductor region are in contact with each other at least at a part on the surface of the semiconductor substrate,
The impurity concentration of the semiconductor region on the surface of the semiconductor substrate is higher than the impurity concentration of the semiconductor region on the bottom surface of the diffusion layer region.

  In this configuration, the diffusion layer region and the semiconductor region are in contact with each other at least partially on the surface of the semiconductor substrate to form a pn junction. On the other hand, the impurity concentration of the semiconductor region on the surface of the semiconductor substrate is higher than the impurity concentration of the semiconductor region on the bottom surface of the diffusion layer region. Therefore, the pn junction on the semiconductor substrate surface has a higher impurity concentration than the pn junction on the bottom surface of the diffusion layer region. The breakdown voltage of the pn junction diode is determined by the impurity concentration of each of the p-type and n-type, and the breakdown voltage decreases as the impurity concentration increases. For this reason, in a pn junction diode element having a pn junction on the surface of the semiconductor substrate, the junction breakdown voltage is lower than the breakdown voltage of the gate insulating film of the transistor of the protected circuit. That is, a pn junction diode element having a junction breakdown voltage lower than that of the gate insulating film is formed. Therefore, the pn junction diode element can effectively protect the thinned gate insulating film.

  In the above, a compound layer (silicide layer) including a metal element and a main constituent element of the semiconductor region is further formed on at least a part of the outermost surface of the diffusion layer region, and the diffusion layer region of the compound layer is the semiconductor. This is a mode in which it is not formed in a portion in contact with the region.

  According to this, since the compound layer on the diffusion layer region lowers the contact resistance, the performance as a protective element can be improved.

  Further, in the above, there is a preferable aspect in which the main constituent element of the semiconductor region is silicon, and the metal element is at least one selected from titanium, cobalt, nickel, tungsten, and molybdenum.

  Further, in the above, there is an aspect in which an element isolation region is provided on the semiconductor substrate. In this case, at least a part of the diffusion layer region is not in contact with the element isolation region, and the semiconductor region is provided between the diffusion layer region and the element isolation region on at least a part of the surface of the semiconductor substrate. It is done.

  Here, in the portion where the semiconductor region is provided between the diffusion layer region and the element isolation region, the breakdown voltage can be lowered and the function as a protection element is improved, but the junction leakage current may be increased in normal operation. is there. On the other hand, the breakdown voltage cannot be lowered at the portion where the diffusion layer region and the element isolation region are in contact with each other, but the junction leakage current is small. Therefore, in consideration of the current capacity as a protection element, the peripheral length of the part where the diffusion layer region and the element isolation region are in contact and the peripheral length where the diffusion layer region and the element isolation region are not in contact can be freely designed. That's fine.

  In the above, the maximum impurity concentration in the diffusion layer region on the surface of the semiconductor substrate is higher than the gate end impurity concentration in the source / drain region of the MIS (Metal Insulator Semiconductor) transistor of the protected circuit provided on the semiconductor substrate. There is an aspect of increasing the value.

  According to this, the performance as a protection element is ensured by making the breakdown voltage of the pn junction diode element lower than the breakdown voltage of the pn junction formed in the source / drain region of a normal transistor.

  In the above, a protection circuit is formed by connecting the pn junction diode element to at least one of an input terminal, an output terminal, and an input / output terminal of a semiconductor element.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a pn junction diode element,
Forming an element isolation region on a semiconductor substrate;
Forming a semiconductor region having the same conductivity type as that of the semiconductor substrate in at least a portion of the semiconductor substrate;
Forming a diffusion layer region having a conductivity type different from the conductivity type of the semiconductor region in at least a portion of the semiconductor substrate in a state where at least a portion thereof is not in contact with the element isolation region; Including
The diffusion layer region and the semiconductor region are formed in contact with each other at least at a part on the surface of the semiconductor substrate.

  According to this, at least part of the surface of the semiconductor substrate, the diffusion layer region and the semiconductor region come into contact with each other to form a pn junction, and the junction breakdown voltage of that portion is lowered, so that it acts as a protective element. Can do.

  In the manufacturing method, in the step of forming a semiconductor region having the same conductivity type as that of the semiconductor substrate, impurities are introduced under the condition that the impurity concentration on the substrate surface is higher than that in the substrate.

  By increasing the impurity concentration on the surface of the substrate, the breakdown voltage of the pn junction formed on the surface of the substrate can be lowered, and it can function as a protective element.

  In the above manufacturing method, the step of forming the diffusion layer region having a conductivity type different from the conductivity type of the semiconductor region includes a step of introducing impurities a plurality of times using different masks. It is preferable that the impurity introduction region in the step having the highest concentration is in contact with the semiconductor region.

  This increases the impurity concentration of the diffusion layer region on the substrate surface, thereby lowering the breakdown voltage of the pn junction formed on the substrate surface, and more effectively working as a protection element.

  In the manufacturing method described above, the step of forming the diffusion layer region having a conductivity type different from the conductivity type of the semiconductor region includes a step of introducing impurities a plurality of times using different masks. The impurity introduction region other than the process having the highest concentration is inside or equivalent to the impurity introduction region in the process having the highest impurity concentration to be introduced, and only the impurity introduction region other than the process having the highest impurity concentration to be introduced is used. It is preferable not to contact the semiconductor region.

  This is because when the impurity concentration region to be introduced is in contact with the semiconductor region only in the region other than the step where the impurity concentration is highest, the impurity concentration of the diffusion layer region at the junction is low, so the breakdown voltage cannot be lowered, and the performance as a protective element This is because there is a case where it cannot be secured. By avoiding this, the function as a protection element is ensured.

  In the above manufacturing method, when at least two types of transistors are formed on the semiconductor substrate, a semiconductor region having the same conductivity type as that of the semiconductor substrate is formed in at least a part of the semiconductor substrate. There are a plurality of impurity introduction steps for forming the impurity, and only the optimum step among the plurality of impurity introduction steps can be selectively performed in the pn junction diode element formation region.

  For example, when both a 1.2V transistor and a 3.3V transistor are mounted, generally, the threshold concentration implantation of the 1.2V transistor has a higher impurity concentration. Accordingly, a low breakdown voltage can be realized by applying the threshold control injection of the 1.2V transistor to the pn junction diode element formed in the 3.3V transistor region. If a lower breakdown voltage is required, both 1.2V transistor, 3.3V transistor, and two threshold control implants can be applied.

  In the above manufacturing method, in the step of forming the semiconductor region in at least a part of the semiconductor substrate, a step of selectively performing only the pn junction diode element formation region can be added. . A pn junction diode element having optimized characteristics can be realized by this process.

  In the above manufacturing method, when forming at least two kinds of transistors on the semiconductor substrate, an impurity introduction step for forming a diffusion layer region having a conductivity type different from the conductivity type of the semiconductor region is performed a plurality of times. And only the optimum step among the plurality of impurity introduction steps can be selectively performed on the pn junction diode element formation region.

  For example, when both a 1.2V transistor and a 3.3V transistor are mounted, the impurity introduction process of the 1.2V transistor generally achieves a higher impurity concentration. Therefore, a low breakdown voltage can be realized by applying an impurity introduction step for forming a diffusion layer region of a 1.2 V transistor to a pn junction diode element formed in a 3.3 V transistor region. . Further, when a lower breakdown voltage is required, both an impurity introduction step for forming a 1.2V transistor, a 3.3V transistor, and two diffusion layer regions can be performed.

  Further, in the above manufacturing method, in the step of forming the diffusion layer region having a conductivity type different from the conductivity type of the semiconductor region, a step of selectively performing only the pn junction diode element formation region may be added. it can. A pn junction diode element having optimized characteristics can be realized by this process.

  According to the semiconductor device of the present invention, in the pn junction diode element, the diffusion layer region having a different conductivity type and the semiconductor region are in contact with each other on the surface of the semiconductor substrate to form a pn junction. Since the concentration is higher than the impurity concentration of the semiconductor region at the bottom surface of the diffusion layer region, the junction breakdown voltage of the pn junction diode element is lower than the breakdown voltage of the gate insulating film of the transistor of the protected circuit, and the pn junction diode element is thinned. The gate insulating film can be effectively protected.

  Further, according to the method for manufacturing a semiconductor device of the present invention, a pn junction diode having a junction breakdown voltage lower than the breakdown voltage of the gate insulating film of the transistor of the circuit to be protected and effectively protecting the thinned gate insulating film. A semiconductor device having elements can be easily manufactured.

  Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
A semiconductor device and a manufacturing method thereof according to Embodiment 1 of the present invention will be described with reference to FIGS.

  First, the structure of the semiconductor device in this embodiment will be described with reference to FIGS.

  1A is a plan view showing an outline of a pn junction diode element for circuit protection in a semiconductor device, FIG. 1B is a cross-sectional view taken along line AB in FIG. 1A, and FIG. FIG. 2B is an impurity concentration distribution diagram in the substrate at a cross section taken along line CD and line EF in FIG.

  As shown in FIG. 1A, a mask layout for forming a pn junction diode element for circuit protection includes an active region 11, an n-type diffusion layer implantation region 12 provided inside the active region 11, A non-silicided region 13 including at least the outer periphery of the active region 11, a contact hole 14 provided in a region inside the n-type diffusion layer implantation region 12, and a metal wiring 15 for connecting to the contact hole 14. ing.

  As shown in FIG. 1B, a pn junction diode element for circuit protection includes a p-well region 23 formed in a p-type semiconductor substrate 21 and an upper portion of the p-type semiconductor substrate 21 in contact with the p-well region 23. An n-type diffusion layer 24 provided, a silicide layer 26 formed on at least a part of the n-type diffusion layer 24, and an element isolation provided on the p-type semiconductor substrate 21 in contact with the p-well region 23 It is composed of an oxide film 22 and a non-silicide region forming insulating film 25. The n-type diffusion layer 24 and the element isolation oxide film 22 are not in contact with each other on the surface of the semiconductor substrate 21, and the silicide layer 26 is formed only on a part of the n-type diffusion layer 24. It is not formed on the outermost periphery. The non-silicide region forming insulating film 25 includes an outermost peripheral portion of the n-type diffusion layer 24, a portion of the p-well region 23 between the n-type diffusion layer 24 and the element isolation oxide film 22, and an element isolation oxide film 22. It is formed over the upper part and part.

  Here, the interlayer insulating film 27, the contact hole 28, and the tungsten filled in the contact hole 28 for electrically connecting the silicide layer 26 and the p-well region 23 to a desired region without short-circuiting with other regions. 29, and a metal wiring layer 30 electrically connected to the tungsten 29 is provided.

1C, the impurity concentration C4 of the p-type semiconductor substrate 21 is constant in the deep part of the substrate, and the concentration of C3 is higher in the p-well region 23 than C4. Furthermore, on the substrate surface, the concentration is further increased to control the threshold value of the transistor, resulting in a concentration of C2. On the other hand, in the cross section taken along the line EF, the n-type diffusion layer 24 has the same structure as that of the source / drain regions, so that the n-type impurity concentration on the outermost surface is as high as C1. The n-type impurity concentration of the n-type diffusion layer 24 is equal to the concentration C3 of the p-well region 23 at a depth Xj from the surface, and in the region deeper than this, the p-type is the same as the cross section along the line CD. In general, in a semiconductor element formed of a CMOS transistor of 0.25 μm or smaller, C4 is 5 × 10 ^{14 to} 5 × 10 ¹⁵ (cm ⁻³ ), and C3 is 1 × 10 ^{17 to} 3 × 10 ¹⁸ (cm ^{− 3} ), C2 has a concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ (cm ⁻³ ) and C1 has a concentration of 1 × 10 ^{20 to} 5 × 10 ²¹ (cm ⁻³ ), but the present invention is limited to this. It doesn't let you.

  Although the semiconductor device in the present embodiment uses a pn junction diode element in which an n-type diffusion layer is provided in a p-well, conversely, a pn junction diode element in which a p-type diffusion layer is provided in an n-well, and these A combination of both may be used. In the semiconductor device according to the present embodiment, the silicide layer 26 is provided to reduce the resistance of the n-type diffusion layer. However, if the silicide connection can be made without providing the silicide layer 26, the silicide layer 26 is provided. It is not necessary to provide it.

  To describe the above in a higher concept, the pn junction diode element in the semiconductor device is formed adjacent to the diffusion layer region 22 formed on the semiconductor substrate 21 and at least a part of the side surface and the bottom surface of the diffusion layer region 22. In addition, a semiconductor region 23 having a conductivity type different from the conductivity type of the diffusion layer region 22 is provided, and at least part of the surface of the semiconductor substrate 21 is in contact with the diffusion layer region 22 and the semiconductor region 23. The impurity concentration of the semiconductor region 23 on the surface of the semiconductor layer 23 is higher than the impurity concentration of the semiconductor region 23 on the bottom surface of the diffusion layer region 22.

  According to the semiconductor device in this embodiment, a highly reliable semiconductor element resistant to electrostatic breakdown can be provided by simply forming a pn junction diode that can protect a thin gate insulating film. This will be described below.

  The breakdown voltage of the pn junction diode is determined by the impurity concentration of each of the p-type and n-type, and the breakdown voltage decreases as the impurity concentration increases. In a normal n-type diffusion layer, as shown in FIG. 10, the element isolation oxide film 65 and the n-type diffusion layer 63 are in contact with each other, and no pn junction interface is formed on the surface of the semiconductor substrate 61. The pn junction interface is the bottom surface of the n-type diffusion layer 63 as in the cross section taken along the line EF of FIG. 1B. As shown in FIG. 1C, the impurity concentration of each of the p-type and n-type in this case Becomes C3.

  On the other hand, according to the semiconductor device of the present embodiment, the impurity concentration C2 of the p-well region 23 on the substrate surface is higher than C3, as shown in the cross section along line CD in FIG. The p-well region 23 forms a pn junction interface with the adjacent n-type diffusion layer 24 on the substrate surface. The p-type and n-type impurity concentrations at the pn junction interface are C2 and C1, respectively, as shown in FIG. 1C. Since these are higher than C3, the junction breakdown voltage decreases.

  FIG. 2 shows the characteristics of the conventional and pn junction diodes of the present embodiment. Whereas the junction breakdown voltage of the conventional pn junction is about 9.8V, the junction breakdown voltage of the pn junction diode of the present embodiment is about 7.7V, and the breakdown voltage is low as described above. As described above, when the gate insulating film of the MOS transistor used in the semiconductor device is thinned to 7 nm, the breakdown voltage of the gate insulating film is reduced to about 8.4V. When a conventional pn junction is used as the protection circuit, the breakdown voltage of the gate insulating film cannot be prevented because the pn junction breakdown voltage is higher. On the other hand, the junction breakdown voltage of the pn junction diode of this embodiment is about 7.7 V, which is lower than the breakdown breakdown voltage of the gate insulating film 8.4 V, so that a current flows through the pn junction first, resulting in the gate insulating film. Can be prevented.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

  3 to 5 are main-portion process cross-sectional views for explaining the manufacturing process of the pn junction diode element constituting the semiconductor device according to the present embodiment.

  First, as shown in FIG. 3A, an element isolation oxide film 22 is formed on the main surface of a p-type semiconductor substrate 21 by using an STI (Shallow Trench Isolation) method or the like.

Next, as shown in FIG. 3B, boron ions are implanted at 1 × 10 ¹³ at an acceleration energy of 250 keV into at least a part of the p-type semiconductor substrate 21 to form a p-well region 23. . In addition, as an n-channel stopper, boron ions are similarly implanted at a dose of 1 × 10 ¹³ with an acceleration energy of 100 keV. These implantation energies and doses are not limited to the above, but generally 100 to 500 keV, 1 × 10 ¹² to 1 × 10 ¹⁴ in order to form the p-well region 23 having a desired concentration and depth. You can choose between doses. These ion implantations are preferably performed at a tilt angle of about 7 °, but are not limited thereto. Furthermore, it is possible to divide under different implantation conditions with different twist angles as required, and to add a transistor threshold control implantation. In this step, in many cases, a photoresist is formed in a part of the region using lithography (not shown), and the p-well region 23 is not formed in at least a part of the p-type semiconductor substrate 21 in many cases. In this case, an n-well region may be formed in a region where the p-well region 23 is not formed using lithography and ion implantation. As the conditions for forming the n-well region, first, 3 × 10 ¹³ doses of phosphorus ions are implanted at an acceleration energy of 600 keV. In addition, as a p-channel stopper, phosphorus ions are also implanted at a dose of 3 × 10 ¹³ with an acceleration energy of 250 keV. These implantation energies and doses are not limited to the above, but generally 300 to 900 keV, 1 × 10 ^{12 to} 5 × 10 ¹⁴ in order to form the n-well region 22 having a desired concentration and depth. You can choose between doses. These ion implantations desirably have a tilt angle of about 7 °, but are not limited thereto. Furthermore, it is possible to divide under different implantation conditions with different twist angles as required, and to add a transistor threshold control implantation.

Next, as shown in FIG. 3C, a gate insulating film 31 and a gate electrode 32 are formed on the p-type semiconductor substrate 21. As the gate insulating film 31, one or a combination of high dielectric materials such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and Hf (hafnium) oxide can be used. Although a silicon oxynitride film having a thickness of about 7 nm is used here, the material and thickness are not limited to this. On the other hand, as the gate electrode 32, one or a combination of polycrystalline silicon, silicide, and metal can be used. Here, polycrystalline silicon having a thickness of 200 nm is used, and phosphorus is implanted at about 8 × 10 ^{15 at 15} keV at least partially before pattern formation. However, the acceleration energy and dose of the material and ion implantation are limited to the above. It is not something.

Next, as shown in FIG. 3D, an n-type LDD (Lightly Doped Drain) layer 33 is formed on a part of the p-type semiconductor substrate 21 by combining resist pattern formation by ordinary lithography and ion implantation. To do. The photoresist 34 for forming the n-type LDD layer 33 is formed with an opening only in the p-well region 23 that is separated from the element isolation oxide film 22 by a distance A. However, in the MOS transistor formed simultaneously at this time, the n-type LDD layer 33 is formed in a self-aligned pattern with respect to the element isolation oxide film 22 as is conventional. As the ion implantation conditions for forming the n-type LDD layer 33, As ions are implanted at an acceleration energy of 45 keV with a 4 × 10 ¹² dose inclined by 38 ° from the main surface, and the wafer is substrated each time implantation is completed. Rotate by 90 ° with respect to the notch for a total of 4 injections. In addition, P ions are implanted at an acceleration energy of 45 keV with a 4 × 10 ¹² dose inclined by 38 ° from the main surface, and the wafer is rotated by 90 ° with respect to the substrate notch each time implantation is completed. Perform multiple injections. These implantation energies and doses are not limited to the above, and in order to form the n-type LDD layer 33 having a desired concentration and depth, generally 3 to 60 keV, 1 × 10 ¹² to 1 × 10 6. You can choose between ¹⁴ doses. Further, these ion implantations desirably have a tilt angle of about 30 ° to 45 °, but are not limited thereto. The distance A between the photoresist 34 and the element isolation oxide film 22 for forming the n-type LDD layer 33 may be determined in consideration of lithography misalignment and is not limited. In consideration of the accuracy of misalignment and the degree of integration, about 100 nm or more and 1000 nm or less are preferable.

  Next, after implanting the LDD layer formation for the p-type transistor (not shown because it is not implanted into this element), as shown in FIG. 4A, the gate insulating film 31 and the gate electrode 32 are formed. Sidewalls 35 are formed on the side walls. The sidewall 35 is formed by depositing a silicon oxide film having a thickness of about 10 nm and a silicon nitride film having a thickness of about 60 nm sequentially by CVD (Chemical Vapor Deposition), and is formed only on the sidewalls of the gate insulating film 31 and the gate electrode 32 by dry etching. To do.

Next, as shown in FIG. 4B, an n-type diffusion layer 24 is formed on a part of the p-type semiconductor substrate 21 by combining resist pattern formation by normal lithography and ion implantation. The photoresist 36 for forming the n-type diffusion layer 24 is formed with an opening only in the p-well region 23 that is separated from the element isolation oxide film 22 by a distance B. However, in the MOS transistor simultaneously formed at this time, the n-type diffusion layer 24 has a pattern formed in a self-aligned manner with respect to the element isolation oxide film 22 as usual. As ion implantation conditions for forming the n-type diffusion layer 24, first, As ions are implanted with an acceleration energy of 20 keV and a 4 × 10 ¹⁴ dose inclined by 7 ° from the main surface. Next, As ions are implanted with an acceleration energy of 50 keV and a 1 × 10 ¹⁵ dose inclined by 7 ° from the main surface, and the wafer is rotated 90 ° with respect to the substrate notch each time implantation is completed, for a total of 4 times. Make an injection. In addition to this, P ions are implanted at an acceleration energy of 45 keV with an 8 × 10 ¹² dose inclined by 7 ° from the main surface, and the wafer is rotated by 90 ° with respect to the substrate notch each time implantation is completed. Perform multiple injections. These implantation energies and doses are not limited to the above, but generally 3 to 60 keV, 1 × 10 ¹⁴ to 1 × 10 in order to form the n-type diffusion layer 24 having a desired concentration and depth. You can choose between ¹⁶ doses. These ion implantations are preferably performed at a tilt angle of about 7 °, but are not limited thereto. The distance B between the photoresist 36 and the element isolation oxide film 22 for forming the n-type diffusion layer 24 is the distance A between the photoresist 34 and the element isolation oxide film 22 for forming the n-type LDD layer 33 described above. It is desirable that B ≦ A is satisfied, which is equal to or smaller than that of. After that, it may be determined in consideration of lithography misalignment, and there is no limitation. In consideration of the accuracy of misalignment and the degree of integration, it is preferably about 50 nm or more and 950 nm or less.

Next, implantation for forming a p-type diffusion layer for the p-type transistor is performed (not shown because it is not implanted into the device). The p-type diffusion layer is formed by 4 × 10 ¹⁵ dose implantation of boron ions at an acceleration energy of 3 keV. In addition, boron ions may be implanted at about 1 × 10 ¹³ dose with an acceleration energy of 15 keV. These implantation energies and doses are not limited to the above conditions, as in the case of As and phosphorus implantation during the formation of the n-type diffusion layer 24, and a p-type diffusion layer having a desired depth and concentration is formed. Therefore, it is possible to select freely.

  Next, as shown in FIG. 4C, a non-silicide region forming insulating film 25 is formed of a silicon oxide film having a thickness of about 50 nm by ordinary lithography and etching. The non-silicide region forming insulating film 25 includes an outermost peripheral portion of the n-type diffusion layer 24, a p-well region 23 on the substrate surface provided between the n-type diffusion layer 24 and the element isolation oxide film 22, and element isolation. It is provided above a part of the oxide film 22. The width C between the element isolation oxide film 22 and the non-silicide region forming insulating film 25 is the distance A between the photoresist 34 and the element isolation oxide film 22 for forming the n-type LDD layer 33 and the n-type diffusion layer. If it is larger than the distance B between the photoresist 36 for forming 24 and the element isolation oxide film 22, it may be determined in consideration of lithography misalignment, and there is no limitation. In view of the accuracy of misalignment and the degree of integration, about 200 nm or more and 2000 nm or less are preferable.

  Next, as shown in FIG. 5A, a self-aligned silicide process using Co, Ti, Ni or the like is performed, and the n-type diffusion layer 24, the gate electrode 32, the p-type diffusion layer (not shown). A silicide layer 26 is formed thereon. For example, in the case of forming Co silicide, a Co metal thin film is formed to a thickness of about 10 nm, a TiN thin film is continuously formed to a thickness of 10 to 20 nm, heat treated at 400 to 500 ° C., and unreacted Co is removed with an acid. Further, by performing a heat treatment at 700 ° C. to 800 ° C., the silicide layer 26 having a thickness of about 30 to 80 nm can be formed.

  Next, as shown in FIG. 5B, an interlayer insulating film 27 is formed on the p-type semiconductor substrate 21 by using a plasma CVD method or the like. As the interlayer insulating film 27, an organic thin film such as a silicon oxide film, SiOF in which fluorine is introduced into the silicon oxide film, a silicon nitride film, or polyimide can be used.

  Next, as shown in FIG. 5C, a part of the interlayer insulating film 27 is etched by combining resist pattern formation by normal lithography and dry etching, a contact hole 28 is provided in a necessary region, and a contact is formed. The inside of the hole 28 is filled with tungsten 29. After filling, if necessary, planarization is performed by CMP (Chemical Mechanical Polishing) or the like to remove excess tungsten. Next, the metal wiring layer 30 is formed so that the n-type diffusion layer 24 can be electrically connected via the silicide layer 26 and the tungsten 29 inside the contact hole 28. Although not shown, the contact hole 28 is provided not only on the n-type diffusion layer 24 but also on the p-type diffusion layer and the gate electrode so that each can be electrically connected as necessary.

  Although a p-type semiconductor substrate is used in this embodiment, it goes without saying that an n-type semiconductor substrate may be used. Further, the p-type well is formed and the n-type diffusion layer is provided, but conversely, the n-type well may be formed and the p-type diffusion layer may be provided. Further, these may be simultaneously formed on the same semiconductor substrate.

(Embodiment 2)
A semiconductor device and a manufacturing method thereof according to Embodiment 2 of the present invention will be described with reference to FIG.

  In recent years, LSIs have been miniaturized, but the voltage at the portion that is connected to the outside has not changed much. Therefore, the protected circuit is miniaturized and formed with a transistor that operates at a low voltage (currently 1.2 V operation), and the external input / output circuit is formed with a transistor that operates at a high voltage (currently 3.3 V operation). It is common to do. Therefore, it is necessary to form a transistor that operates at a low voltage and a transistor that operates at a high voltage on the same substrate, and a process for each transistor is required.

  FIG. 6 shows the steps of performing the implantation of the 1.2V transistor, the 3.3V transistor, and the pn junction diode element of the present invention. As shown in FIG. 6, when an n-type transistor is taken as an example, the ion implantation for forming the p-well and the implantation for forming the n-type diffusion layer share both the 1.2V transistor and the 3.3V transistor. In many cases, however, implantation for controlling the threshold value of the transistor and implantation for forming the LDD layer are separately required. In the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention, only the step of injecting 3.3V transistors is used as shown in the pn junction 1 of FIG. On the other hand, as described above, for the threshold control implantation and the LDD layer forming implantation, it is necessary to perform the steps for the 1.2 V transistor and the 3.3 V transistor, respectively. Usually, in the implantation process for the 1.2V transistor, the 3.3V transistor region is masked with a photoresist and is not implanted. Conversely, in the implantation process for the 3.3V transistor, the 1.2V transistor is not implanted. Although the region is masked with photoresist and not implanted, there is no such restriction in pn junction diode elements.

  Therefore, as shown in the column of pn junction 2 in FIG. 6, in the pn junction diode element constituting the semiconductor device in the present embodiment, in order to optimize the junction breakdown voltage, threshold voltage control of a 3.3V transistor is performed. Instead of implantation, a threshold voltage implantation of a 1.2V transistor may be performed. Also, both threshold control injections for 3.3V transistors and 1.2V transistors may be performed. Furthermore, although the number of masks increases, instead of these, in order to perform dedicated implantation under optimum conditions for the pn junction diode element, a mask that is implanted only in the pn junction diode element region is created, and implantation is performed under optimum conditions. This injection may be used in combination with a 3.3V transistor threshold control injection or a 1.2V transistor threshold control injection.

  The same applies to the implantation step for forming the LDD layer. In the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention, as shown by the pn junction 1 in FIG. 6, only the implantation step for forming the LDD layer of the 3.3 V transistor is used. Instead, as shown in the column of the pn junction 3 in FIG. 6, an LDD layer forming implantation for a 1.2 V transistor may be performed instead of an LDD layer forming implantation for a 3.3 V transistor. In addition, implantation for forming LDD layers for both 3.3 V transistor and 1.2 V transistor may be performed. Furthermore, although the number of masks increases, instead of these, in order to perform dedicated implantation under the optimum conditions for the pn junction diode element, a mask that is implanted only in the pn junction diode element region is created and implanted under the optimum conditions. Alternatively, this implantation may be used in combination with an implantation for forming an LDD layer of a 3.3V transistor and an implantation for forming an LDD layer of a 1.2V transistor.

  Further, in the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention, as described with reference to FIGS. 3 to 5, the photoresist 36 for forming the n-type diffusion layer 24, the element isolation oxide film 22, This distance B is preferably equal to or smaller than the distance A between the photoresist 34 for forming the n-type LDD layer 33 and the element isolation oxide film 22 and satisfies B ≦ A. However, as described above, when the LDD layer forming implantation is combined and the implantation at a higher concentration than the conventional 3.3V transistor LDD layer forming implantation is performed, a desired breakdown voltage can be obtained even when B> A. May be possible. In this case, it goes without saying that the mask may be designed with B> A.

  A modification of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.

  In the pn junction diode element according to the first embodiment of the present invention, as shown in FIG. 2, the leakage current may be larger than that of the conventional pn junction. Since the leakage current may increase the power consumption of the semiconductor device, it is desirable to reduce the leakage current as much as possible. On the other hand, this leakage current flows not in the bottom surface of the n-type diffusion layer but in the periphery. FIG. 7 shows the analysis result.

  Various patterns were formed by changing the area and peripheral length of the n-type diffusion layer, and each leakage current value when 3.6 V was applied was measured. FIG. 7A shows the relationship between the area of the n-type diffusion layer and the leakage current Median value when 3.6 V is applied. FIG. 7B shows the relationship between the peripheral length of the n-type diffusion layer and the leakage current Median value when 3.6 V is applied. As is clear from FIGS. 7A and 7B, the leakage current shows a good correlation with the peripheral length of the n-type diffusion layer. This indicates that a leak current flows around the n-type diffusion layer. Therefore, in order to suppress the leakage current, it is preferable to make the peripheral length of the n-type diffusion layer as small as possible.

  On the other hand, as shown in FIG. 2, a large current can flow near the junction breakdown voltage, and depending on the standard of the semiconductor device, the performance as a protection circuit is satisfied even if the peripheral length is shortened. Therefore, as shown in FIG. 7C, the junction leakage current is set such that a part of the periphery of the n-type diffusion layer 24 is formed in a self-aligned manner by the element isolation oxide film 22 as in the conventional pn junction. The required performance as a protective element can be ensured.

  In the above embodiment, as a semiconductor constituting the semiconductor substrate 21, silicon, germanium, a compound thereof, a III-V group semiconductor such as GaAs, GaN, or GaP, a II-VI group semiconductor such as ZnSe, or the like is used. Can do.

  INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method thereof according to the present invention are useful for providing a highly reliable semiconductor element that is resistant to electrostatic breakdown by simply forming a pn junction diode that can protect a thin gate insulating film. is there.

The top view of the area | region in which the pn junction diode element for circuit protection of the semiconductor device in Embodiment 1 of this invention is formed (a), Partial expansion of the pn junction diode element along the AB line in (a) Cross-sectional diagrams (b) and (b) Impurity concentration distribution diagram in substrate along cross-section along line CD and line EF (c) Characteristics of conventional and pn junction diodes of the present invention Process sectional view (No. 1) for explaining a manufacturing process of the pn junction diode element in the first embodiment of the present invention (No. 1) Process sectional view (No. 2) for explaining a manufacturing process of the pn junction diode element in the first embodiment of the present invention (Part 2) Process sectional view (No. 3) for explaining a manufacturing process of the pn junction diode element in the first embodiment of the present invention (No. 3) The figure showing each injection implementation process of 1.2V type transistor, 3.3V type transistor, and pn junction diode element in Embodiment 2 of the present invention In Embodiment 3 of the present invention, a diagram (a) of the junction leakage current dependency of the pn junction diode element on the n-type diffusion layer area, a diagram (b) of the junction leakage current dependency on the n-type diffusion layer peripheral length, pn Partial enlarged sectional view of the junction diode element (c) Circuit diagram in the case of using a pn junction as a protection circuit in a conventional semiconductor device Transistor connection diagram of inverter circuit, one of the typical protected circuits Partial enlarged sectional view of a pn junction diode of a diode-type input / output protection circuit in a conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Active area | region 12 N type diffused layer injection | pouring area | region 13 Non-silicided area | region 14 Contact hole 15 Metal wiring 21 P-type semiconductor substrate 22 Element isolation oxide film 23 P-type well area | region 24 n-type diffused layer 25 Insulating film for non-silicided area | region formation 26 Silicide layer 27 Interlayer insulating film 28 Contact hole 29 Tungsten 30 Metal wiring layer 31 Gate electrode 32 Gate insulating film 33 N-type LDD layer 34, 36 Photo resist 35 Side wall

Claims (14)

A semiconductor device having a pn junction diode element,
The pn junction diode element is
A diffusion layer region formed on a semiconductor substrate;
A semiconductor region having a conductivity type different from the conductivity type of the diffusion layer region, formed adjacent to at least a part of the side surface and the bottom surface of the diffusion layer region;
The diffusion layer region and the semiconductor region are in contact with each other at least at a part on the surface of the semiconductor substrate,
A semiconductor device, wherein an impurity concentration of the semiconductor region on a surface of the semiconductor substrate is higher than an impurity concentration of the semiconductor region on a bottom surface of the diffusion layer region.   A compound layer composed of a metal element and a main constituent element of the semiconductor region is further formed on at least a part of the outermost surface of the diffusion layer region, and the compound layer is formed in a portion where the diffusion layer region is in contact with the semiconductor region. The semiconductor device according to claim 1, which is not provided.   The semiconductor device according to claim 2, wherein a main constituent element of the semiconductor region is silicon, and the metal element is at least one selected from titanium, cobalt, nickel, tungsten, and molybdenum.   There is an element isolation region on the semiconductor substrate, and at least part of the diffusion layer region is not in contact with the element isolation region, and the diffusion layer region and the element isolation region are at least part of the surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor region is provided between the first and second semiconductor regions.   The maximum value of the impurity concentration of the diffusion layer region on the surface of the semiconductor substrate is higher than the gate end impurity concentration of the source / drain region of the MIS transistor provided on the semiconductor substrate. Item 5. The semiconductor device according to any one of Items 4 to 4.   6. The semiconductor device according to claim 1, wherein the pn junction diode element is connected to at least one of an input terminal, an output terminal, and an input / output terminal of the semiconductor element. A method of manufacturing a semiconductor device having a pn junction diode element,
Forming an element isolation region on a semiconductor substrate;
Forming a semiconductor region having the same conductivity type as that of the semiconductor substrate in at least a portion of the semiconductor substrate;
Forming a diffusion layer region having a conductivity type different from the conductivity type of the semiconductor region in at least a portion of the semiconductor substrate in a state where at least a portion thereof is not in contact with the element isolation region; Including
A method for manufacturing a semiconductor device, comprising forming the diffusion layer region and the semiconductor region in contact with each other at least at a part of the surface of the semiconductor substrate.   8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the semiconductor region, impurities are introduced under a condition that an impurity concentration on the substrate surface is higher than that in the substrate.   The step of forming the diffusion layer region includes a step of introducing impurities a plurality of times using different masks, and the impurity introduction region in the step of introducing the highest impurity concentration is in contact with the semiconductor region. The method for manufacturing a semiconductor device according to claim 7 or 8.   The step of forming the diffusion layer region includes a step of introducing impurities a plurality of times using different masks, and the impurity introduction region other than the step having the highest impurity concentration to be introduced has the highest impurity concentration to be introduced. 10. The semiconductor device according to claim 7, wherein the semiconductor region is not in contact with only the impurity introduction region other than the step having the highest impurity concentration to be introduced, which is inside or equivalent to the impurity introduction region in the process. A method for manufacturing a semiconductor device according to any one of the above. In a method for manufacturing a semiconductor device in which at least two types of transistors are formed on the semiconductor substrate,
Having an impurity introduction step for forming a semiconductor region having the same conductivity type as the conductivity type of the semiconductor substrate a plurality of times in at least a part of the semiconductor substrate;
11. The method of manufacturing a semiconductor device according to claim 7, wherein only an optimum step among the plurality of impurity introduction steps is selectively performed in the pn junction diode element formation region.   12. The method of manufacturing a semiconductor device according to claim 7, wherein a step of selectively performing only the pn junction diode element formation region is added in the step of forming the semiconductor region. In a method for manufacturing a semiconductor device in which at least two types of transistors are formed on the semiconductor substrate,
Having an impurity introduction step for forming the diffusion layer region a plurality of times,
13. The method of manufacturing a semiconductor device according to claim 7, wherein only an optimum step among the plurality of impurity introduction steps is selectively performed in the pn junction diode element formation region.   14. The method of manufacturing a semiconductor device according to claim 7, wherein a step of selectively performing only the pn junction diode element forming region is added in the step of forming the diffusion layer region.

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