JP2006331107A - Electric power management circuit and electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric power management circuit which improves a processing speed of electronic equipment while restraining total electric power consumption of a plurality of function blocks inside the electronic equipment under permissible electric power, and also provide an electronic circuit. <P>SOLUTION: The electric power management circuit 2 manages the electric power of a plurality of function blocks 6, 7 and 8. Each of the function blocks 6, 7 and 8 operates in a plurality of operating states which change by a state transition. The operating states of the blocks 7, 8 and 9 transit when they output state transition request signals 9, which requests state transitions, to the electric power management circuit 2 and acquire the permission for the state transitions from the electric power management circuit 2. The electric power management circuit 2 is provided with a computing part 3 which computes a posterior-to-transition power consumption value 13, which is a total power consumption value of the plurality of function blocks after their states transit, based on the state transition request signals 9; and a permission part 4 which permits the state transitions based on the state transition request signals 9 when the posterior-to-transition power consumption value 13 is at most a prescribed permissible electric power value 5. By this, an operational speed can be improved without exceeding permissible electric power of electronic equipment. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for increasing the processing speed of an electronic circuit while maintaining an allowable power state.

  Electronic devices such as mobile phones and PDAs obtain power from a portable power source such as a battery in order to ensure portability.

  Recent electronic devices such as mobile phones and PDAs include many functions such as image processing, audio processing, communication processing, and encryption processing. Many of these functions are realized by functional blocks and software such as an electronic circuit mounted in the electronic device, and are often realized by a system LSI in particular.

  The power consumption of the electronic device varies greatly depending on the type of functional block to be executed. For example, power consumption is high when image processing is being performed, but power consumption is low when memory control is being performed.

  Thus, in an electronic device including a plurality of functional blocks with different power consumption, it is preferable that the total power consumption during the operation of the plurality of functional blocks does not exceed the allowable power. Patent Document 1 discloses a technique in which the operation permission of a functional block is restricted in consideration of allowable power.

  FIG. 30 is an internal schematic diagram of a conventional portable device.

  The battery 101 supplies power to the system LSI 103 via the power supply voltage conversion circuit 102. The power supply voltage conversion circuit 102 includes a series regulator, a switching regulator, and the like, and performs voltage conversion in accordance with a voltage required by the system LSI 103.

  FIG. 31 is a block diagram of a conventional power management system, which is disclosed in Patent Document 1. In FIG.

  The monitoring circuit 116 monitors operation requests from the functional blocks 113 and 114. When the monitoring circuit 116 detects the operation request, the monitoring circuit 116 notifies the power management mechanism 115. The power management mechanism 115 calculates the total power consumption of the functional block that has output the operation request, and permits the operation of the functional block when the total power consumption does not exceed the allowable power consumption.

  As a result, the total power consumption is suppressed below the allowable power, the battery operating time and the electronic device operating time are extended, and excessive heat generation is prevented.

  However, in the conventional technology, only the maximum power during the operation of the functional block is considered when determining permission for the operation request of the functional block. That is, the difference in power consumption due to the difference in the operation state of the functional block is not considered. That is, even when the same functional block operates, depending on the operating state, there are cases where high power is required and low power is required, but in the conventional technology, depending on the operating state in this same functional block Differences in required power are not considered.

  For this reason, depending on the operating state, even though the actual total power consumption is less than or equal to the permissible power, it is permitted based on the maximum power during operation, so an extra function block that does not permit operation is generated. There was a problem. For this reason, there has been a problem that the processing time is unnecessarily prolonged and the performance of the electronic device is lowered.

In particular, in the prior art in which the operation permission is determined based only on the maximum power during operation, there has been a problem that the processing time of a functional block having a high processing priority exceeds the time limit.
JP 2003-202935 A

  Accordingly, an object of the present invention is to provide a power management circuit and an electronic circuit that improve the processing speed of the electronic device while suppressing the total power consumption of a plurality of functional blocks inside the electronic device to be equal to or lower than the allowable power.

  A power management circuit according to a first aspect of the present invention is a power management circuit that manages the power of a plurality of functional blocks, wherein each of the plurality of functional blocks operates in a plurality of operating states that change due to a state transition, When the state transition request signal for requesting the power management circuit is output to the power management circuit and permission for the state transition is received from the power management circuit, the operation state transitions, and the power management circuit performs a plurality of operations based on the state transition request signal. A calculation unit that calculates a post-transition power consumption value that is a total power consumption value after the state transition of the functional block, and a state transition based on the state transition request signal when the post-transition power consumption value is equal to or less than a predetermined allowable power value. The permission part to permit is provided.

  With this configuration, the state transition permission determination is made after comparison with the allowable power based on the power consumption for each operation state, not the maximum power consumption or average power consumption of the functional block. For this reason, the power consumption is determined in finer units. Furthermore, the processing speed can be increased while maintaining the allowable power.

  In the power management circuit according to the second invention, the state transition request signal includes information indicating states before and after the state transition.

  With this configuration, the calculation unit can calculate both the total power consumption value of the plurality of functional blocks in the current state and the total power consumption value of the plurality of functional blocks after the transition.

  In the power management circuit according to the third invention, the plurality of functional blocks include a processor that operates based on a program.

  With this configuration, even in a functional block that operates in a more complicated operating state, power management and permission for state transition are reliably performed.

  A power management circuit according to a fourth aspect of the present invention includes a holding unit that holds an operation state signal and a state transition request signal.

  With this configuration, the power management circuit can easily grasp a state transition request from a plurality of functional blocks.

  In the power management circuit according to the fifth aspect, the calculation unit calculates the post-transition power consumption value when the content held by the holding unit changes.

  With this configuration, it is possible to minimize the operation of the calculation unit and the permission unit and to reduce the power consumption of the power management circuit itself.

  In the power management circuit according to the sixth aspect of the invention, the calculation unit calculates a difference value of the total power consumption values before and after the state transition of the plurality of functional blocks, and the permission unit has a difference value equal to or less than a predetermined value. The state transition based on the state transition request signal is permitted.

  With this configuration, it is possible to reduce the burden on the power supply due to power fluctuations. By reducing this burden, the life of the power source can be extended.

  In the power management circuit according to the seventh aspect of the invention, the allowable power value is a power value obtained by subtracting the power consumption value of a specific functional block from the power value allowed for the entire plurality of functional blocks.

  With this configuration, the state transition of a specific functional block is not inhibited regardless of the state transition request of another functional block.

  In the power management circuit according to the eighth aspect of the invention, the specific functional block has a time constraint on the time required for the state transition.

  With this configuration, a specific functional block is allowed to undergo state transition including other functional blocks, while keeping the time constraint in the state transition.

  In the power management circuit according to the ninth aspect of the invention, the specific function block is not allowed to stand by at the time of state transition.

  With this configuration, a specific function block does not need to wait for a state transition.

  In the power management circuit according to the tenth invention, each of the plurality of functional blocks has an operational priority, there are a plurality of state transition request signals within a predetermined period, and the power consumption value after transition is an allowable power. When the value exceeds the value, the permission unit permits the state transition of the functional block having a high priority among the functional blocks that output the state transition request signal.

  With this configuration, even when the state transition requests compete, the state transition according to the operation priority is permitted. For this reason, a state transition that matches the specifications relating to the processing of the electronic circuit is made.

  In the power management circuit according to the eleventh aspect, the predetermined period is equal to or shorter than the period of the shortest transition time among the transition times required for the state transition of the plurality of functional blocks.

  With this configuration, processing for a plurality of state transition request signals is reliably performed.

  In the power management circuit according to the twelfth aspect, the state transition based on the state transition request signal output from the functional block for which permission has not been obtained is suspended.

  With this configuration, even when state transition is not permitted, the state transition request is not abandoned, and permission is determined again at the next opportunity.

  In the power management circuit according to the thirteenth aspect of the present invention, the function block for which permission has not been obtained is transitioned to the idle state.

  With this configuration, unnecessary power consumption is reduced.

  In the power management circuit according to the fourteenth aspect, each of the plurality of functional blocks has an operational priority, and when the post-transition power consumption value exceeds the allowable power value, the permission unit is in operation. The function block that outputs the state transition request signal is allowed after at least one of the frequency reduction and stop of the clock signal to the function block that has a lower priority than the function block that outputs the state transition request signal. To do.

  According to this configuration, permission of state transition for a functional block having a high priority is more reliably performed.

  In the power management circuit according to the fifteenth aspect, each of the plurality of functional blocks has an operational priority, and when the power consumption value after transition exceeds the allowable power value, the permission unit is in operation. In addition, a function block having a lower priority than the function block that has output the state transition request signal is transitioned to the idle state, and then the state transition of the function block that has output the state transition request signal is permitted.

  According to this configuration, permission of state transition for a functional block having a high priority is more reliably performed.

  An electronic circuit according to a sixteenth aspect includes a plurality of functional blocks that operate in a plurality of operation states that change due to state transitions, and a power management circuit that manages power of the plurality of functional blocks, and each of the plurality of functional blocks includes When the state transition request signal for requesting the state transition is output to the power management circuit and permission for the state transition is received from the power management circuit, the operation state transitions, and the power management circuit is based on the state transition request signal. A calculation unit that calculates a post-transition power consumption value, which is a total power consumption value after state transition of a plurality of functional blocks, and a state transition request signal when the post-transition power consumption value is equal to or less than a predetermined allowable power value A permission unit that permits state transition is provided.

  With this configuration, the state transition permission is determined by comparing with the allowable power based on the power consumption for each operation state, not the maximum power consumption or average power consumption of the functional block. For this reason, the power consumption is determined in finer units. Furthermore, the processing speed can be increased while maintaining the allowable power.

  According to the present invention, since the total power consumption of the functional blocks included in the electronic device is suppressed to an allowable power or less, the operation time of the battery and the electronic device is increased.

  Further, since the power consumption for each operation state of the functional block is referred to in the operation permission control for the operation request of the functional block, the operation permission for more functional blocks can be given in the same period. For this reason, the electronic device can operate at high speed without exceeding the allowable power.

  Further, the operation specification is not hindered by the state transition permission determination based on the allowable power value obtained by subtracting the power consumption in the functional block having a high processing time constraint in advance.

  Furthermore, in the operation permission for the functional block, the processing priority for each functional block is taken into consideration, so that the power is managed in accordance with the processing restriction. In addition, the state transition is permitted more efficiently by reducing the clock frequency of the functional block having a low priority when determining whether to permit the state transition.

  In addition, since the total power consumption of the plurality of functional blocks is suppressed to an allowable power or less, the required capacity of the power supply voltage conversion circuit can be reduced, and the electronic device can be downsized.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
First, the outline about a power management circuit and an electronic circuit is demonstrated using FIG. 1, FIG.

  1 and 2 are block diagrams of the electronic circuit according to Embodiment 1 of the present invention.

  The power management circuit 2 includes a calculation unit 3, a permission unit 4, and a memory 12, and the memory 12 holds a predetermined allowable power value. Moreover, you may provide the holding | maintenance part 11 as FIG. 2 shows.

  Around the power management circuit 2, a first functional block 6, a second functional block 7, and a third functional block 8, which are a plurality of functional blocks that perform arbitrary operation processing, are arranged. The first function block 6, the second function block 7, and the third function block 8 include a state transition in which the operation state changes. Therefore, the first function block 6 to the third function block 8 output a state transition request signal 9 for requesting a state transition to the calculation unit 3 (or the holding unit 11) when the state transition occurs. The permission unit 4 outputs a permission signal 10 for the state transition request from the first function block 6 to the third function block 8 based on consideration of the allowable power value 5.

  The memory 12 only needs to be a storable element such as a register.

  Next, details of each part of the power management circuit 2 will be described.

  First, the calculation unit 3 will be described.

  The calculation unit 3 calculates the total power consumption of the functional blocks provided in the electronic circuit 1 based on the state transition request signal 9 from each functional block (in FIG. 1 and FIG. 2, the first functional block 6 to the third functional block 8). Calculate the value. At this time, the state transition request signal 9 indicates a state before and after the state transition. That is, since the state transition request signal 9 is a signal representing a transition from one state to another state in a certain functional block, the calculation unit 3 can recognize the states before and after the state transition. Here, the calculation unit 3 has information regarding the power consumption value in each state of each functional block, and a plurality of functional blocks (from the first functional block 6 to the third functional block 8 in FIGS. 1 and 2). The total power consumption value before the state transition can be calculated. Similarly, the total power consumption value after state transition (power consumption value 13 after transition) can be calculated.

  That is, with the reception of the state transition request signal 9, the calculation unit 3 calculates both the post-transition power consumption value 13 when a state transition occurs in addition to the current total power consumption value before the state transition. .

  When the state transition request signal 9 is received, both the total power consumption value before the state transition and the total power consumption value after the state transition are not calculated. What is necessary is just to calculate the total power consumption value after the transition. Thus, the current total power consumption value is grasped until a new state transition request signal 9 is received, and the post-transition power consumption value 13 is calculated when the new state transition request signal 9 is received, The total power consumption value before and after the state transition is grasped.

  The calculation unit 3 outputs the calculated post-transition power consumption value 13 to the permission unit 4.

  When the holding unit 11 is provided, the state transition request signal 9 from each functional block is based on the state transition request signal 9 held in the holding unit 11 and the calculation unit 3 calculates the power consumption value after transition. 13 is calculated. At this time, when the content held by the holding unit 11 changes, the calculation unit 3 calculates the post-transition power consumption value 13. Only when the content held by the holding unit 11 changes, the calculation unit 3 performs the calculation work, so that the power consumption in the power management circuit 2 is reduced.

  The calculation unit 3 may calculate not only the total power consumption value of a plurality of functional blocks provided in the electronic circuit 1 but also the total power consumption value including peripheral circuits and the like. Alternatively, when there are a plurality of power supply systems, the total power consumption value is calculated only for the functional block group to be subjected to power management. In particular, the total power consumption value of only functional blocks connected to the power management circuit 2 may be calculated.

  Next, the permission unit 4 will be described.

  The permission unit 4 receives the calculated post-transition power consumption value 13 from the calculation unit 3. The permission unit 4 compares the predetermined allowable power value 5 held in the memory 12 with the post-transition power consumption value 13.

  Here, the predetermined allowable power value 5 is a power value that can be supplied to a plurality of functional blocks (in FIGS. 1 and 2, the first functional block 6 to the third functional block 8) provided in the electronic circuit 1. . For example, when the electronic circuit 1 is incorporated in a portable electronic device, a power value that allows the battery to maintain a sufficient operating time is used as the allowable power value 5.

  The permission unit 4 compares the post-transition power consumption value 13 with the allowable power value 5, and if the post-transition power consumption value 13 does not exceed the allowable power value 5, the state transition of the functional block that has output the state transition request signal 9 Allow. When the post-transition power consumption value 13 falls within the allowable power value 5 due to the state transition, the permission unit 4 permits the state transition to prevent a state exceeding the allowable power value.

  Moreover, the permission part 4 outputs the permission signal 10 with respect to the functional block which output the state transition request signal 9 in permission of a state transition. The permission signal 10 is connected to, for example, an enable signal for state transition in the functional block. Thus, the actual switching of the state transition is easily realized in each functional block by the permission signal 10.

  For example, when the first function block 6 outputs the state transition request signal 9 and the post-transition power consumption value 13 is less than or equal to the allowable power value 5, the permission unit 4 permits the first function block 6 to The signal 10 is output. The first function block 6 makes a state transition to a desired state by the permission signal 10 and starts an operation after the state transition.

  Conversely, when the post-transition power consumption value 13 exceeds the allowable power value 5, the permission unit 4 does not output the permission signal 10 for the first functional block 6. The state transition of the first function block 6 is suspended, and is in a standby state until the next time the power consumption value 13 after the transition changes. For example, when a separate state transition request signal 9 is received from another functional block (second functional block 7 and third functional block 8 in FIGS. 1 and 2), the pending first functional block 6 The post-transition power consumption value 13 is newly calculated from the power after the state transition and the power after the transition of a new other functional block. If the newly calculated post-transition power consumption value 13 is equal to or less than the allowable power value 5, the permission signal 10 is output for the state transition of the first functional block 6 that has been suspended.

  As described above, the transition of the operation state of the plurality of functional blocks is performed without exceeding the allowable power value 5.

  The calculation unit 3 may calculate not only the post-transition power consumption value 13 but also the difference value of the total power consumption before and after the state transition. In this case, the permission unit 4 compares the difference value with a predetermined value, and outputs a permission signal 10 to the functional block that has output the state transition request signal 9 when the difference value is equal to or smaller than the predetermined value. .

  The permission unit 4 can suppress a change in power consumption by determining permission of state transition based on the difference value. For this reason, a load on a power source such as a battery due to power fluctuation is reduced, and the electronic device in which the electronic circuit 1 is incorporated operates for a long time.

  Note that the predetermined allowable power value 5 may be a power value obtained by removing the maximum power consumption value of a specific functional block from the power value allowed for the entire plurality of functional blocks.

  By removing the maximum power consumption value of a specific functional block in advance, the operation of the functional block that needs to be preferentially operated is ensured.

  The specific functional block is, for example, a functional block having a time constraint on the time required for state transition. It is a functional block that has a plurality of operation states, has a time restriction in the transition of the operation state, and is inappropriate for being subject to the state transition permission by the power management circuit 2. If the maximum power consumption value of such a specific functional block is removed in advance, a specific functional block with a time constraint surely makes a state transition regardless of the power supply state to other functional blocks. be able to.

  Similarly, a functional block in which standby at the time of state transition is unacceptable, a functional block having an operation priority of a certain level or more may be set as a specific functional block.

  For example, when the first function block 6 is a specific function block, the power value excluding the maximum power consumption value of the first function block 6 is handled as the allowable power value 5.

  The specific functional block may be singular or plural.

  Next, details of the operation of the power management circuit 2 will be described using the operation state of each functional block.

  First, details of the first functional block 6 will be described.

  FIG. 3 is a block diagram of the first functional block according to Embodiment 1 of the present invention.

  The first functional block 6 includes a management unit 20, a direct memory access (drawing and hereinafter referred to as “DMA”) controller 21, a random access memory (drawing and hereinafter referred to as “RAM”) 22, an arithmetic circuit. 23 and a register 24 are provided.

  The first functional block 6 includes a state transition in which a plurality of operation states transition, and the management unit 20 manages the state transition. Therefore, the management unit 20 outputs the state transition request signal 9 to the power management circuit 2 and receives the permission signal 10 from the power management circuit 2. Based on the permission signal 10, the management unit 20 executes a state transition of the operation state inside the first functional block 6.

  The DMA controller 21 transfers data between the external memory of the first functional block 6 and the RAM 22. The arithmetic circuit 23 performs various arithmetic processes such as image processing and sound processing. The arithmetic circuit 23 reads out data from the RAM 22 and performs arithmetic processing, and writes the data after the arithmetic processing into the RAM 22. The register 24 is used for setting the DMA controller 21 and the like.

  The first functional block 6 has the state transition shown in FIG. FIG. 4 is a state transition diagram of the first functional block according to Embodiment 1 of the present invention.

  Each state shown in FIG. 4 will be described below.

  State ST1: The operating state is an idle state. This is a state after resetting or after completion of other operations. The power consumption in the state ST1 is 50 mW.

  State ST2: The operation state is a DMA transfer state. The DMA controller 21 transfers data between the external memory and the RAM 22. The power consumption in state ST2 is 300 mW.

  State ST3: The operation state is a calculation state. Predetermined arithmetic processing is performed by the arithmetic circuit 23. The power consumption in state ST3 is 500 mW.

  State ST4: The operation state is a DMA transfer state. As in the state ST2, the power consumption is 300 mW.

  Moreover, the 1st functional block 6 has the time interval of a state transition, as FIG. 5 shows. FIG. 5 is a timing chart showing state transition of the first functional block according to Embodiment 1 of the present invention. The relationship with the time for each state transition shown in FIG. 5 indicates the shortest time for the state transition, and the state transition may be realized by taking a longer time than the time shown in FIG. That is, in FIG. 5, the state transitions to the state ST2 at time t1 and transitions to the state ST3 at time t3, but the transition from the state ST2 to the state ST3 may take more time.

  Next, details of the second functional block 7 will be described. FIG. 6 is an internal block diagram of the second functional block according to Embodiment 1 of the present invention.

  The second functional block 7 includes a management unit 31, a digital signal processor (in the drawing, and hereinafter referred to as “DSP”) 30, a bus interface 32, a host interface 33, a ROM 34, and a RAM 35. The second functional block 7 performs audio processing, for example.

  The management unit 31 manages state transitions of the second functional block. The bus interface 32 controls data access between the DSP 30 and the external memory. The host interface 33 controls data access between the DSP 30 and an external processor or other functional block. The DSP 30 performs processing such as voice compression and decompression, and operates according to a program stored in the ROM 34. The RAM 35 holds data processed by the DSP 30.

  The second functional block 7 has the state transition shown in FIG. FIG. 7 is a state transition diagram of the first functional block according to Embodiment 1 of the present invention.

  Each state shown in FIG. 7 will be described below.

  State ST10: The operation state is an idle state. The power consumption in state ST10 is 100 mW.

  State ST11: The operation state is a data transfer state. In this state, data is transferred from the external memory to the RAM 35 via the bus interface 32. The power consumption in state ST11 is 300 mW.

  State ST12: The operating state is a DSP processing state. In the DSP 30, data processing is being executed. The power consumption in state ST12 is 500 mW.

  State ST13: The operation state is a data transfer state. The power consumption in state ST13 is 300 mW.

  Further, the second functional block 7 has a time interval of state transition as shown in FIG. FIG. 8 is a timing chart showing state transition of the second functional block according to Embodiment 1 of the present invention. The time required for the state transition shown in FIG. 8 is the shortest time, and the state transition may be realized by taking a longer time than the time shown in FIG.

  As shown in FIG. 8, at time t1, transition is made from state ST10 to state ST11, and at time t3, transition is made from state ST11 to state ST12. Furthermore, at time t6, the state transitions from state ST12 to state ST13, and returns to state ST10 at time t7.

  Next, details of the third functional block 8 will be described.

  FIG. 9 is an internal block diagram of the third functional block according to Embodiment 1 of the present invention.

  The third functional block 8 includes a management unit 40, a DMA controller 41, a FIFO 42, a receiving circuit 43, and a register 44.

  The receiving circuit 43 receives data from the outside, and the DMA controller 41 transfers data to the external memory via the FIFO 42. The DMA controller 41 performs data transfer when the data held in the FIFO 42 exceeds a certain amount. The management unit 40 manages these state transitions.

  The third functional block 8 has the state transition shown in FIG. FIG. 10 is a state transition diagram of the third functional block according to Embodiment 1 of the present invention.

  Each state shown in FIG. 10 will be described below.

  State ST20: The operating state is an idle state. The power consumption in state ST20 is 50 mW.

  State ST21: The operation state is a data reception state. The receiving circuit 43 is receiving data from the outside. The power consumption in state ST21 is 100 mW.

  State ST22: The operation state is a DMA transfer state. The data accumulated in the FIFO 42 is being transferred by the DMA controller 41. The power consumption in state ST22 is 300 mW.

  The third functional block 8 has a time interval for state transition as shown in FIG. FIG. 11 is a timing chart showing state transition of the third functional block according to Embodiment 1 of the present invention. In FIG. 11, the shortest time is shown as the time required for the state transition, and the state transition may take a longer time than this time.

  As shown in FIG. 11, at time t1, the state transitions from state ST20 to state ST21, and at time t6, transitions to state ST22.

  The above three functional blocks will be described with reference to FIGS. 12 and 13 assuming that the power management circuit 2 manages the allowable power value 5 of 1000 mW.

  FIG. 12 is a process flowchart of the power management circuit according to the first embodiment of the present invention.

  First, the operation starts at step 1, and the operation starts at step 2.

  In step 3, the presence / absence of a state transition request is confirmed. When the power management circuit 2 receives the state transition request signal 9, the calculation unit 3 calculates the post-transition power consumption value 13 in step 4. In step 5, the permission unit 4 compares the calculated post-transition power consumption value 13 with the allowable power value 5. As a result of the comparison, if the post-transition power consumption value 13 is the allowable power value 5 or less, the permission unit 4 outputs a permission signal 10 in response to the state transition request. On the other hand, when the post-transition power consumption value 13 is larger than the allowable power value 5, the transition request is suspended and is judged again when another state transition request signal 9 is generated.

  Next, details of the state transition will be described with reference to FIG.

  FIG. 13 is a diagram showing state transition of the electronic circuit according to the first embodiment of the present invention.

  The horizontal axis represents the time interval, and t1, t2, etc. described on the time axis are the same as t1, etc. shown in FIG.

  In order from the top, the transition requests of the first functional block 6, the second functional block 7, and the third functional block 8 and the status of the state transition are shown. The power value described at the top is an actual power consumption value within the period. A state transition request signal 9 is output from each functional block, and a series of flows in which the power management circuit 2 calculates a post-transition power consumption value 13 and permits transition is shown. Hereinafter, it demonstrates along the order of time.

  From time t0 to t1, the first functional block 6 is in the state ST1, the second functional block 7 is in the state ST10, and the third functional block 8 is in the state ST20. Further, the total power consumption value from the first function block 6 to the third function block 8 in this period is 200 mW.

  At time t1, each of the first function block 6, the second function block 7, and the third function block 8 outputs a state transition request signal 9. The calculation unit 3 calculates a post-transition power consumption value 13 that is a total power consumption value after state transition. Here, since the transition is made to the state ST2, the state ST11, and the state ST21, the calculation unit 3 calculates the post-transition power consumption value 13 as 700 mW. Since 700 mW is 1000 mW or less which is an allowable power value, the permission unit 4 outputs a permission signal 10 for all state transitions, and all state transitions are executed. The power consumption after executing the state transition is 700 mW.

  Next, the state transition request signal 9 is output from the first function block 6 and the second function block 7 at time t3. Here, after the state transition of the first functional block 6, the state is ST3, and the power consumption is 500 mW. Further, after the state transition of the second functional block, the state is ST12, and the power consumption is 500 mW. Since the third functional block 8 is in the state ST21 and the power consumption is 100 mW, the post-transition power consumption value 13 is calculated as 1100 mW, which exceeds the allowable power value of 1000 mW. For this reason, the permission unit 4 permits only the state transition of either the first function block 6 or the second function block 7. In FIG. 13, the permission unit 4 permits only the state transition of the second function block 7. In this way, when a transition request conflicts, it is permitted based on, for example, priority.

  The state transition request signal 9 of the first function block 6 is suspended (for example, held by a register in the holding unit 11 or the calculation unit 3), and the state transition request signal 9 of the second function block 7 is The permission signal 10 is output, and the second functional block 7 transits to the state ST12. At this time, the total power consumption value is 900 mW.

  Next, at time t6, the second function block 7 and the third function block 8 output the state transition request signal 9. Since the new state transition request signal 9 gives an opportunity to change the power consumption value 13 after the transition, permission is determined including the state transition request signal 9 of the first function block 6 that has been suspended.

  The calculation unit 3 calculates a post-transition power consumption value 13 in the states ST3, ST13, and ST22, which are states after the state transition. At this time, since the post-transition power consumption value 13 is calculated as 1100 mW exceeding the allowable power value 5, all transition requests are not permitted. Here, the transition request for the first function block 6 and the transition request for the second function block 7 that have been suspended are permitted, and the transition request for the third function block 8 is suspended. Therefore, the first function block 6 transits to the state ST3, the second function block 7 transits to the state ST13, and the third function block 8 remains in the state ST21.

  Next, at time t7, the second functional block 7 outputs a new state transition request signal 9. For this reason, the permission unit 4 also determines the pending transition request for the third function block 8.

  After the state transition of the second functional block 7 (transition to the state ST10) and after the state transition of the third functional block 8 (transition to the state ST22), the calculation unit 3 sets the post-transition power consumption value 13 to 900 mW. calculate. Since the post-transition power consumption value 13 is an allowable power value of 5 or less, all state transitions are permitted. Therefore, the second function block 7 transits to the state ST10, the third function block 8 transits to the state ST22, and the first function block 6 maintains the state ST3.

  Next, at time t8, the first function block 6 and the third function block 8 output a new state transition request signal 9. The first function block 6 outputs a request for transition to the state ST4, and the third function block 8 outputs a request for transition to the state ST20. The calculation unit 3 calculates a power consumption value 13 after state transition. Here, the post-transition power consumption value 13 is calculated as 450 mW and is an allowable power value of 5 or less. For this reason, all transition requests are permitted, and the permission unit 4 outputs a permission signal 10 to the first function block 6 and the third function block 8.

  Finally, at time t10, the first functional block outputs the state transition request signal 9 and transitions to the state ST1 in the idle state. In this flow, the operation based on a series of state transitions from the first function block 6 to the third function block 8 is completed.

  As is apparent from the above, the power management circuit 2 in the first embodiment executes the transition permission based on the power consumption for each operation state, so the operations from the first function block 6 to the third function block 8 are All the processing ends at the processing time t10.

  On the other hand, when the operation permission is determined based on the maximum power consumption of the functional block as in the prior art, a longer processing time is required. The first function block 6 and the second function block 7 have a maximum power consumption of 500 mW, and the third function block has a maximum power consumption of 400 mW. For this reason, when the allowable power value 5 is 1000 mW, the operation of only up to two functional blocks is permitted at the same time. For this reason, each functional block requires a time t7, and a series of processing ends. Therefore, only two functional blocks operate from time t0 to t7, and the remaining one functional block from t7 to t14. Works. For this reason, time t14 is required to complete the operation of the three functional blocks.

  Alternatively, when the allowable power value is 900 mW, the power management circuit 2 and the electronic circuit 1 in the first embodiment similarly finish the processing of the three functional blocks at time t10. On the other hand, in the conventional technique, only one functional block can be operated at the same time, and processing of three functional blocks requires time t21.

  As is clear from this, the power management circuit 2 and the electronic circuit 1 in the first embodiment improve the processing speed while maintaining the allowable power value or less. As a result, the operation time of the electronic device is ensured and the performance is improved.

  In particular, in the case of an electronic circuit composed of a large number of functional blocks, operation permission based on such power management is performed in the entire process, thereby preventing a state in which an allowable power value in an arbitrary period is exceeded. Thus, the life of the battery or the like is increased.

  If any of the first function block 6 to the third function block 8 has a time restriction in the state transition, or the waiting at the time of the state transition is unacceptable, this function block The power value obtained by removing the maximum power consumption value from the power values allowed for the three functional blocks as a whole may be determined as the allowable power value 5. In this case, the state transition of a specific functional block is always ensured. For example, when the second functional block 7 is a specific functional block, a power value obtained by subtracting the maximum power consumption value 500 mW of the second functional block 7 from the power value allowed for the whole is set as the allowable power value 5. It can be handled.

  In addition, when a plurality of state transition request signals 9 are accepted and all state transitions are not permitted and are suspended, the suspended functional block is forcibly consumed the lowest power in the initial state, the idle state, etc. It may be changed to a state.

  A process in which the functional block is forcibly shifted to an idle state or the like when the state transition is suspended will be described with reference to FIGS. 14 to 17.

  FIG. 14 is a diagram illustrating state transition of the electronic circuit according to the first embodiment of the present invention.

  The timing related to the state transition is the same as that shown in FIG.

  At time t3, both the first functional block 6 and the second functional block 7 output the state transition request signal 9. Here, the state transition from the allowable power value 5 to the first function block 6 is not permitted and is suspended. In FIG. 13, the first functional block 6 remains in the state ST2, but here it is forcibly transitioned to the state ST1 in the idle state. This is because the power consumption in the state ST1 is the smallest.

  Therefore, the total power consumption value from time t3 to time t6 is 650 mW, which is smaller than 900 mW in FIG. Therefore, the battery life and the like become longer.

  Similarly, when the state transition of the third function block 8 is suspended at time t6, the third function block 8 is forcibly transitioned to the state St20 in the idle state.

  The state transition in each functional block based on FIG. 14 is shown in FIGS. FIG. 15 is a state transition diagram of the first functional block according to the first embodiment of the present invention, FIG. 16 is a state transition diagram of the second functional block according to the first embodiment of the present invention, and FIG. It is a state transition diagram of the 3rd functional block in form 1 of.

  As is clear from FIG. 15, the first functional block 6 is forcibly transitioned to the state ST1 with the lowest power consumption between time t3 and time t6. Similarly, as is apparent from FIG. 17, the third function block 8 is forcibly transitioned to the state ST20 from time t6 to t7. On the other hand, as is apparent from FIG. 16, the second function block 7 is not forcedly transitioned.

  As described above, when the state transition is suspended, the state may be forcibly transitioned to a state with the least power consumption, such as an initial state or an idle state. This forced transition reduces the overall power consumption and extends the operation period.

  The allowable power value 5 may be a constant value or a variable value.

  For example, a variable value in which the allowable power value 5 decreases according to the remaining battery level is also preferable in terms of extending the operating time.

  Although the first embodiment has been described on the assumption that there are three functional blocks, other numbers may be used.

(Embodiment 2)
Next, a second embodiment will be described. In the second embodiment, in the power management circuit and electronic circuit described in the first embodiment, state transition request signals from a plurality of functional blocks compete and all state transitions cannot be permitted from the viewpoint of the allowable power value. explain.

  FIG. 18 is a block diagram of an electronic circuit according to the second embodiment of the present invention. Description of elements having the same reference numerals as those described in Embodiment 1 is omitted.

  The first function block 50, the second function block 51, and the third function block 52 each include a state transition in which the operation state changes.

  The holding unit 11 is arbitrarily provided.

  In the electronic circuit 1 shown in FIG. 18, the state transition request signals 9 from a plurality of functional blocks may compete. For example, the first functional block 50 and the second functional block 51 may output the state transition request signal 9 at the same time. At this time, the first function block 50 and the second function block 51 may output the state transition request signal 9 at the same time, or the first function block 50 and the second function block 51 are in the state at the same time within a predetermined period. The transition request signal 9 may be output.

  Here, the predetermined period is a minimum period for determining whether to permit state transition, and is, for example, the minimum among the state transition periods (periods required for transition from one state to the next state) possessed by a plurality of functional blocks. Period is used. By setting the minimum period required for the state transition to be a predetermined period, permission determination processing is performed for the plurality of state transition request signals 9 without delay. The plurality of state transition request signals 9 are received and held by the holding unit 11 or a register in the calculation unit 3.

  Furthermore, when all the state transitions based on the plurality of state transition request signals 9 are not permitted due to the relationship with the allowable power value, the permission unit 4 needs to select and permit one of the state transitions.

  In this selective permission for a plurality of state transitions, the priority for each functional block is used as a reference. For example, when the state transition request signal 9 from the first function block 50 and the second function block 51 competes and only one of the allowable power values 5 can be permitted, the first function block 50 and the second function block 51 Judgment is made based on the difference in priority.

  For example, when the priority of the first function block 50 is higher than the priority of the second function block 51, the permission unit 4 outputs a permission signal 10 to the first function block 50, and the second function block 50 The state transition request signal 9 from the block 51 is held in the holding unit 11 and the calculation unit 3, and the state transition is suspended. With respect to the state transition from the second functional block 51 that has been put on hold, it is determined whether it is permitted or not at the next timing.

  Here, the next timing is a timing at which a new state transition request signal 9 is accepted. This is because the post-transition power consumption value 13 changes at the timing when a new state transition request signal 9 is accepted. At this next timing, based on the newly calculated post-transition power consumption value 13 and the priority, the permission unit 4 determines permission / non-permission for the state transition of the second functional block 51 that is suspended. To do.

  At this time, the second function block 51 may stand by while maintaining the current state because the state transition is suspended. However, in order to reduce the overall power consumption, the state may be changed to an initial state or an idle state (a state with the lowest power consumption) during standby.

  For example, when the current state of the second functional block 51 is “data reception state” and after the state transition is “data compression state”, the “data reception state” is maintained even if the state transition is suspended. There is no need to At this time, the state of the second functional block 51 is changed to the “idle state”. Thereby, the power consumption of the second functional block 51 in standby is reduced, and the power consumption of the entire electronic circuit is also reduced.

  With reference to FIG. 19, permission / denial of state transition based on priority will be described.

  FIG. 19 is a diagram showing state transition of the electronic circuit according to the second embodiment of the present invention.

  There are three functional blocks from the first functional block 50 to the third functional block 52, and the priority is higher in the order of the first functional block 50, the second functional block 51, and the third functional block 52. The first functional block has three states, a state ST30 (power consumption is 100 mW), a state ST31 (power consumption is 500 mW), and a state ST32 (power consumption is 200 mW). The second functional block 51 has three states: a state ST40 (power consumption is 100 mW), a state ST41 (power consumption is 500 mW), and a state ST42 (power consumption is 200 mW). The third functional block 52 has two states, a state ST50 (power consumption 300 mW) and a state ST51 (power consumption 400 mW).

  The allowable power value 5 is 1000 mW.

  First, from time t0 to time t1, the first functional block 50 is in the state ST30, the second functional block 51 is in the state ST40, the third functional block 52 is in the state ST50, and the total power consumption value Is 500 mW.

  At time t1, the first function block 50 and the second function block 51 output the state transition request signal 9. At this time, the first functional block 50 requests a state transition from the state ST30 to the state ST31, and the second functional block 51 requests a state transition from the state ST40 to the state ST41. For this reason, the calculation unit 3 calculates the post-transition power consumption value 13 as 1300 mW. Since the post-transition power consumption value 13 exceeds the allowable power value 5, the permission unit 4 cannot permit both state transitions. Here, since the priority of the first function block 50 is higher than the priority of the second function block 51, the state transition of the first function block 50 is permitted, and the state transition of the second function block 51 is suspended. . As a result, after time t1, the first functional block 50 is in the state ST31, and the second functional block 51 remains in the state ST40. The total power consumption value is 900 mW, and the allowable power value is observed.

  Next, at time t2, a new state transition request signal 9 is output from both the first function block 50 and the third function block 52, and the state transition of the suspended second function block 51 is also permitted. Judgment is made.

  The calculation unit 3 calculates a post-transition power consumption value 13, and the post-transition power consumption value 13 is calculated as 1100 mW. Since this exceeds the allowable power value 5, the permission unit 4 cannot permit all state transitions. Here, since the priority of the 3rd functional block 52 is the lowest, the state transition of the 1st functional block 50 and the 2nd functional block 51 is permitted. When these two state transitions are permitted, the post-transition power consumption value 13 is 1000 mW and does not exceed the allowable power value 5. The state transition of the third function block 52 is suspended.

  Next, at time t3, a new state transition request signal 9 is output from the second function block 51, the state transition of the third function block 52 that has been suspended is also permitted, and the second function block 51 enters the state ST42. The third function block 52 transits to the state ST51.

  Thus, the state transition of each functional block is permitted without exceeding the allowable power value by the processing according to the priority. As a result, power consumption is suppressed.

  When the state transition is suspended, the state may be transitioned to a state with the lowest power consumption such as an initial state or an idle state. At this time, for example, even if a functional block that is not a target of state transition and has a low priority is forcibly shifted to an idle state, state transition is permitted for a functional block with a high priority. good.

  Alternatively, the power consumption of this functional block is reduced by reducing and / or stopping the frequency of the clock signal for the functional block with low priority during operation, and then for the functional block with high priority. The state transition may be permitted.

  For example, the state transition request signal 9 from the first functional block 50 and the second functional block 51 competes at time t1 in FIG. At this time, since the post-transition power consumption value 13 is calculated as 1300 mW, the state transition of the second functional block 51 having a low priority is suspended. However, the clock signal for the third function block 52 having a lower priority than the second function block 51 may be stopped here, and the state transition of the second function block 51 may be permitted. When the clock signal to the third function block 52 is stopped, the power consumption of the third function block 52 becomes approximately 0 mW, and even if the state transition of the second function block 51 is permitted, the power consumption value after the transition is 1000 mW. Therefore, the post-transition power consumption value 13 does not exceed the allowable power value 5. As a result, state transition of the second functional block 51 is permitted at time t1.

  In addition to the processing based on the priority, the permission unit 4 may preferentially permit state transition with a long holding period.

  Further, the permission unit 4 may execute the permission of the state transition in consideration of the permission of the state transition based on the priority and the adjustment of the clock frequency.

  In addition, when the state transition request signal competes, when the state transition is suspended, the forced transition to the initial state or the idle state is as shown in FIGS. 14 to 17 as an example.

(Embodiment 3)
Next, Embodiment 3 will be described.

  FIG. 20 is a block diagram of an electronic circuit according to Embodiment 3 of the present invention. The processor 302 is connected to other circuits and the like via the internal bus 305. The ROM 303 stores a program used by the processor 302. A clock generator (“CLKGEN” in the drawing) 327 supplies a clock signal to each functional block. The first function block 307, the second function block 308, and the third function block 309 have the same internal structure and state transition as described in the first embodiment.

  Each functional block outputs a signal representing the current operation state and the state after transition to the power management circuit 306. The power management circuit 306 outputs a permission signal that permits state transition to each functional block.

  Further, the clock generator 327 outputs a clock supply request signal relating to each functional block to the power management circuit 306.

  The clock generator 327, which is set to supply clocks to the individual functional blocks from the processor 302, receives a clock supply request from the power management circuit 306, and starts clock supply to the functional blocks.

  In addition, after the clock supply to the functional block is started, the clock generator 327 supplies a clock having a cycle sufficient for the functional block that started the clock supply to complete the internal reset, and then releases the reset of the functional block.

  The power management circuit 306 includes a calculation unit and a permission unit inside, and permits state transition of each functional block based on the priority of each functional block and the power consumption value after transition.

  The power management circuit 306 also adjusts the supply of a clock signal to each functional block in addition to the permission of state transition. Furthermore, when the state transition is permitted, the power management circuit 306 takes into consideration the difference in power consumption depending on the supply state of the clock signal to each functional block.

  The state transition permission / non-permission processing in consideration of the presence / absence of a clock signal, the priority, the power consumption value after transition, and the like will be described with reference to FIGS.

  FIGS. 21 and 22 are operation flowcharts of the power management circuit according to the third embodiment of the present invention.

  Hereinafter, each step will be described.

  Step 1101: Reset the electronic circuit.

  Step 1102: In the calculation unit in the power management circuit 306, the total power consumption value is initialized, and the calculation of the power consumption value of the functional block can be started.

  Step 1103: It is determined whether the clock supply request signal from the clock generator 327 has been withdrawn for a certain functional block.

  Step 1104: When it is determined that the clock supply request signal has been withdrawn, the power value after stopping the clock signal of the functional block that is the determination target in Step 1103 is applied to the total power consumption value.

  Step 1105: The processing from Step 1103 to Step 1104 is repeated for the clock supply request signal in all functional blocks.

  Step 1106: It is determined whether there is a functional block that has newly entered a standby state.

  Step 1107: When there is a functional block that is newly in the standby state, the power value after the standby state is applied to the total power consumption value.

  Step 1108: Steps 1106 to 1107 are repeated for all functional blocks.

  Step 1109: Maximize the priority of the functional block currently being processed.

  Step 1110: In the target functional block, it is determined whether the clock signal is not supplied and the clock supply is being requested.

  Step 1111: If it is determined in step 1110 that a clock supply is being requested, the total power consumption when the clock is supplied to the target functional block is compared with the allowable power value.

  Step 1112: If it is determined in step 1110 that the total power consumption when the clock signal is supplied to the target functional block is equal to or less than the allowable power value, clock supply to the block is permitted.

  Step 1113: The total power consumption value when the clock is supplied to the target functional block is applied to the total power consumption value.

  Step 1114: It is determined whether or not there is a state transition request signal from the target functional block.

  Step 1115: When there is a state transition request signal in Step 1114, the total power consumption value after the state transition is compared with the allowable power value.

  Step 1116: In step 1115, if it is determined that the post-transition power consumption value when the state transition is permitted to the block requesting the state transition is equal to or less than the allowable power value, the power management circuit 306 Allow state transitions.

  Step 1117: The power value after the state transition permission for the target functional block is applied to the total power consumption value.

  Step 1118: It is determined whether the total power consumption value has decreased. In the case of a decrease, the processing returns to step 1109 so that the clock supply and the state transition permission are preferentially performed for the functional block having a high processing priority, and the processing is repeated again from the block having a high priority. .

  Step 1119: It is determined whether processing has been completed for all functional blocks. When the processing is completed for all the functional blocks, the processing is repeated from step 1110.

  Step 1120: If there is an unprocessed function block in step 1119, the function block to be processed is treated as a function block with one lower priority, and the processing from step 1110 is repeated.

  As described above, the power management circuit 306 determines permission / non-permission of state transition in accordance with the priority of the functional block in consideration of power consumption that varies depending on the presence / absence of clock supply.

(Embodiment 4)
Next, a fourth embodiment will be described.

  FIG. 23 is a block diagram of an electronic circuit according to Embodiment 4 of the present invention.

  A signal 1901 from the power management circuit 306 to the clock generator 327 is added to the electronic circuit shown in FIG. A signal 1901 instructs to stop or reduce the frequency of the clock signal supplied to each functional block.

  The power management circuit 306 according to the fourth embodiment performs at least one of stopping and reducing the clock signal to the low-priority functional block in response to a state transition request from the high-priority functional block, so that the priority is high. Allow state transition to functional block.

  The operation of the power management circuit 306 will be described with reference to FIGS.

  24 and 25 are operation flowcharts of the power management circuit 306 in Embodiment 4 of the present invention. The description of the same reference numerals as those in FIGS. 21 and 22 is omitted.

  In the flowcharts shown in FIGS. 24 and 25, the “Yes” path in steps 1111 and 1114 and the “Yes” path in steps 1105 and 1119 are compared to the flowcharts shown in FIGS. 21 and 22. Process 1 is added during this period.

  Processing 1 will be described with reference to FIG. FIG. 26 is an operation flowchart of process 1 in the fourth embodiment of the present invention.

  Reference numerals 1601, 1602, and 1603 are connection points with the flowcharts shown in FIGS.

  Step 1701: It is determined whether or not there is a function block that has a lower processing priority than the target function block currently being determined and is operating. If it does not exist, the flow of process 1 is exited from the connection point 1603.

  Step 1702: If it is determined in Step 1701 that there is a function block with low priority during operation, the power management circuit 306 instructs the clock generator 327 to reduce the frequency of the clock signal for this function block. To do. Receiving the instruction, the clock generator 327 reduces the frequency of the clock signal for the functional block to be instructed.

  At this time, when there are a plurality of low-priority functional blocks in operation, the clock generator 327 reduces the frequency of the clock signal with respect to the lowest-priority functional block. Or when it is necessary to reduce the frequency of a some functional block, the frequency of a some functional block is reduced from the low priority order.

  Step 1703: The total power consumption value when the clock of the corresponding functional block is reduced is applied to the total power consumption value.

  Through the above processing 1, the overall power consumption is adjusted, and the state transition of the functional block having a high priority is permitted, or the clock supply to the functional block having a high priority is permitted.

  Next, a mode in which the processing in the power management circuit 306 can be observed from the outside will be described.

  FIG. 27 is a block diagram of an electronic circuit according to Embodiment 4 of the present invention. In the power management circuit 306, an output signal 2201 to the outside is added.

  FIG. 28 is a block diagram of power management circuit 306 according to Embodiment 4 of the present invention.

  The power management circuit 306 includes a status output interface 2301. The status output interface 2301 notifies the operating status to the outside via the output signal 2201.

  The state output interface 2301 receives a signal indicating the current state of each functional block and the state after the transition, and a permission signal to each functional block. Further, a clock supply request signal from the clock generator is input.

  With these input signals, the state output interface can recognize the state inside the electronic circuit. Furthermore, the recognized status can be notified to the outside.

  FIG. 29 is an internal block diagram of the status output interface according to Embodiment 4 of the present invention.

  The status output interface 2301 includes a parallel / serial conversion unit 2401 and a transmission circuit 2402.

  The parallel / serial conversion unit 2401 receives signals 310, 311, and 322 indicating the current state from each functional block in parallel and converts them into serial signals. Similarly, the parallel / serial conversion unit 2401 receives the state transition request signals 313, 314, and 315 from each functional block in parallel, and converts them into serial signals. The parallel / serial conversion unit 2401 converts the clock supply request signal 336 and the clock supply permission signal 332 into serial signals.

  The transmission circuit 2402 outputs these converted serial signals to the outside.

  With this configuration, the operation and state inside the electronic circuit including the power management circuit 306 can be observed from the outside.

  Based on the observed information, the priority of each functional block and the adjustment of the clock frequency are performed.

  INDUSTRIAL APPLICABILITY The present invention can be suitably used in electronic devices that require reduced power consumption and high performance, for example, electronic devices that are driven by a portable power source such as a portable terminal.

1 is a block diagram of an electronic circuit according to Embodiment 1 of the present invention. 1 is a block diagram of an electronic circuit according to Embodiment 1 of the present invention. The block diagram of the 1st functional block in Embodiment 1 of this invention State transition diagram of first functional block according to Embodiment 1 of the present invention Timing chart showing the state transition of the first functional block in the first embodiment of the present invention The internal block diagram of the 2nd functional block in Embodiment 1 of this invention State transition diagram of first functional block according to Embodiment 1 of the present invention Timing chart showing state transition of second functional block according to Embodiment 1 of the present invention The internal block diagram of the 3rd functional block in Embodiment 1 of this invention State transition diagram of third functional block according to Embodiment 1 of the present invention Timing chart showing state transition of third functional block in embodiment 1 of invention Processing flowchart of power management circuit in Embodiment 1 of the present invention The figure which shows the state transition of the electronic circuit in Embodiment 1 of this invention The figure which shows the state transition of the electronic circuit in Embodiment 1 of this invention State transition diagram of first functional block according to Embodiment 1 of the present invention State transition diagram of second functional block according to Embodiment 1 of the present invention State transition diagram of third functional block according to Embodiment 1 of the present invention The block diagram of the electronic circuit in Embodiment 2 of this invention The figure which shows the state transition of the electronic circuit in Embodiment 2 of this invention The block diagram of the electronic circuit in Embodiment 3 of this invention Operation flowchart of power management circuit in Embodiment 3 of the present invention Operation flowchart of power management circuit in Embodiment 3 of the present invention The block diagram of the electronic circuit in Embodiment 4 of this invention Operation flowchart of power management circuit 306 in Embodiment 4 of the present invention Operation flowchart of power management circuit 306 in Embodiment 4 of the present invention Operation flowchart of processing 1 in Embodiment 4 of the present invention The block diagram of the electronic circuit in Embodiment 4 of this invention Block diagram of power management circuit 306 in Embodiment 4 of the present invention Internal block diagram of status output interface in embodiment 4 of the present invention Internal schematic diagram of a conventional portable device Block diagram of a conventional power management system

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic circuit 2 Power management circuit 3 Calculation part 4 Permit part 5 Allowable power value 6 1st function block 7 2nd function block 8 3rd function block 9 State transition request signal 10 Permit signal 11 Holding part 12 Memory 20 Management part 21 DMA Controller 22 RAM
23 arithmetic circuit 24 register 30 DSP
43 receiver circuit 101 battery 102 power supply voltage conversion circuit 103 system LSI
111 Processor 112 Memory 113, 114 Function Block 115 Power Management Mechanism 116 Monitoring Circuit

Claims (17)

A power management circuit for managing the power of a plurality of functional blocks,
Each of the plurality of functional blocks operates in a plurality of operation states that change due to a state transition, and outputs a state transition request signal that requests the state transition to the power management circuit, and the state transition from the power management circuit The operating state transitions when permission for
The power management circuit calculates a post-transition power consumption value that is a total power consumption value after state transition of the plurality of functional blocks based on the state transition request signal;
A power management circuit comprising a permission unit that permits state transition based on the state transition request signal when the post-transition power consumption value is equal to or less than a predetermined allowable power value. The power management circuit according to claim 1, wherein the state transition request signal includes information indicating states before and after the state transition. The power management circuit according to claim 1, wherein the plurality of functional blocks include a processor that operates based on a program. The power management circuit according to claim 1, further comprising a holding unit that holds the operation state signal and the state transition request signal. 5. The power management circuit according to claim 1, wherein the calculation unit calculates the post-transition power consumption value when content held in the holding unit changes. 6. The calculation unit calculates a difference value of total power consumption values before and after the state transition of the plurality of functional blocks, and the permission unit outputs a state transition request signal when the difference value is a predetermined value or less. The power management circuit according to any one of claims 1 to 5, wherein state transition is permitted. The power management circuit according to claim 1, wherein the allowable power value is a power value obtained by subtracting a power consumption value of a specific functional block from a power value allowed for the plurality of functional blocks as a whole. The power management circuit according to claim 7, wherein the specific functional block has a time restriction on a time required for the state transition. The power management circuit according to claim 7, wherein the specific function block is unacceptable for standby during state transition. Each of the plurality of functional blocks has an operational priority, and when there are a plurality of the state transition request signals within a predetermined period and the power consumption value after the transition exceeds the allowable power value, The power management circuit according to any one of claims 1 to 9, wherein the permission unit permits state transition of the functional block having a higher priority among the functional blocks that output the state transition request signal. The power management circuit according to claim 10, wherein the predetermined period is equal to or shorter than a period of a shortest transition time among transition times required for the state transition of the plurality of functional blocks. The power management circuit according to any one of claims 10 to 11, wherein a state transition based on the state transition request signal output from a functional block for which the permission has not been obtained is suspended. The power management circuit according to any one of claims 10 to 11, wherein the function block for which permission has not been obtained is transitioned to an idle state. Each of the plurality of functional blocks has an operational priority, and when the post-transition power consumption value exceeds the allowable power value, the permission unit is operating and the state transition request signal 2. The state transition of the functional block that outputs the state transition request signal is permitted after at least one of frequency reduction and stop of the clock signal to the functional block having a lower priority than the functional block that outputs the state is allowed. The power management circuit according to any one of 9 to 9. Each of the plurality of functional blocks has an operational priority, and when the post-transition power consumption value exceeds the allowable power value, the permission unit is operating and the state transition request signal The function block having the lower priority than the function block that outputs the state is allowed to transition to an idle state, and then the state transition of the function block that has output the state transition request signal is permitted. Power management circuit. A plurality of functional blocks that operate in a plurality of operation states that change by state transition;
A power management circuit for managing power of the plurality of functional blocks;
Each of the plurality of functional blocks outputs a state transition request signal for requesting the state transition to the power management circuit, and an operation state transitions when permission for the state transition is received from the power management circuit,
The power management circuit calculates a post-transition power consumption value that is a total power consumption value after state transition of the plurality of functional blocks based on the state transition request signal;
An electronic circuit comprising a permission unit that permits state transition based on the state transition request signal when the power consumption value after transition is equal to or less than a predetermined allowable power value. The electronic circuit according to claim 16, wherein the functional block includes a management unit that manages the operation state, and the management unit outputs the state transition request signal to the power management circuit.

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