JP2006330228A - Plasma display device and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an address electrode drive circuit of a plasma display device which makes transition time of an address signal approximately constant without being influenced by the change directions of the adjacent address signals, prevents generation of erroneous lighting of pixels and electromagnetic radiation and requires only a small amount of power consumption. <P>SOLUTION: The address electrode drive circuit is provided with an output circuit 64A having two output MOSFETs Q11 and Q12 in serial forms and which is connected to any of signal lines of the plasma display device and a drive circuit 63A including a transistor Q1 for constant current and supplies constant current to gate capacity of the output MOSFETs when Q1, one of the output MOSFETs is made from off state to on state according to an input signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique that is effective when applied to a driving circuit of a plasma display device, and more particularly to an address electrode driving circuit (address driver) that drives an address line (address electrode) orthogonal to a scanning line of the plasma display device. It relates to effective technology.

  Plasma display panels (hereinafter referred to as PDPs) include an AC type PDP that emits light by generating an alternating current voltage and a DC type PDP that emits light by generating a direct current voltage. In any case, basically, various layers such as conductive layers and insulating layers to be electrodes are formed and bonded to two glass substrates, and a gas such as Ne that generates ultraviolet rays by discharge is sealed inside. Yes. Among these, the ribs (partitions) for forming discharge cells are in the form of cells in the DC type PDP, whereas the ribs in the AC type PDP are in the form of stripes, so the structure of the AC type PDP is simpler.

  In addition, the AC type PDP is selected by using a counter discharge type in which sustain discharge and selective discharge are performed with two opposing electrodes, and a third electrode in which sustain discharge is performed between two electrodes in the same plane. There are surface discharge types that perform discharge. Here, a schematic configuration of the display panel of the surface discharge type PDP will be briefly described with reference to FIG. Note that the display panel shown in FIG. 1 is an example of a reflective display panel having excellent luminance characteristics.

On the front substrate 11, X electrodes 12x and Y electrodes 12y for sustain discharge are alternately arranged in parallel in a stripe shape. These electrodes 12x and 12y are transparent electrodes made of ITO, Cr, A bus electrode made of Cu or the like is used. Further, the electrodes 12x and 12y are covered with a transparent dielectric layer 13 made of glass or the like, and a protective film 14 made of MgO or the like is formed on the discharge surface.
On the other hand, an address line (also referred to as a data electrode or an address electrode) 16 for selective discharge is disposed on the rear substrate 15 in a direction orthogonal to the electrodes 12x and 12y. Further, the address lines 16 are covered with a white dielectric layer 17, and partition walls (ribs) 18 are formed in stripes along the address lines 16. Inside the partition wall 18, fluorescent layers 19a, 19b, and 19c of three colors of R (red), G (green), and B (blue) are regularly arranged for visible light emission and colorization. Has been.

  The front substrate 11 and the rear substrate 15 on which various conductive layers and insulating films are formed are bonded by a seal layer (not shown) formed around the substrate so that the partition wall 18 and the protective film 14 are in close contact with each other. . Also, a space for sandwiching the two substrates is filled with a gas for generating ultraviolet rays when a discharge occurs.

A PDP display panel 10 having the above configuration, an address driver for applying a voltage for driving the address line 16 of the display panel, a scan driver for applying a voltage for driving the X and Y electrodes 12x and 12y of the display panel, An AC type PDP is configured by a sustain driver, a control circuit, and the like that generate a voltage for sustain discharge. Then, a voltage is applied between the X electrode 12x and the address line 16 by the address driver and the scanning driver to perform selective discharge, and a voltage is applied between the X and Y electrodes 12x and 12y by the sustain driver to cause a sustain discharge. As a result, the light emission display on the display panel 10 is executed. As an invention related to a semiconductor integrated circuit for driving address electrodes of a plasma display, there is an invention described in Patent Document 1, for example.
JP 2004-325705 A

  As shown in FIG. 2, main loads of the address driver in the AC type PDP are a coupling capacitor (hereinafter referred to as a sustain capacitor) Cs between the sustain electrode and the scan electrode, and an address signal for driving an adjacent pin. A capacitance between the wirings (hereinafter referred to as an adjacent pin capacitance) Cp. Of these load capacitors, the sustain capacitor Cs is almost constant, but the adjacent pin capacitor Cp is invisible when the adjacent address signal changes in the same direction as itself. That is, the load of the address driver varies depending on the direction of change of the adjacent address signal.

  Here, when the adjacent address signal changes in the opposite direction, the amount of change is doubled and the load appears to be larger, but by shifting the timing between when the address signal rises and when it falls , Such an increase in load can be avoided. Therefore, the load on the address driver in the case of such timing control is small when the adjacent address signal changes in the same direction as itself, and when the adjacent address signal does not change (including when the adjacent address signal changes in the opposite direction). Will grow. In the PDP, the adjacent pin capacitance when the adjacent address signals do not change reaches approximately the same size as the sustain capacitance.

  By the way, in the evaluation of the PDP, there are a black and white display mode in which white and black are alternately displayed every several lines, and a staggered display mode in which the display is inverted between adjacent dots. In the monochrome display mode, all the bits change in the same direction, that is, adjacent address signals change in the same direction, so that the load is the smallest. In the staggered display mode, the adjacent address signals change in opposite directions, so the load becomes the largest. When the load of the address driver fluctuates in this way, as shown in FIG. 3, the address output rises or falls steeply in the monochrome display mode and rises or falls gently in the staggered display mode, whereby the address signal transition time. Also changes. FIG. 4 shows the relationship between the load magnitude and the address signal transition time in a PDP using a conventional address driver.

  As a result of examination by the present inventors, when the load of the address driver in the monochrome display mode is about 20 pF and the address transition time is about 20 ns (nanosecond), the load of the address driver in the staggered display mode is about 50 pF. It was found that the transition time is about 45 ns, which is about twice as long. Here, if the address transition time is long, there is a possibility that a pixel to be lit does not illuminate or a pixel that should not be lit is lit. A design is made to increase the driving force of the address driver so that the time falls within a predetermined time.

  However, in the PDP using the address driver having such a large driving force, there is a problem that electromagnetic radiation is generated from the address line because the change of the address signal in the monochrome display mode is too steep. In order to prevent such a problem, some conventional PDPs take measures such as putting a transparent electromagnetic wave shielding film on the surface of the panel. However, when such measures are taken, another problem of increasing the cost of the PDP occurs.

  In order to solve such a problem, the gate capacitance of the output MOSFET (insulated gate field effect transistor) constituting the address driver is charged / discharged by a constant current source provided in the level shift circuit in the previous stage, so that a desired through An invention in which the output is changed at a rate has been previously proposed by the present inventors (Japanese Patent Laid-Open No. 2004-325705).

  However, in this prior application, the switch in series with the constant current source is configured to be turned on / off by a control pulse. For this reason, it has been found that it is difficult to optimally set the pulse width of this control pulse, and there is a problem that wasteful current flows and power consumption increases. Further, Patent Document 1 discloses an invention related to an address electrode drive circuit that prevents unnecessary drive current consumption due to unnecessary pulses, but this prior invention controls the output slew rate. This is not disclosed.

The present invention can make the transition time of the address signal almost constant without being affected by the direction of change of the adjacent address signal, thereby preventing erroneous lighting of the pixel and generation of electromagnetic radiation and consumption. An object of the present invention is to provide an address electrode drive circuit for a plasma display device that requires less power.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a constant current is connected to an output circuit that is connected between the first and second power supply voltage terminals and includes two series-type output MOSFETs, and a connection node is connected to one of signal lines (address electrodes) of the plasma display device. A driving circuit is provided that includes a transistor for supplying a constant current to the gate capacitance of the output MOSFET when one of the output MOSFETs is turned on in response to an input signal. In addition, a switch transistor is provided which is connected in series with the constant current transistor and in which the potential of the connection node, that is, the output terminal is applied to the control terminal. Then, when the potential of the connection node reaches a predetermined potential, the switch transistor is turned off, and the charging of the gate capacitance by the constant current of the constant current transistor is stopped, and the output The change rate (slew rate) of the signal is controlled.

  According to the above-described means, the gate capacitance of the output MOSFET is charged with a constant current, so that the gate voltage rises at a constant speed, and the load of the output driver circuit varies depending on the direction of change of the adjacent address signal. Even if it fluctuates, the transition time of the address signal can be made substantially constant. For this reason, it is possible to prevent erroneous lighting from occurring because the change in the address signal is too slow, or electromagnetic radiation from the address line due to the change in the address signal being too steep.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, it is possible to realize a semiconductor integrated circuit device suitable for an address electrode drive circuit of a plasma display device that can make the address signal transition time substantially constant without being influenced by the direction of change of the adjacent address signal.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 5 is a block diagram showing a schematic configuration of a display device using an AC type PDP as an example of a plasma display device effective by applying the address electrode driving circuit according to the present invention. 5 uses a three-electrode surface discharge type PDP, the address electrode driving circuit according to the present invention is also applicable to a counter discharge type PDP.

  The plasma display device of FIG. 5 drives a display panel 10, a digital signal processing circuit 20, a power supply circuit 30, a scanning driver 40 that scans and drives an X electrode, a sustain driver 50 that drives a Y electrode, and an address line. The address driver 60 is configured. The display panel 10 uses an AC type PDP having the same configuration as that shown in FIG.

  The digital signal processing control circuit 20 generates and supplies control pulses to the drivers 40 to 60 based on the signals such as the clock CLK, the display data DATA, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC. Based on the control pulse from the digital signal processing control circuit 20, the scanning driver 40 and the address driver 60 determine where to emit light in each pixel on the display panel 10 and where not to emit light, and generate corresponding drive voltages. Output.

  Specifically, the scanning driver 40 outputs a voltage for sequentially driving the X electrodes provided on the front substrate to the selection level, and the address driver 60 selects the address line on the rear substrate at the selection level or not according to the display data. A voltage for driving to a level is output, and a voltage of a selection level is applied to an address line corresponding to a pixel to emit light. As a result, a discharge is performed between the selected electrodes, and only the selected pixels emit light once.

  Based on the control pulse from the digital signal processing control circuit 20, the sustain driver 50 applies a continuous voltage pulse having a phase opposite to that of the X electrode to the Y electrode of the front substrate, thereby causing a sustain discharge between the X and Y electrodes. Let Due to the sustain discharge, only the pixels that have previously selectively emitted light once are discharged and light emission is displayed on the display panel 10.

FIG. 6 is a block diagram of an embodiment of an address electrode drive circuit (address driver) formed into a semiconductor integrated circuit suitable for application of the present invention.
The address driver 60 of this embodiment receives the digital display data signal input from the digital signal processing control circuit 20 and generates a high voltage output pulse to be applied to the address line so that a discharge occurs between the X and Y electrodes. Output. The address driver 60 includes a shift register 61 that converts input serial display data into parallel data, a latch unit 62 that holds the converted display data, a level conversion unit 63 that converts a signal level, and an address line. A driver unit 64 that outputs a voltage pulse to be applied, a control unit 65 that generates control signals for the shift register 61 to the driver unit 64, and the like.

  The control unit 65 sequentially fetches the serial display data DATA1 to DATAn in synchronization with the system clock signal CLK, and transfers them from the shift register 61 to the latch unit 62 in synchronization with the latch signal LAT from the digital signal processing control circuit 20. Let The address driver 60 includes a power supply terminal VDD1 to which a power supply voltage such as 5V supplied to the shift register 61, the latch unit 62, and the control unit 65 is applied, and a high power supply such as 80V supplied to the driver unit 64. A power supply terminal VDD2 to which a voltage is applied and a power supply terminal GND to which a ground potential is applied are provided.

  FIG. 7 shows a circuit diagram of an embodiment of the level shift circuit 63A and the driver 64A in the address driver 60 of FIG. The level shift circuit 63 </ b> A and the driver 64 </ b> A are unit circuits provided corresponding to the respective address output terminals, and these constitute a level conversion unit 63 and a driver unit 64.

  As shown in FIG. 7, in this embodiment, the driver 64A is connected between a first power supply voltage terminal to which a high power supply voltage VDH such as 70V is applied and a ground point as a second power supply voltage terminal. It is composed of two N-channel MOSFETs Q11 and Q12 connected in series.

  The level shift circuit 63A includes three MOSFETs Q1, Q2, Q3 and a resistor R1 connected in series between the first power supply voltage terminal and the ground point, and a series connection between the first power supply voltage terminal and the ground point. The two MOSFETs Q4 and Q5 connected to each other, and the MOSFET Q6 provided in parallel with Q4. Of these MOSFETs, Q2 to Q4 and Q6 are P-channel MOSFETs, and Q1 and Q5 are N-channel MOSFETs. The MOSFETs Q11 and Q12 of the driver 64A have a large gate width and a low gate-source breakdown voltage compared to Q2, Q6, etc. so as to have sufficiently higher driving power than the MOSFETs Q1 to Q6 of the level shift circuit 63A. It is formed by.

  In this embodiment, an input signal PIN is applied to the gate terminal of MOSFET Q5, and a signal PINB having a phase opposite to that of PIN is applied to the gate terminal of Q1. The potential of the common drain of the MOSFETs Q4 and Q6 is applied to the gate terminal of the high-side output MOSFET Q11, and the input signal NIN is applied to the gate terminal of the low-side output MOSFET Q12. The input signals PIN and NIN are signals having substantially opposite phases so that the high-level periods do not overlap each other. Q11 and Q12 are complementarily turned on and off to output address electrode drive pulses and simultaneously turned on. By controlling so as not to be in a state, a through current is prevented from flowing.

  When the input signal PINB is at a high level, the MOSFET Q1 and the resistor R1 function as a constant current source for supplying a current determined by the threshold voltage of Q1 and the resistance value of R1. The MOSFET Q3 functions as a current-voltage conversion element with the gate and drain coupled together, and the MOSFET Q4 is connected to the gate in common with the Q3 to form a current mirror circuit that passes a current I2 proportional to the drain current I1 of Q3. ing. Further, the potential of the output node of the driver 64A is applied to the gate terminal of the MOSFET Q2 provided in series with the input MOSFET Q1, and functions as a switching element that performs on / off operation by monitoring the output.

  Further, a Zener diode DZ1 is connected in the reverse direction between the gate terminal of the output MOSFET Q11 and the output node of the driver 64A so as to function as a withstand voltage protection element. This Zener diode DZ1 lowers the gate voltage of the output MOSFET Q11 by causing a reverse current to flow when the output terminal is accidentally shorted to a ground point in a state where the output is at a high level, for example. It prevents the drain current from flowing and destroying between the drain and the source. The reverse voltage of DZ1 is set to a value such as 6V, for example.

Next, the operation of the circuit of FIG. 7 when the output of the driver 64A changes from the low level to the high level will be described with reference to the timing chart of FIG.
When the output is at low level, the input signals are PIN and NIN at high level and PINB at low level. From this state, first, the input signal NIN is changed to the low level, and the low-side output MOSFET Q12 is turned off (timing t1). Subsequently, the input signal PIN is changed from the high level to the low level, and the reverse-phase signal PINB is changed from the low level to the high level, so that the input MOSFET Q5 of the level shift circuit 63A is turned off and Q1 is turned on. (Timing t2).

  At this time, since the output potential Vout is initially at a low level, the monitor switch MOSFET Q2 is in an on state, and when Q1 is turned on, a drain current I1 flows through Q1, and the current flows to Q3 through Q2. The current I2 proportional to I1 is caused to flow through Q4 by the current mirrors of Q3 and Q4. As a result, the parasitic capacitance (mainly the gate capacitances Cgd and Cgs of the high-side output MOSFET Q11) connected to the drain terminal of Q4 is charged with a constant current, and the gate voltage of Q11 rises at a constant speed. At this time, if the load capacitance of the output terminal is within the range of the driving capability of Q11, the output potential Vout also rises at a constant speed following the change of the gate voltage. The parasitic capacitance connected to the drain terminal of Q4 includes the source-drain capacitance Cds of Q5 and Q6 in addition to the gate capacitances Cgd and Cgs of Q11, but the size of Q11 is smaller than that of Q5 and Q6. Therefore, Cgd + Cgs >> Cds, and the slew rate of the gate voltage of Q11 is almost determined by the constant current I2 and the gate capacitances Cgd and Cgs of Q11.

  When the output potential Vout rises to a certain level (VDH−Vthq3−Vthq2), the monitor switch MOSFET Q2 is turned off. Here, Vthq3 and Vthq2 are the threshold voltages of the MOSFETs Q3 and Q2, respectively, and are designed to be, for example, Vthq3≈2V and Vthq2≈7V. Then, when Vout rises to 61 V, the drain current of MOSFETs Q3 and Q4 of the current mirror stops flowing, and the charging of the gate capacitance of Q11 by the current of Q4 is automatically terminated (timing t3).

  Thereby, it is possible to prevent the useless drive current I1 from flowing. Here, when an element having a relatively high threshold voltage (for example, the same voltage as Vthq2 of Q2) is used as the MOSFET Q6, it is turned off while the monitor switch MOSFET Q2 is turned on, and Q2 is turned off. Thus, it can be operated to turn on when the drain voltage of Q1 decreases. Thereby, even if Q2 is turned off and the drain current of Q4 stops flowing, the gate voltage of the output MOSFET Q11 can be kept at a high level by Q6.

  FIG. 18 shows operation waveform diagrams of the gate voltage and the output voltage of the output MOSFET when the output of the driver 64A in FIG. 7 is changed from the low level to the high level. When the input MOSFET Q1 of the level shift circuit 63A of FIG. 7 is turned on by the input signal PIB and Q5 is turned off by the input signal PI, the constant current I2 of the MOSFET Q4 of the current mirror is changed to the N-channel output MOSFET Q11. Charge the gate-source parasitic capacitance Cgs. At this time, a parasitic capacitance Cgd between the gate and the drain also exists, but the capacitance value seen from the gate side is increased by the Miller effect. Therefore, the current I2 acts as a current for charging the gate-source parasitic capacitance Cgs having a relatively small capacitance value. Then, as shown in FIG. 18, the gate-source voltage Vgs of the output MOSFET Q11 rises linearly.

  When the gate-source voltage Vgs of the MOSFET Q11 becomes larger than the threshold voltage, the MOSFET Q11 is turned on and a drain current flows to charge the load capacitor CL connected to the output terminal. The output voltage Vout is changed from the low level to the high level. At this time, an address electrode of the PDP is connected to the output terminal, and the address electrode of the PDP includes a parasitic capacitance existing between the circuit ground potential and a parasitic capacitance existing between adjacent address electrodes. The load capacity CL is as follows. The parasitic capacitance existing between the adjacent address electrodes can be regarded as not present when viewed from the output terminal when the adjacent address electrode changes to the high level, so that the load capacitance CL for the output circuit is Get smaller. On the other hand, when the adjacent address electrode remains at the low level, or when converting from the high level to the low level, the charging current is supplied to the adjacent address electrode and the load capacitance CL for the output circuit is large. Become. The load capacitance CL of the output circuit greatly changes due to such a change in the adjacent address electrode.

  In the output circuit of this embodiment, when the load capacitance CL is small, as shown in FIG. 18, the gate-source voltage Vgs of the N-channel MOSFET Q11 that increases linearly by the current I2 reaches Vgs1 that is relatively small. The drain current of the MOSFET Q11 that flows when this operation starts the charging operation to the small load capacitance CL and raises the output voltage Vout. As the output voltage Vout rises, the current I2 is consumed for charging the gate-drain parasitic capacitance Cgd of the MOSFET Q11. As a result, the gate voltage VG1 (gate-source voltage Vgs1) becomes substantially constant. As a result, the address electrode is linearly raised from the low level (L) to the high level (H) by a relatively small constant drain current corresponding to the gate voltage VG1.

  On the other hand, when the load capacitance CL is large, the gate-source parasitic capacitance Cgs is charged by the current I2 so as to increase the gate-source voltage Vgs as shown in FIG. As the charging period becomes longer in this way, the output MOSFET Q11 causes a relatively large drain current to flow by the gate voltage VG2 to which the increased gate-source voltage Vgs2 is applied, thereby charging the large load capacitance CL. Start and increase the output voltage Vout. As the output voltage Vout rises, the current I2 is consumed in the charging operation of the gate-drain parasitic capacitance Cgd of the MOSFET Q11. As a result, the gate voltage VG2 (gate-source voltage Vgs2) becomes substantially constant. As a result, the address electrode is linearly raised from the low level (L) to the high level (H) by a relatively large constant drain current corresponding to the gate voltage VG2.

  In this embodiment, as described above, when the low-side output MOSFET Q12 is in the off state and the output transitions from the low level to the high level due to the change of the high-side output MOSFET Q11 from off to on, the high-side MOSFET Q11 The charge / discharge operation of the gate parasitic capacitances Cgs and Cgd of Q11 is performed by the constant current I2 of the current mirror MOSFET Q4 only while the switch MOSFET Q2 is on. The output rising speed at this time is mainly determined by the charging speed (slew rate) of the parasitic capacitance Cgd by the constant current I2 as described above. As a result, the gate voltage VG of the high-side MOSFET Q11 is balanced by the gate-source Vgs that becomes the driver current io corresponding to the load capacitance CL and its rising speed tr. This is a section in which the gate voltage VG becomes constant in the rising process in FIG. The driver current io required at this time is io = VG2 (high level) × CL / tr. Therefore, the larger the capacitance value of the load capacitor CL and the faster (smaller) the rising speed tr, the greater the driver current io of the high-side MOSFET Q11.

  In the case of the circuit of this embodiment, when the gate of the high-side MOSFET Q11 is connected to the high voltage power supply VDH, the gate-source voltage Vgs of the high-side MOSFET Q11 becomes the maximum, and the high-side MOSFET Q11. The driver current io is also maximized. Thereafter, since the driver current io of the high-side MOSFET Q11 becomes constant at the maximum value, the rising speed tr changes when the load capacitance changes in the above equation. That is, in the conventional circuit, since the gate-source voltage Vgs is determined by the maximum voltage, the driver current io is always used at a maximum current and a constant current. It will change accordingly. On the other hand, in the circuit of the present embodiment, when the rising speed tr is determined by the slew rate and used within the maximum driver current in the equation io = VG2 (high level) × CL / tr, the load capacitance CL changes. However, it is possible to control so that the rising speed tr does not change.

  In this way, the rise of the output voltage Vout can be made substantially the same regardless of the magnitude (variation) of the load capacity. In other words, when the load capacitance CL is small, a small output current io corresponding thereto is formed, and when the load capacitance CL is large, a large output current io corresponding thereto is formed, and the output voltage Vout is as described above. The rise is almost the same. However, in order to realize the operation as described above, it is necessary that the high-side MOSFET Q11 has sufficient drivability to realize the rising characteristics. In other words, the high-side MOSFET Q11 is designed to have such drivability that the output current io capable of realizing the required rising characteristics can be obtained even with the voltage Vgs1 and the voltage Vgs2 smaller than the power supply voltage VG2. good.

  According to the driving circuit of this embodiment, the rise time can be made constant even when the output load capacitance changes, so that the address can be set regardless of the direction of change in the output of the circuit that drives the adjacent address electrode. The signal transition time can be kept constant. As a result, it is possible to suppress the occurrence of erroneous lighting of the pixel due to the long transition time, or conversely the generation of electromagnetic radiation due to the short transition time.

  FIG. 17 is a diagram for explaining the characteristics of the address driver of FIG. The characteristic diagram of FIG. 17 is a simulation result (marked by ■) showing the relationship between the load capacity when the output rises and the transition time of the output. For comparison, the characteristics (marked by ◆) of the address driver without slew rate control are shown.

  As shown in FIG. 17, in the driver without slew rate control, the transition time difference Δt2 is about 30 ns (nanoseconds) between the monochrome display mode in which white and black are alternately displayed every several lines and the staggered display mode in which the display is inverted between adjacent dots. Also reach nearby. On the other hand, in the driver of this embodiment, when the load capacitance is 60 pF or less, the transition time becomes almost constant, and the transition time difference Δt1 is about 2 ns between the monochrome display mode and the staggered display mode, and the transition time difference is greatly increased. It can be seen that it is improved.

  Further, according to the driving circuit of the present embodiment, the output potential Vout is monitored and the MOSFET Q2 is turned off. As shown in FIG. 8, when the Vout reaches a predetermined potential, the Q2 Can be turned off, so that a useless current I1 does not continue to flow through Q1.

  Here, a method of turning on / off the MOSFET Q2 in series with the MOSFET Q1 functioning as a constant current source by using a control pulse generated separately, instead of the output voltage, as in the previous application is also conceivable. However, in the method using the control pulse, it is difficult to optimally set the pulse width of the control pulse. If the pulse width is narrow, Q11 is turned off before the output potential Vout reaches a predetermined potential. Therefore, it must be designed wider.

  However, with such a design, as shown in FIG. 9, the current I1 continues to flow through Q1 even after Vout reaches a predetermined potential, and the portion indicated by hatching becomes a useless current, resulting in an increase in power consumption. The problem that occurs. Further, in order to optimally set the pulse width of the control pulse CP, it is necessary to provide a trimming circuit or the like in consideration of manufacturing variations. This increases the circuit scale and increases the chip area, which is not a preferable measure.

  Furthermore, since an N-channel MOSFET is used for the high-side output MOSFET Q11, the occupied area can be reduced. As is well known, since the N-channel MOSFET has higher carrier mobility than the P-channel MOSFET, the N-channel MOSFET has a higher operating speed if the size is the same, and the N-channel MOSFET if the speed is the same. Can reduce the size. Therefore, by using an N-channel MOSFET for the high-side output MOSFET Q11, the occupied area can be reduced.

  FIG. 10 shows a modification of the first embodiment. In this modification, a PN junction diode D1 connected in the same reverse direction in parallel with the Zener diode DZ1 is provided. The PN junction diode D1 is a protection element for the Zener diode DZ1. Since the Zener diode DZ1 may be destroyed when a large amount of forward current flows, in the embodiment of FIG. 7, immediately after the MOSFET Q5 is turned on, from the output terminal to the gate terminal of the output MOSFET Q11 through the Zener diode DZ1. There is a possibility that current flows and the Zener diode DZ1 itself is destroyed.

  Here, in order to prevent the output MOSFETs Q11 and Q12 from being turned on at the same time and causing a through current from flowing from the power supply voltage VDH to the ground point, Q5 is turned on before turning on the MOSFET Q12 and the gate voltage of Q11 is turned on. It is necessary to lower Q11 and turn off Q11. Therefore, it cannot be avoided that a forward current flows through the Zener diode DZ1.

  In the present modification, when a forward current flows through the Zener diode DZ1, the current also flows through the PN junction diode D1 connected in parallel with the Zener diode DZ1, so that the destruction of the Zener diode DZ1 can be avoided. However, when a Zener diode DZ1 that can sufficiently flow a forward current is used, the PN junction diode D1 can be omitted.

  FIG. 11 shows a second embodiment of the level shift circuit of the address driver that outputs the address electrode drive signal and the driver. In this embodiment, a circuit for driving the gate terminal of the low-side output MOSFET Q12 of the driver 64A is provided, and the falling of the output voltage Vout is also controlled at the slew rate. Specifically, two MOSFETs Q7, Q8 and a resistor R2 connected in series between the output node and the ground point, and 2 connected in series between the output node and the ground point in parallel therewith. The MOSFETs Q9 and Q10 and a protective Zener diode DZ2 connected in the reverse direction between the gate and source of the output MOSFET Q12. Unlike the Zener diode DZ1, since no forward current flows through the Zener diode DZ2, a protective element corresponding to the diode D1 is unnecessary.

  Of these MOSFETs, Q8 and Q9 are P-channel MOSFETs, Q7 and Q10 are N-channel MOSFETs, and MOSFETs Q8 to Q10 are constituted by elements having a smaller size than the output MOSFET Q12. Further, as the MOSFETs Q8 and Q9, elements having a lower gate-source breakdown voltage than the MOSFETs Q2 and Q6 constituting the circuit for driving the high-side output MOSFET Q11 can be used.

  In this embodiment, an input signal NIN is applied to the gate terminal of the MOSFET Q7 so that the high level period does not overlap with the input signal PIN, and a signal NINB having a phase opposite to that of NIN is applied to the gate terminal of Q10. Yes. The potential of the common drain of MOSFETs Q9 and Q10 is applied to the gate terminal of the low-side output MOSFET Q12. When the input signal NIN is at a high level, the MOSFET Q7 and the resistor R2 function as a constant current source for flowing a current determined by the threshold voltage of Q7 and the resistance value of R2. The MOSFET Q8 functions as a current-voltage conversion element with the gate and drain coupled together, and the MOSFET Q9 is connected to the gate in common with the Q8 to form a current mirror circuit that passes a current I4 proportional to the drain current I3 of Q7. ing.

Next, the operation of the circuit of FIG. 11 when the output of the driver 64A changes from the high level to the low level will be described using the timing chart of FIG.
When the output is at a high level, the input signals NIN and PIN are at a low level and NINB and PINB are at a high level. From this state, first, the input signal PIN is changed to the high level, the MOSFET Q5 is turned on, the charge charged in the gate capacitance of the high-side output MOSFET Q11 is extracted, and the Q11 is turned off ( Timing t11). Subsequently, the input signal NIN is changed from the low level to the high level, and the reverse-phase signal NINB is changed from the high level to the low level, so that the MOSFET Q10 is turned off and Q7 is turned on (timing t12).

  At this time, the output potential Vout is initially at a high level, and when Q7 is turned on, the drain current I3 of Q7 flows to Q8, and the current I4 proportional to I3 is supplied to Q9 by the current mirror of Q8 and Q9. Washed away. As a result, the parasitic capacitance (mainly the gate capacitances Cgd and Cgs of the low-side output MOSFET Q12) connected to the drain terminal of Q9 is charged with a constant current, and after the output terminal starts falling, the parasitic capacitance is constant according to the load capacitance. The gate voltage is maintained, and the load capacitance is discharged by the output current corresponding to the gate voltage. At this time, if the load capacitance of the output terminal is within the drive capability range of Q12, the output potential Vout falls at a constant speed.

  When the output potential Vout drops to the potential (about 4V) that is the sum of the threshold voltages of the MOSFETs Q7 and Q8, Q8 is turned off, the drain currents I3 and I4 of Q7 and Q9 do not flow, and the gate of Q12 by Q9 The charging of the capacity is automatically terminated (timing t13). Thereby, it is possible to prevent the useless drive current I3 from flowing. Since Q10 is off after Q9 is turned off, the gate voltage of the low-side output MOSFET Q12 is at a voltage (4V) higher than its threshold voltage (about 2V). The output voltage Vout decreases until the gate voltage of Q12 divided by Q9 and Q10 becomes a potential (3V) lower than Vth of Q12.

  At this time, since the output node is connected to the drain terminal of the MOSFET Q5 that is turned on via the diode D1, the output voltage Vout is higher than the ground voltage by the forward voltage Vf at the end of the fall. Decrease to voltage.

  According to the drive circuit of this embodiment, the fall time can be made constant even when the output load capacitance changes, so that the output circuit of the circuit that drives the adjacent address electrode can be driven regardless of the direction of change. The transition time of the address signal can be kept constant. As a result, it is possible to prevent the transition time from becoming longer and causing erroneous pixel lighting, or conversely the transition time from being shortened to generate electromagnetic radiation. Further, when the output potential Vout is lowered to a certain potential, the MOSFET Q8 in series with the constant current MOSFET Q7 can be automatically turned off, so that the unnecessary current I3 does not continue to flow through the constant current MOSFET Q7. Can be.

  Here, as in the previous application, the source terminals of the MOSFETs Q8 and Q9 constituting the current mirror circuit are connected to a predetermined power supply voltage without an output node, and the input signal NIN of the MOSFET Q7 functioning as a constant current source is connected. A method of turning on and off with a predetermined pulse width Pw as shown in FIG. 13 is also conceivable. However, in such a system using control pulses, it is difficult to optimally set the pulse width of the input signal NIN, and the current I3 continues to flow through Q7 even after Vout reaches a predetermined potential. End up. For this reason, the portion shown by hatching in FIG. 13 becomes a wasteful current, resulting in a problem of increased power consumption. However, this embodiment does not have such a problem.

  Further, by connecting the source terminals of the MOSFETs Q8 and Q9 to the output node as in the present embodiment, the operating current of the low-side slew rate control circuit consisting of Q7 to Q10 is originally supplied to the ground point by the output MOSFET Q12. Since the current that is passed as an unnecessary current can be applied, there is an advantage that the power consumption can be further reduced.

  In the first embodiment of FIG. 7, the low-side MOSFET Q12 is controlled only by the input signal NIN without controlling the slew rate in order to prevent electromagnetic radiation from the address line in general. This is because it is more important when the electrode driving signal rises than when it falls. As in the first embodiment, it is possible to obtain a considerable effect only by controlling the slew rate of only the high-side MOSFET Q11.

  FIG. 14 shows a third embodiment. In this embodiment, a P-channel MOSFET is used as the high-side output MOSFET Q11 of the driver 64A, and the position where the monitor switch MOSFET Q2 is provided is changed.

  Specifically, a MOSFET Q3 is connected in series with the MOSFET Q1 to which the input signal PINB is applied to the gate terminal, a MOSFET Q4 is connected in series to the MOSFET Q5 to which the input signal PIN is applied to the gate terminal, and Q3 and Q4 Have a gate and a drain cross-coupled to each other to form a latch circuit. The gate terminal of the MOSFET Q6 that supplies a current for charging the gate capacitance of the high-side output MOSFET Q11 is connected to the drain terminal of the MOSFET Q4.

  In series with this MOSFET Q6, a monitoring switch MOSFET Q2, a MOSFET Q21 that functions as a constant current source by applying an input signal PIN2 to its gate terminal, and a resistor R1 are connected. Further, between the connection node of Q6 and Q2 and the ground point, a MOSFET Q22 and a resistor R2 are connected which are applied with an input signal PIN3 at their gate terminals and function as a constant current source. Q22 is allowed to continuously pass a minute current I2 such as 1 μA while the output voltage Vout is maintained at a high level.

  FIG. 15 shows the input signal NIN applied to the gate terminal of the low-side output MOSFET Q12 and the MOSFETs Q1, Q5 of the level shift circuit when the output of the driver changes from low level to high level in the circuit of FIG. , Q21, Q22, the timing of the signals PIN, PIN2, PIN3, PINB input to the gate terminals, and how the output changes. When such an input signal is applied, the charge of the gate capacitance of the high-side output MOSFET Q11 is discharged by a constant current I1 such as 300 μA flowing through the MOSFET Q21, and after the rise of the output terminal starts, the load capacitance becomes The corresponding constant gate voltage is maintained, and the load capacity is charged by the output current corresponding to the gate voltage, so that the output potential Vout rises at a constant speed.

  When the output potential Vout rises to a certain level, the monitoring MOSFET Q2 is turned off. Then, the drain current I1 of the MOSFET Q21 does not flow, and the discharge of the gate capacitance of Q11 by the current of Q21 is automatically terminated. As a result, useless drive current can be prevented from flowing.

  Further, while the output voltage Vout is maintained at the high level, a small current I2 such as 1 μA can be continuously supplied by Q22, so that even if the monitoring MOSFET Q2 is turned off, the output MOSFET can be consumed with a relatively small current consumption. The on state can be maintained by keeping the gate voltage of Q11 at a low level. Since the current I2 of Q22 is very small compared to the current I1 of Q21, application of this embodiment eliminates the need to control with the control pulse as in the previous application, and wasteful drive current I1 in the MOSFET Q21. Can be prevented and the total power consumption can be reduced.

  That is, in the circuit of FIG. 14, the monitor MOSFET Q2 is not provided, and the input signal PIN2 of the MOSFET Q21 is used as a control pulse as shown in FIG. 16, so that the gate voltage of the output MOSFET Q11 corresponds to the load capacitance. It is possible to keep the voltage constant and charge the load capacitance with an output current corresponding to the voltage, thereby raising the output potential Vout at a predetermined slew rate. However, in such a case, a useless drive current I1 flows in Q21 as shown by hatching in FIG. 16, but by applying this embodiment, useless drive current I1 in Q21 as shown in FIG. Can be prevented from flowing.

  As described above, by applying the above embodiment, the address signal can be changed at an optimum slew rate. Accordingly, it is possible to prevent display image quality degradation and generation of electromagnetic radiation due to erroneous lighting of pixels in the plasma display device. Further, since it is not necessary to use a control pulse, there is an advantage that it is possible to prevent unnecessary drive current from flowing and reduce power consumption.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the level shift circuit and the driver are all constituted by MOS transistors, but the constant current transistors Q1, Q7, Q21, etc. may be constituted by bipolar transistors.

  In the embodiment of FIG. 14, only the circuit for controlling the slew rate of the gate voltage of the high-side output MOSFET Q11 is shown, but the low-side output MOSFET Q12 as shown in FIG. An embodiment in which a circuit for controlling the slew rate of the gate voltage is also conceivable.

  In the above description, the case where the invention made by the present inventor is mainly applied to the address electrode drive circuit of the surface discharge type PDP which is the field of use behind the present invention has been described, but the present invention is not limited thereto. In addition, the present invention can be used for an address electrode drive circuit of a counter discharge type PDP and other drive circuits for driving a display signal line having a relatively large load and a high applied voltage.

It is a perspective view which shows schematic structure of the display panel of surface discharge type PDP. FIG. 3 is an equivalent circuit diagram showing a state of a load connected to an address driver that drives an address line of a PDP. It is a wave form diagram which shows the change of the output of the conventional address driver which drives the address line of PDP. It is a graph which shows the relationship between the load capacity and transition time of the conventional address driver which drives the address line of PDP. 1 is a block diagram showing a schematic configuration of a plasma display device effective by applying a semiconductor integrated circuit for driving an address electrode of a PDP according to the present invention. 1 is a block diagram showing a schematic configuration of an embodiment of an address electrode driving circuit (address driver) which is preferably formed into a semiconductor integrated circuit by applying the present invention. FIG. 1 is a circuit diagram showing a first embodiment of a level shift circuit and a driver constituting an address driver. FIG. FIG. 8 is a timing chart showing changes in signals, output voltages, and drive currents input to the level shift circuit of FIG. 7 when the output changes from low level to high level. 6 is a timing chart showing changes in an input signal, an output voltage, and a drive current when the level shift circuit is controlled by a control pulse. It is a circuit diagram which shows the modification of a 1st Example. FIG. 6 is a circuit diagram showing a second embodiment of a level shift circuit and a driver of an address driver that outputs an address electrode drive signal. 12 is a timing chart showing changes in a signal, an output voltage, and a drive current input to the level shift circuit of FIG. 11 when an output changes from a low level to a high level in the second embodiment. 10 is a timing chart showing changes in an input signal, an output voltage, and a drive current when the level shift circuit is controlled by a control pulse in the second embodiment. FIG. 10 is a circuit diagram showing a third embodiment of a level shift circuit and a driver of an address driver that outputs an address electrode drive signal. FIG. 15 is a timing chart showing changes in a signal, an output voltage, and a drive current that are input to the level shift circuit of FIG. 14 when the output changes from a low level to a high level in the third embodiment. 12 is a timing chart showing changes in an input signal, an output voltage, and a drive current when the level shift circuit is controlled by a control pulse in the third embodiment. It is a characteristic view which shows the load capacity-transition time characteristic of the address driver of an Example. FIG. 6 is an operation waveform diagram of a gate voltage and an output voltage of an output MOSFET when an output is changed from a low level to a high level in the address driver of the example.

Explanation of symbols

10 Display panel (PDP)
20 Digital Signal Processing Circuit 30 Power Supply Circuit 40 Scan Driver 50 Sustain Driver 60 Address Driver (Semiconductor Integrated Circuit Device for Driving)
61 Shift register 62 Latch part 63 Level conversion part 64 Driver part 63A Level shift circuit 64A Driver (address electrode drive circuit)

Claims (22)

A plurality of output circuits which are extended side by side and output to each of a plurality of signal lines serving as capacitive loads;
A first power supply voltage terminal to which a first power supply voltage is supplied;
A second power supply voltage terminal to which a second power supply voltage lower than the first power supply voltage is supplied,
Each of the plurality of output circuits is
A first output MOSFET connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and having a connection node coupled to an output node to which one of the plurality of signal lines is connected; A two-output MOSFET;
A first drive circuit that includes a constant current transistor, and causes a constant current to flow through the gate capacitance of the first output MOSFET when the first output MOSFET is switched from an off state to an on state according to an input signal;
The constant current transistor is connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the potential of the output node of the first output MOSFET and the second output MOSFET is applied to the control terminal. A switch transistor adapted to be
The semiconductor integrated circuit device, wherein when the potential of the output node reaches a predetermined potential, the switch transistor is turned off and charging / discharging of the gate capacitance by the constant current is stopped. In claim 1,
The first driving circuit includes a current mirror circuit including a first transistor connected in series with the switch transistor and a second transistor having a control terminal commonly connected to the first transistor, and the second transistor includes A semiconductor integrated circuit device, wherein the constant current is supplied to a gate capacitance of the first output MOSFET. In claim 2,
The first drive circuit includes a third transistor connected in parallel with the second transistor between the first power supply voltage terminal and the gate terminal of the first output MOSFET, and increases the potential of the output node. After the switch transistor is turned off by the step, the third transistor is turned on to pass a current through the gate capacitance of the first output MOSFET. In claim 3,
A semiconductor device comprising a fourth transistor connected in series with the third transistor between the first power supply voltage terminal and the output node and switched complementarily to the constant current transistor. Integrated circuit device. In claim 1,
2. The semiconductor integrated circuit device according to claim 1, wherein each of the first output MOSFET and the second output MOSFET is an N-channel type MOSFET. In claim 5,
A semiconductor integrated circuit device comprising: a protective diode connected in a reverse direction between the gate terminal of the first output MOSFET and the output node. In claim 6,
2. The semiconductor integrated circuit device according to claim 1, wherein the protection diode is a Zener diode, and includes a PN junction diode connected in parallel with the Zener diode. In claim 1,
A second drive circuit including a second constant current transistor, and configured to switch the second output MOSFET in a complementary manner with the first output MOSFET in response to an input signal;
2. The semiconductor integrated circuit device according to claim 1, wherein the second drive circuit causes a constant current to flow through the gate capacitance of the second output MOSFET when the second output MOSFET is turned from the off state to the on state. In claim 8,
The semiconductor integrated circuit device, wherein the second drive circuit is connected between the output node and the second power supply voltage terminal. In claim 8,
The second drive circuit includes:
A current mirror circuit including a fifth transistor connected in series to the second constant current transistor and a sixth transistor having a control terminal connected in common to the fifth transistor, and the second output by the sixth transistor; A semiconductor integrated circuit device, wherein the constant current is passed through a gate capacitance of a MOSFET. In claim 10,
A seventh transistor connected in series with the sixth transistor between the output node and the second power supply voltage terminal and switched complementarily to the second constant current transistor is provided. A semiconductor integrated circuit device. A first output MOSFET and a second output MOSFET which are connected in series between the first power supply voltage terminal and the second power supply voltage terminal and whose connection node is connected to the output terminal;
A first drive circuit that includes a constant current transistor, and causes a constant current to flow through the gate capacitance of the first output MOSFET when the first output MOSFET is switched from an off state to an on state according to an input signal;
The constant current transistor is connected in series between the first power supply voltage terminal and the second power supply voltage terminal, and the potential of the connection node of the first output MOSFET and the second output MOSFET is applied to the control terminal. A switch transistor adapted to be
A semiconductor integrated circuit device having a plurality of output circuits for turning off the switch transistor when the potential of the connection node reaches a predetermined potential and stopping charging and discharging of the gate capacitance by the constant current;
And a display panel to which each of the plurality of address electrodes is connected to each output terminal of the plurality of output circuits. In claim 12,
The first driving circuit includes a current mirror circuit including a first transistor connected in series with the switch transistor and a second transistor having a control terminal commonly connected to the first transistor, and the second transistor includes A plasma display device, wherein the constant current is passed through a gate capacitance of the first output MOSFET. In claim 13,
The first drive circuit includes a third transistor connected in parallel with the second transistor between the first power supply voltage terminal and the gate terminal of the first output MOSFET, and increases the potential of the output node. After the switch transistor is turned off by the above, the third transistor is turned on, and a current flows through the gate capacitance of the first output MOSFET. In claim 14,
A plasma comprising a fourth transistor connected in series with the third transistor between the first power supply voltage terminal and the output node and switched in a complementary manner with the constant current transistor. Display device. In claim 12,
The plasma display apparatus, wherein the first output MOSFET and the second output MOSFET are N-channel MOSFETs. In claim 16,
A plasma display device comprising: a protective diode connected in a reverse direction between the gate terminal of the first output MOSFET and the output node. In claim 17,
The plasma display device, wherein the protection diode is a Zener diode, and includes a PN junction diode connected in parallel with the Zener diode. In claim 12,
A second drive circuit including a second constant current transistor, and configured to switch the second output MOSFET in a complementary manner with the first output MOSFET according to an input signal;
The plasma display apparatus, wherein the second drive circuit causes a constant current to flow through the gate capacitance of the second output MOSFET when the second output MOSFET is turned from an off state to an on state. In claim 19,
The plasma display apparatus, wherein the second drive circuit is connected between the output node and the second power supply voltage terminal. In claim 19,
The second drive circuit includes:
A current mirror circuit including a fifth transistor connected in series to the second constant current transistor and a sixth transistor having a control terminal connected in common to the fifth transistor, and the second output by the sixth transistor; A plasma display device characterized by causing the constant current to flow through a gate capacitance of a MOSFET. In claim 20,
A seventh transistor connected in series with the sixth transistor between the output node and the second power supply voltage terminal and switched complementarily to the second constant current transistor is provided. Plasma display device.

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