JP2006328531A5 - - Google Patents

Description

Method for forming oxide dielectric layer and capacitor layer forming material having oxide dielectric layer obtained by the method

  The present invention relates to a capacitor layer forming material, a method for manufacturing the capacitor layer forming material, and a printed wiring board including a built-in capacitor layer obtained by using the capacitor layer forming material.

  The capacitor layer forming material referred to in the present invention has a configuration in which a dielectric layer is provided between a first conductive layer used for forming an upper electrode and a second conductive layer used for forming a lower electrode. The first conductive layer and the second conductive layer are processed so as to form a capacitor circuit by etching or the like, and constitute an electronic material such as a printed wiring board as disclosed in Patent Document 1. Generally used as a material.

The dielectric layer has an insulating property and accumulates a certain amount of charge. Various methods are employed as a method for forming such a dielectric layer, but a chemical vapor phase reaction method (CVD method), a sputtering deposition method, or a sol-gel method is generally used. For example, Patent Document 2, as using chemical vapor reaction method, and depositing a HiAkirashitsujo SrTiO ₃ based thin at a temperature lower than 400 ° C. on the base, the amorphous form SrTiO ₃ based thin film Is produced by laser annealing or rapid thermal annealing to obtain a SrTiO ₃ -based thin film. This method aims to obtain a SrTiO ₃ -based thin film having a high dielectric constant.

  Next, in Patent Document 3, a thin film capacitor in which a lower electrode, a dielectric having a high dielectric constant, and an upper electrode are stacked on an arbitrary layer on a substrate as a sputtering deposition method is used. The dielectric is a polycrystal composed of crystal grains and crystal grain boundaries, and contains metal ions that can have a plurality of valences as impurities, and the impurity is present at a higher concentration near the crystal grain boundaries than inside the crystal grains. A thin film capacitor characterized by containing it is disclosed, and it is disclosed that Mn ions are suitable as metal ions capable of taking a plurality of valences thereof. A thin film capacitor obtained by this method has long-term reliability and a long time to breakdown.

Furthermore, Patent Document 4 discloses an oxide that forms a dielectric oxide thin film using a metal alkoxide as a raw material on a substrate after subjecting the surface of the substrate to a hydroxylation treatment using a sol-gel method. A method for manufacturing a dielectric thin film is disclosed. Here, the oxide dielectric that can be formed as a thin film is a metal oxide having dielectric properties, such as LiNbO ₃ , Li ₂ B ₄ O ₇ , PbZrTiO ₃ , BaTiO ₃ , SrTiO ₃ , PbLaZrTiO ₃ , LiTaO _3. , ZnO, Ta ₂ O ₅ or the like. The oxide dielectric thin film obtained by this method is an oxide dielectric thin film excellent in orientation and crystallinity.

  The formation of the dielectric layer using the sol-gel method does not require the use of a vacuum process as compared with the formation of the dielectric layer using the chemical vapor reaction method (CVD method) or the sputtering deposition method, and the dielectric layer is wide. There is an advantage that it can be easily formed on a substrate having an area. In addition, since it is easy to make the components of the dielectric layer have a theoretical ratio and an extremely thin dielectric layer can be obtained, it is expected to be a material for forming a large-capacity capacitor layer.

Further, in the method of manufacturing a PZT thin film disclosed in Patent Document 5, after a buffer layer mainly composed of PbTiO ₃ (PT) is formed on a substrate, the buffer layer mainly composed of PbTiO ₃ is not subjected to organic pyrolysis. A thin film material mainly composed of PZT is applied before being processed, and both layers are subjected to organic thermal decomposition, followed by a crystallization heat treatment at 430 to 500 ° C. Yes. When the buffer layer is crystallized at a low temperature, the effect of reducing the energy for crystallization of PZT at the time of PZT film formation by taking advantage of the characteristics that PT and PZT are close in crystal structure and lattice constant. It is what I expected. Certainly, the production of the dielectric layer by the sol-gel method is generally required to be crystallized by high-temperature baking, and thus various problems are likely to occur, and is effective as a low-temperature baking method.

JP 2002-539634 Gazette Japanese Patent Laid-Open No. 06-140385 JP 2001-358303 A JP 07-294862 A Japanese Patent No. 3427795

  However, the dielectric layer using the sol-gel method is short-circuited between the upper electrode and the lower electrode when the capacitor is formed due to the thinness of the dielectric layer and the presence of gaps between the oxide particles. As a result, there is a problem in that the leakage current may increase, resulting in a low production yield. In particular, when an attempt is made to increase the electrode area in order to increase the capacitance of the capacitor, the occurrence of defective products that cause a short-circuit phenomenon becomes significant.

In general, capacitor circuits have been able to reduce the power consumption of electronic and electrical equipment by storing surplus electricity, etc., so having as much electrical capacity as possible is the basic quality. Desired. The capacitance (C) of the capacitor is calculated from the equation C = εε ₀ (A / d) (ε ₀ is the dielectric constant of vacuum). In particular, due to the recent trend of reducing the thickness of electronic and electrical devices, the same demands have been made on printed wiring boards. The surface area of capacitor electrodes (A ) May be required to increase the capacity of the capacitor circuit.

  When a general capacitor circuit is formed, a dielectric layer is formed on a substrate such as a metal foil for forming the lower electrode by a sol-gel method, and then a sputtering method or the like is formed on the dielectric layer. A copper layer serving as an upper electrode is formed and patterned by wet etching to form a predetermined capacitor circuit. However, the etchant used when performing wet etching penetrates into the dielectric layer and reaches the metal foil as the substrate. When such a phenomenon occurs, the substrate is eluted and even the dielectric layer is removed. When such penetration of the etching solution into the dielectric layer occurs, the dielectric loss increases and adversely affects electrical characteristics such as an increase in apparent capacitance density. Also, elution of the substrate, damage to the dielectric layer, etc. cause a short circuit between the upper electrode and the lower electrode (substrate), and the production yield of the capacitor circuit decreases. In particular, when manufacturing a capacitor foil for embedded passive components, it is preferable to use an inexpensive base metal foil as a constituent material of the lower electrode so as not to increase the product cost. It is desirable that the etching is possible and the characteristic does not deteriorate.

  Furthermore, if a PZT thin film as a dielectric layer is obtained by a low-temperature firing method as disclosed in Patent Document 5, a buffer layer that promotes crystallization of PZT is essential, which complicates the manufacturing process and reduces the manufacturing cost and This is not preferable because management of manufacturing conditions becomes complicated and the total manufacturing cost increases. Moreover, since the dielectric layer obtained by the technique disclosed in Patent Document 5 has a buffer layer, the total thickness as the dielectric layer is also thick, and the use of PT with poor quality as the dielectric is used. There is a drawback that it is difficult to obtain a high-capacity dielectric layer.

  In view of the above, in the market, a dielectric layer is formed by using a sol-gel method with excellent manufacturing cost merit, and the dielectric layer is not easily damaged by an etching solution and has a high electric capacity. Has been desired. At the same time, the dielectric layer forming method has been required to have a high production yield.

  Therefore, the inventors of the present invention have tried a technique such as refining the oxide crystal grains of the dielectric layer formed by a keen sol-gel method to an unprecedented level, or rather obtaining coarse grains with few crystal grain boundaries. In the meantime, the inventors came up with the following invention.

Method for forming oxide dielectric layer according to the present invention: The method for forming an oxide dielectric layer according to the present invention is a method for forming an oxide dielectric layer by a sol-gel method, and includes the following (a) to (c): The process is provided.

(A) A solution preparation step for preparing a sol-gel solution for producing a desired oxide dielectric layer.
(B) A series of coating the sol-gel solution on the surface of a metal substrate, drying at 120 ° C. to 250 ° C. in an oxygen-containing atmosphere, and performing thermal decomposition at 270 ° C. to 390 ° C. in an oxygen-containing atmosphere. When the process is a single unit process and this single unit process is repeated a plurality of times, an inert gas replacement at 550 ° C. to 1000 ° C. or a pre-baking process in vacuum is optionally provided between the single unit process and the single unit process. Coating process to adjust the film thickness.
(C) A firing step of finally performing a firing process at 550 ° C. to 1000 ° C. to obtain a dielectric layer .

  And it is preferable that the atmosphere of the baking process of said (c) is inert gas substitution or in a vacuum.

In addition , the sol-gel solution used in the method for forming an oxide dielectric layer according to the present invention includes a (Ba _1-x Sr _x ) TiO ₃ (0 ≦ x ≦ 1) film or a BiZrO ₃ film as the oxide dielectric layer. It is preferable to form.

  Furthermore, the sol-gel solution used in the method for forming an oxide dielectric layer according to the present invention is a total of 0.01 mol of one or more selected from manganese, silicon, nickel, aluminum, lanthanum, niobium, magnesium and tin. It is preferable to form an oxide dielectric layer containing from 0.5 to 5.00 mol%.

  The dielectric layer obtained by the method for forming an oxide dielectric layer according to the present invention preferably has a thickness of 20 nm to 2 μm.

  The metal substrate used in the method for forming an oxide dielectric layer according to the present invention includes a nickel foil having a thickness of 1 μm to 100 μm, a nickel alloy foil, a composite foil having a nickel layer as a surface layer, and a nickel alloy layer as a surface layer. It is preferably one of the composite foils.

  And as for the said metal base material, it is preferable that the nickel alloy layer of the composite foil provided with nickel alloy foil or a nickel alloy layer in a surface layer consists of nickel-phosphorus alloys.

Capacitor layer forming material according to the present invention: A capacitor layer forming material according to the present invention includes a dielectric layer between a first conductive layer used for forming an upper electrode and a second conductive layer used for forming a lower electrode. In the above, it is preferable that the dielectric layer is obtained by the oxide dielectric layer forming method according to any one of the above-described manufacturing methods.

Printed wiring board according to the present invention: By using the capacitor layer forming material according to the present invention, a printed wiring board having a high-quality built-in capacitor layer can be obtained.

  The method for forming an oxide dielectric layer by the sol-gel method according to the present invention is capable of forming a high-quality oxide dielectric layer with good yield. The dielectric layer obtained by the method for forming an oxide dielectric layer according to the present invention has characteristics of reducing leakage current and being hardly damaged by an etching solution, and is particularly suitable for forming a capacitor circuit by an etching method. . And the capacitor layer forming material which formed the dielectric layer using the formation method of the oxide dielectric layer by the sol-gel method which concerns on this invention is suitable for formation of the capacitor layer of a printed wiring board, and is high electrical capacity and low Capacitor circuits exhibiting dielectric loss can be manufactured.

<Method for Forming Oxide Dielectric Layer According to Present Invention>
The method for forming an oxide dielectric layer according to the present invention is a method for forming an oxide dielectric layer by a sol-gel method, and includes the following steps (a) to (c). Hereinafter, it demonstrates for every process.

  First, in order to easily understand the features of the present invention, the formation of an oxide dielectric layer by a sol-gel method that has been conventionally performed by the present inventors will be briefly described. The formation of an oxide dielectric layer for use as a conventional dielectric layer usually goes through steps (I) to (III).

  (I) A solution preparation step for preparing a sol-gel solution for producing a desired oxide dielectric layer. (II) The sol-gel solution is applied to the substrate surface, dried in an oxygen-containing atmosphere at 120 ° C. to 250 ° C. for 30 seconds to 10 minutes, and 450 ° C. to 550 ° C. in an oxygen-containing atmosphere. A coating process for adjusting the film thickness by repeating the process of thermal decomposition under conditions of 5 to 30 minutes. Then, the step (II) is repeated a plurality of times to adjust to a desired film thickness. (III) Next, as a final firing, a firing step in which a dielectric layer is formed by firing in an inert gas replacement atmosphere or vacuum at 550 ° C. to 800 ° C. for 5 minutes to 60 minutes. Through the above steps, an oxide dielectric layer has been formed.

  As can be seen from the above, the oxide dielectric layer using the conventional sol-gel method is formed only once in the final stage. In contrast, in the present invention, the oxide dielectric layer is manufactured by providing one or more preliminary firings in the course of one unit process.

Step (a): This step is a solution preparation step for preparing a sol-gel solution for producing a desired oxide dielectric layer. There is no special restriction regarding this step, and a commercially available preparation agent may be used or it may be blended by itself. As a result, it is only necessary to obtain either a (Ba _1-x Sr _x ) TiO ₃ (0 ≦ x ≦ 1) film or a BiZrO ₃ film as the desired oxide dielectric layer. Here, in the (Ba _1-x Sr _x ) TiO ₃ (0 ≦ x ≦ 1) film, when x = 0, it means the BaTiO ₃ composition, and when x = 1, it means the SrTiO ₃ composition. It will be a thing. Then, as the intermediate _composition, there are _{(Ba 0.7} Sr 0.3) TiO ₃ or the like.

  Further, considering the mechanism of the generation of the leakage current of the dielectric layer, the leakage current in the case of the oxide dielectric layer formed by the sol-gel method flows through the crystal grain boundary and lattice defects of the oxide dielectric layer. It has turned out to be highly possible. That is, the finer the oxide dielectric layer structure, the greater the grain boundaries, and the higher the internal defect density in the crystal, the greater the leakage current. Although the solution of this point will be described later, depending on the composition of the oxide dielectric layer, it is possible to reduce the leakage current and improve the quality as the dielectric layer.

  That is, it is preferable to include one or more selected from manganese, silicon, nickel, aluminum, lanthanum, niobium, magnesium and tin in the crystal grain boundaries and grains of the oxide dielectric layer. These components are considered to be present as oxides inside the dielectric layer, and are defined as segregating at the crystal grain boundaries of the oxide dielectric layer obtained by the sol-gel method. It is used to shut off. Therefore, these components are referred to as “leak prevention components”. Among these leak preventing components, it is preferable to use manganese. This is because this manganese can be easily segregated at the crystal grain boundary of the oxide dielectric layer obtained by the sol-gel method. At this time, it is preferable that the amount of the leakage preventing component contained in the oxide dielectric layer is 0.01 mol% to 5.00 mol%. Here, when two or more kinds of components are used, the total component amount is the leak prevention component amount. When the amount of the leakage preventing component is less than 0.01 mol%, the segregation of the leakage preventing component to the crystal grain boundary of the oxide dielectric layer obtained by the sol-gel method is insufficient, and a good leakage current is obtained. The reduction effect cannot be obtained. On the other hand, when the amount of the leak preventing component exceeds 5.00 mol%, segregation of the leak preventing component to the crystal grain boundary of the oxide dielectric layer obtained by the sol-gel method becomes excessive, and the dielectric layer becomes brittle. The toughness is lost, and defects such as dielectric layer breakdown are likely to occur due to an etchant shower or the like when processing the upper electrode shape or the like by an etching method. Further, when the amount of the leakage preventing component is excessive, the growth of the oxide crystal structure in the production method described below tends to be suppressed. Therefore, by adopting a composition containing the leakage preventing component in the above range, the capacitance as a capacitor is significantly increased, the leakage current is further reduced, and the life is increased. More preferably, the amount of the leakage preventing component contained in the oxide dielectric layer is 0.25 mol% to 1.50 mol%. This is to ensure the quality of the oxide dielectric layer more reliably. The oxide dielectric layer is a dielectric film having a perovskite structure, and does not contain manganese oxide unless explicitly stated that the oxide dielectric layer contains a manganese oxide component or the like.

  In addition, it is assumed that a leak preventing component such as manganese is substituted in the oxide crystal lattice. In general, an oxide dielectric layer causes oxygen vacancies by crystallization under a low oxygen partial pressure. For this reason, the valence of titanium is reduced from tetravalent to trivalent, and the insulating property is reduced by electron hopping between titanium atoms having different valences. However, when an appropriate amount of leak prevention component is substituted and dissolved in the oxide crystal, it can take a divalent or trivalent valence configuration to compensate for oxygen vacancies, and the titanium is not reduced and insulated. The effect which improves property can be expected.

  The oxide dielectric layer formed by the method according to the present invention preferably has a thickness of 20 nm to 2 μm. The thinner the dielectric layer, the higher the electric capacity. Therefore, the thinner the dielectric layer, the better. However, when the thickness of the dielectric layer is less than 20 nm, even if the above-described manganese, silicon, or the like is added to the dielectric layer, the effect of reducing the leakage current is lost, and dielectric breakdown occurs at an early stage, thus extending the life. I can't. On the other hand, since the insulation reliability increases when the dielectric layer is thick, the dielectric layer may be thick depending on the balance with the electric capacity. However, when the dielectric layer is formed by the sol-gel method, about 2 μm is practical considering industrial productivity, and about 1 μm seems to be the upper limit considering the market demand. In view of the size of the crystal structure of the oxide dielectric layer described later, the thickness is more preferably 50 nm or more.

(B) Step: In this step, the sol-gel solution is applied to the surface of the metal substrate (referred to as “coating” in the following description), and in an oxygen-containing atmosphere at 120 to 250 ° C. A series of steps is performed by drying (referred to as “drying” in the following description) and performing thermal decomposition at 270 ° C. to 390 ° C. in an oxygen-containing atmosphere (referred to as “thermal decomposition” in the following description). As a unit process, when repeating this one unit process a plurality of times, at least one 550 ° C. to 1000 ° C. inert gas replacement or pre-baking treatment in vacuum is provided between one unit process and one unit process. This is a coating process for adjusting the film thickness.

  That is, in this step, a series of steps of coating → drying → pyrolysis is referred to as one unit step. In the conventional method, this single unit process is simply repeated a plurality of times and finally fired. On the other hand, in the present invention, at least one preliminary firing step is provided in the middle of repeating one unit step a plurality of times. Therefore, for example, if one unit process is repeated six times, if one pre-baking step is provided, one unit step (first time) → pre-firing step → one unit step (second time) → 1 unit For example, the process of the process (third time) → one unit process (fourth time) → one unit process (fifth time) → one unit process (sixth time) is adopted. If two firing steps are provided, one unit process (first time) → preliminary firing step → one unit process (second time) → one unit process (third time) → preliminary firing step → one unit process (4 1st process (5th time) → 1 unit process (6th time), etc. Furthermore, if a firing process is provided between all 1 unit processes, 1 unit process (first time) → preliminary firing process → 1 unit process (second time) → preliminary firing process → 1 unit process (third time) → preliminary A process of firing step → one unit step (fourth) → pre-baking step → one unit step (fifth) → pre-baking step → one unit step (sixth) is adopted.

  The crystal state of the oxide dielectric layer obtained by the conventional sol-gel method has fine crystal grains, and a large number of voids can be confirmed in the crystal grains. This is considered to be because the organic component contained in the sol-gel liquid is evaporated during firing. When wet etching is performed in such a state, the etching solution easily penetrates into the dielectric layer. Therefore, when the upper electrode is patterned by etching, the substrate (the constituent material of the lower electrode) is eroded by the etching solution that has passed through the dielectric layer, and the dielectric layer at the erosion site is lost and disappears. On the other hand, by adopting this step (b), the structure of the oxide dielectric layer becomes dense with high film density and few structural defects in the crystal grains. Therefore, even if the upper electrode is patterned by the wet etching method as described above, the penetration of the etchant into the dielectric layer is difficult to occur. Therefore, the dielectric film is exposed on the portion where the dielectric layer is to be exposed after the upper electrode is patterned by etching. Is reliably observed, and etching elution of the substrate (the constituent material of the lower electrode) can be prevented. As a result, a leakage current is small and a capacitor circuit having a high-capacity dielectric layer can be obtained. The most effective prevention of the penetration of the etching solution into the dielectric layer here is that the pre-baking step is preferably performed as early as possible, considering the case where six unit processes are repeated. Therefore, it is ideal to carry out by one unit process (first time) → pre-firing step → one unit process (second time). Considering the case where this pre-baking step is performed only once, the meaning of the pre-baking step is closer to the final baking, such as 1 unit step (fifth) → pre-baking step → one unit step (sixth step), and final baking. The effect of providing a pre-baking step is weakened.

  The crystal structure of the oxide dielectric layer is preferably as large as possible. This is because if the grain size can be made as large as possible, the abundance ratio of the crystal grain boundary that becomes a leak path can be reduced. According to the study by the present inventors, if limited to the crystal grain size, the coarsened crystal structure of the dielectric layer grows in the thickness direction and the planar direction, and the grain size (major axis) is 50 nm to 300 nm. When the oxide crystal structure is included, it has been found that the leakage current is reduced, the dielectric layer has a high electric capacity, and the life can be extended to withstand long-term use. The grain size as used herein refers to the size of a crystal grain obtained by measuring the major axis of a coarse grain directly observed from an observation image obtained by observing a cross section of a dielectric layer with a focused ion beam at a magnification of 1,000,000 with a transmission electron microscope. Although it cannot be said to be a grain size in a strict sense, there is no problem as an index for clarifying the presence of coarse crystal grains. When the observed particle size (major axis) is less than 50 nm, the leakage current is reduced and the capacitance is increased as compared with the oxide dielectric layer obtained by the conventional sol-gel method. Not noticeable. On the other hand, in order to obtain crystal grains with a grain size (major axis) of the oxide crystal structure constituting the dielectric layer exceeding 300 nm, very special manufacturing conditions must be applied, and a substantial industrial scale. Production is impossible.

  Here, coating in one unit process will be described. There is no particular limitation on the coating means for applying the sol-gel solution to the surface of the metal substrate. However, it is preferable to use a spin coater as long as the uniformity of the film thickness and the characteristics of the sol-gel solution are taken into consideration.

  And as a metal base material said here, it is preferable to use either a nickel layer, a nickel alloy layer, the composite foil provided with a nickel layer in a surface layer, or the composite foil provided with a nickel alloy layer in a surface layer. These can be preferably used. (1) It can be obtained as a metal foil, and a dielectric layer can be formed on the surface by the sol-gel method in the state of the foil. (2) Excellent oxidation resistance and anti-softening properties against severe thermal history applied when forming a dielectric layer by a sol-gel method. (3) By changing the nickel alloy composition, the adhesion with the dielectric layer can be controlled at a certain level. (4) A fine capacitor circuit can be formed when the lower electrode shape is formed by an etching method.

  The nickel layer or nickel alloy layer here is mainly intended to use a metal foil. Therefore, the nickel layer is preferably formed of a pure nickel foil having a so-called purity of 99.0% (others, inevitable impurities) or more, and most preferably 99.9% or more. The higher the purity of the nickel foil, the better the adhesion stability between the nickel foil and the dielectric layer. The nickel alloy layer is a layer formed using, for example, a nickel-phosphorus alloy. The phosphorus content of the nickel-phosphorus alloy mentioned here is preferably 0.1 wt% to 11 wt%. The phosphorus component of the nickel-phosphorus alloy layer diffuses into the dielectric layer and can adhere to the dielectric layer if it is subjected to high temperature loads in the manufacturing process of the capacitor layer forming material and the normal printed wiring board manufacturing process. It is considered that the dielectric constant is deteriorated and the dielectric constant is also changed. However, a nickel-phosphorus alloy layer having an appropriate phosphorus content improves the electrical characteristics as a capacitor. When the phosphorus content is less than 0.1 wt%, it becomes the same as when pure nickel is used, and the significance of alloying is lost. On the other hand, when the phosphorus content exceeds 11 wt%, phosphorus segregates at the interface of the dielectric layer, the adhesiveness with the dielectric layer is deteriorated, and it becomes easy to peel off. Therefore, the phosphorus content is preferably in the range of 0.1 wt% to 11 wt%. In order to ensure more stable adhesion with the dielectric layer, a stable quality capacitor circuit can be obtained even if there is a certain variation in the process if the phosphorus content is in the range of 0.2 wt% to 3 wt%. Formation is possible. If the optimum range is pointed out, the phosphorus content is 0.25 wt% to 1 wt% to ensure the best adhesion with the dielectric layer and at the same time to ensure a good dielectric constant. The phosphorus content in the present invention is a value converted as [P component weight] / [Ni component weight] × 100 (wt%).

   In addition to the nickel foil and the nickel alloy foil, a composite foil provided with a nickel layer as a surface layer and a composite foil provided with a nickel alloy layer as a surface layer can also be used for the metal substrate in the present invention. That is, it is described as a concept including a composite foil provided with these nickel or nickel alloy layers in the outermost layer of the metal foil. For example, a composite foil provided with a nickel layer or a nickel alloy layer on the surface of a copper foil can be used as a material constituting the metal substrate. Further, this nickel layer or nickel alloy layer may be provided on one side or both sides of the foil.

  As long as such physical properties are provided, there is almost no deterioration in strength even after a high-temperature processing process of 300 ° C. to 400 ° C. used in a printed wiring board manufacturing process using a fluororesin substrate, a liquid crystal polymer or the like as a substrate material. As a result, even when this metal foil or composite foil is used as a metal substrate and a dielectric layer is formed on the surface thereof, the quality of the metal substrate is hardly deteriorated. In addition, it is preferable that the crystal structure of the nickel foil and the nickel alloy foil referred to in the present invention has a crystal grain as fine as possible with improved strength. More specifically, rolled nickel foil is preferable in terms of tensile strength, and in the case of electrolytic nickel foil, it is refined to a level of an average crystal grain size of 0.5 μm or less, and has physical properties with high mechanical strength. Is preferred.

  The total thickness of the metal substrate is preferably 1 μm to 100 μm. If the thickness is less than 1 μm, the reliability as an electrode when a capacitor circuit is formed is remarkably lacking, and it is extremely difficult to form a dielectric layer on the surface. On the other hand, there is almost no practical requirement for a thickness exceeding 100 μm. Further, when the thickness of the second conductive layer is 10 μm or less, handling becomes difficult. Therefore, it is preferable that the metal foil constituting the second conductive layer is a metal foil with a carrier foil bonded to the carrier foil via a bonding interface. The carrier foil may be removed at a subsequent stage after processing into the capacitor layer forming material referred to in the present invention. In the case of a composite foil having a nickel layer as a surface layer or a composite foil having a nickel alloy layer as a surface layer, the nickel layer or nickel alloy layer has a total thickness of 1 μm to 100 μm of both composite foils. Assuming that there is, it is preferably 0.1 μm to 3 μm. When the thickness of the nickel layer or nickel alloy layer is less than 0.1 μm, it is possible to obtain oxidation resistance against the severe thermal history applied when forming the dielectric layer by the sol-gel method. Absent. On the other hand, when the thickness of the nickel layer or the nickel alloy layer exceeds 3 μm, there is no significant difference from the case of using a normal nickel foil or nickel alloy foil in terms of cost.

  With respect to each method for producing the metal base material described above, there is no particular limitation, and it is possible to adopt all methods that can be normally considered. Illustratively, a nickel foil or a nickel alloy foil can be produced by an electrolytic method or a rolling method. There are no particular limitations on these production methods. In particular, the rolling method adjusts the components of the ingot by a metallurgical process and processes it into a foil shape with a rolling roll while performing an appropriate annealing operation, which is advantageous for producing a nickel alloy foil, It is sufficient to adopt a conventional method. Furthermore, in the case of a composite foil having a nickel layer as a surface layer or a composite foil having a nickel alloy layer as a surface layer, the following electrolytic method, sputtering vapor deposition method, chemical vapor reaction method is applied to the surface of a metal foil such as a copper foil. A nickel layer or a nickel alloy layer can be formed by, for example.

For example, in the case of the electrolytic method, the deposited metal structure varies depending on the electrolytic solution, electrolysis conditions, etc., and as a result, the physical strength is also affected. However, when forming a nickel foil or a nickel layer, a solution known as a nickel plating solution can be widely used. For example, (i) nickel sulfate is used, nickel concentration is 5 to 30 g / l, liquid temperature is 20 to 50 ° C., pH is ^{2 to} 4, current density is 0.3 to 10 A / dm ² , and (ii) nickel sulfate is used. Conditions of concentration 5-30 g / l, potassium pyrophosphate 50-500 g / l, liquid temperature 20-50 ° C., pH 8-11, current density 0.3-10 A / dm ² , (iii) nickel concentration using nickel sulfate 10 to 70 g / l, boric acid 20 to 60 g / l, liquid temperature 20 to 50 ° C., pH ^{2 to} 4, current density 1 to 50 A / dm ² , and other general watt bath conditions.

And when manufacturing nickel- phosphorus alloy foil or a nickel- phosphorus alloy layer by electrolysis, a phosphoric acid type solution is used as electrolyte solution. In this case, (i) nickel sulfate concentration 120 g / l to 180 g / l, nickel chloride concentration 35 g / l to 55 g / l, H ₃ PO ₄ concentration 3 g / l to 5 g / l, H ₃ PO ₃ concentration 2 g / l to 4 g / l, liquid temperature 70 ° C. to 95 ° C., pH 0.5 to 1.5, current density 5 A / dm ^{2 to} 50 A / dm ² , (ii) nickel sulfate concentration 180 g / l to 280 g / l, chloride Nickel concentration 30 g / l to 50 g / l, H ₃ BO ₃ concentration 16 g / l to 25 g / l, H ₃ PO ₃ concentration 1 g / l to 5 g / l, liquid temperature 45 ° C. to 65 ° C., current density 5 A / dm ² The condition of ˜50 A / dm ² is employed. Further, it is possible to form a nickel-phosphorus alloy layer by an electroless method using a commercially available electroless plating solution, but industrial productivity is not satisfied in terms of film forming speed.

  Next, drying in one unit process will be described. When the application of the sol-gel solution is completed, it is dried at 120 ° C. to 250 ° C. in an oxygen-containing atmosphere. At this time, when the drying temperature is less than 120 ° C., drying within an industrially required time becomes insufficient, and the surface of the dielectric layer after subsequent thermal decomposition often becomes rough. On the other hand, if the drying temperature exceeds 250 ° C., the dry state tends to be non-uniform, and as a result, the subsequent thermal decomposition reaction becomes non-uniform, and the local quality variation of the dielectric layer is likely to occur. And it is preferable to employ | adopt the range for 30 seconds-10 minutes for the time in this drying. Even when 250 ° C., which is the upper limit of the above temperature range, is adopted, if the drying time is less than 30 seconds, a sufficiently dry state cannot be obtained. Moreover, even if the lower limit of 120 ° C. in the above temperature range is adopted, if the drying time exceeds 10 minutes, the subsequent thermal decomposition reaction is likely to be uneven, and the local quality variation of the dielectric layer is likely to occur. . When performing this drying and thermal decomposition described later, it is performed in an oxygen-containing atmosphere. That is, the decomposition of the organic matter is not promoted when performed in a reducing atmosphere.

  In the production method according to the present invention, another great effect can be obtained by employing low temperature conditions of 120 ° C. to 250 ° C. for drying and 270 ° C. to 390 ° C. for thermal decomposition. FIG. 5 shows a transmission electron microscope observation image. Here, a different phase 5 (a layer having a different contrast at the interface between the lower electrode 4 and the dielectric layer 1 in FIG. 5) is formed at the interface between the lower electrode 4 and the dielectric layer 1. ) Is confirmed. This heterogeneous phase tends to occur when the drying temperature and the pyrolysis temperature are increased, and when this heterogeneous phase occurs, the adhesion between the dielectric layer and the lower electrode tends to be impaired and the dielectric properties tend to deteriorate. It is speculated that this heterogeneous phase is nickel oxide, other composite metal oxides, etc., but details are unknown. On the other hand, when the conditions of the low temperature drying and the low temperature pyrolysis are adopted for drying, an interface having no different phases can be stably formed as in the transmission electron microscope image of FIG. Stable adhesion with the electrode 4 and good dielectric properties can be obtained.

  Further, the thermal decomposition of one unit process will be described. When the drying is completed, thermal decomposition is performed at a temperature of 270 ° C. to 390 ° C. in an oxygen-containing atmosphere. Here, the employed pyrolysis temperature is very characteristic. A temperature range of 450 ° C. to 550 ° C. has been adopted as the conventional pyrolysis temperature. On the other hand, in the manufacturing method according to the present invention, a thermal decomposition temperature in a low temperature range of 270 ° C. to 390 ° C. is employed in order to prevent excessive oxidation of the metal substrate. Here, when the thermal decomposition temperature is less than 270 ° C., no matter how long the heating is continued, good thermal decomposition is difficult to occur, productivity is lacking, and good capacitor characteristics cannot be obtained. On the other hand, the dielectric layer is formed on the surface of the metal substrate. When heating at a temperature exceeding 390 ° C., the surface of the metal substrate is significantly oxidized at the interface between the dielectric layer and the metal substrate. To be seen. However, in consideration of process variations and quality safety in mass production, it is preferable to set an upper limit of about 370 ° C., which is a lower temperature. The heating time is determined by the decomposition temperature employed and the properties of the sol-gel solution, but it is desirable to employ a heating temperature range of 5 minutes to 30 minutes. Assuming that the above temperature range is adopted, sufficient heat decomposition cannot be performed with heating for less than 5 minutes. Further, when the heating time exceeds 30 minutes, the oxidation of the surface of the metal substrate proceeds even in the above temperature range.

  And the preliminary baking process provided between the 1 unit process mentioned above and 1 unit process performs the 550 degreeC-1000 degreeC inert gas substitution, or the baking process in a vacuum. Since this condition is almost the same as the step (c) described below, the critical significance of the numerical value will be described in the description. In addition, it is preferable to employ | adopt the time for 2 to 60 minutes as the baking time in this preliminary baking process. This firing time will also be described later.

(C) Process: This process is a baking process which finally carries out the inert gas substitution of 550 degreeC-1000 degreeC, or performs the baking process in a vacuum, and makes it a dielectric layer. This firing step is a so-called main firing step, and after this firing, a final dielectric layer is obtained. In this firing step, heating is performed in an inert gas replacement atmosphere or vacuum to prevent oxidative degradation of the metal substrate. The heating temperature at this time is 550 ° C to 1000 ° C. Heating below this temperature condition makes it difficult to sinter within the calcination time required industrially, and provides a dielectric layer that has excellent adhesion to a metal substrate and has an appropriate fineness and a crystal structure with an appropriate grain size. It is not possible. If an excessive heating temperature exceeding this temperature condition is adopted, deterioration of the dielectric layer and deterioration of the physical strength of the substrate proceed, and it becomes impossible to achieve high electric capacity and long life as capacitor characteristics. The firing time at this firing temperature is preferably 5 to 60 minutes. Even when the upper limit temperature (1000 ° C.) of the firing temperature is adopted, firing cannot be performed sufficiently in a firing time of less than 5 minutes, and a good dielectric layer having a large electric capacity cannot be obtained. On the other hand, if the firing time is less than 60 minutes, even if the lower limit temperature (550 ° C.) of the firing temperature is adopted, a good dielectric layer having a large electric capacity cannot be obtained, and the dielectric layer is easily embrittled.

  In the dielectric layer manufactured by the above method, the dielectric layer is formed directly on the surface of the metal substrate, and there is no buffer layer between the metal substrate and the dielectric layer. Therefore, there is an advantage that the total manufacturing cost does not increase without complicating the manufacturing process, and since there is no buffer layer, the total thickness as the dielectric layer is thin and a high-capacity dielectric layer can be easily obtained.

<Capacitor layer forming material according to the present invention>
The capacitor layer forming material according to the present invention is a capacitor layer forming material comprising a dielectric layer between a first conductive layer used for forming an upper electrode and a second conductive layer used for forming a lower electrode. It is preferable that the oxide dielectric layer is obtained by any of the methods described above. That is, an oxide dielectric layer is formed on the surface of the metal base material by using the above-described dielectric layer forming method, using a metal foil or the like as the second conductive layer used for forming the lower electrode. Then, a first conductive layer is formed on the obtained dielectric layer to form a capacitor layer forming material. Here, as a method of forming the first conductive layer on the dielectric layer, it is possible to employ a method of bonding using a metal foil, a method of forming a conductive layer by a plating method, a method such as sputtering deposition. .

<Printed wiring board using capacitor layer forming material according to the present invention>
By using the capacitor layer forming material according to the present invention, a printed wiring board having a high quality built-in capacitor layer can be obtained.

  The capacitor layer forming material according to the present invention can be suitably used for forming a built-in capacitor layer of a multilayer printed wiring board. The first conductive layer and the second conductive layer of the capacitor layer forming material are formed into a capacitor circuit shape by an etching method and used as a constituent material of a multilayer printed wiring board. Further, by using the above-described nickel or nickel alloy for the second conductive layer, it is possible to form a lower electrode having excellent adhesion with the dielectric layer, and the lower electrode is a material having excellent heat resistance. Even when hot pressing in the range of 300 ° C. to 400 ° C. is performed a plurality of times, oxidation deterioration does not occur and physical property changes hardly occur. There is no particular limitation on the method of manufacturing a printed wiring board having a built-in capacitor circuit using the capacitor layer forming material according to the present invention, and any method can be adopted.

  Here, an example of a manufacturing method when manufacturing a printed wiring board is shown. For example, the first conductive layer 12 on one side of the capacitor layer forming material 11 shown in FIG. 7A is leveled, and a dry film is laminated on both sides to form the etching resist layer 21. Then, an etching pattern for forming the upper electrode is exposed and developed on the etching resist layer on the surface of the first conductive layer. Then, the upper electrode 15 is formed by etching with a copper chloride etchant as shown in FIG.

  Then, with the etching resist remaining on the circuit surface after the formation of the upper electrode 15, the exposed dielectric layer in the region other than the circuit portion is removed. As a method for removing the dielectric layer at this time, it is preferable to use wet blasting. When this wet blasting process is completed, the etching resist is peeled off, washed with water and dried to obtain the state shown in FIG.

  In the capacitor layer forming material after the removal of the dielectric layer, it is necessary to remove the exposed dielectric layer and bury a deeper gap between the upper electrodes. Therefore, as shown in FIG. 8D, in order to provide an insulating layer and a conductive layer on the surface of the capacitor layer forming material, a resin layer provided with a semi-cured resin layer 17 having a thickness of about 80 μm on one side of the copper foil 16. The attached copper foil 18 is superposed and hot press-molded under a heating condition of 180 ° C. × 60 minutes, and the copper foil layer 16 and the insulating layer 17 ′ are laminated on the outer layer to obtain the state shown in FIG. . Then, the outer second conductive layer 14 shown in FIG. 8 (e) is etched to form the lower electrode 19, which is in the state shown in FIG. 8 (f).

  Next, the copper foil layer 16 located on the outer layer is drilled by a laser processing method, and copper plating is performed to provide a copper plating layer 24, a via hole 23 is formed, and etching is performed to perform the process shown in FIG. State. And as shown in FIG.9 (h), the copper foil 18 with a resin layer is piled up, it hot-press-molds on the heating conditions of 180 degreeC x 60 minutes, and the copper foil layer 16 and the insulating layer 17 are used as an outer layer. Are brought into a state shown in FIG.

  Then, the outer copper foil layer 16 shown in FIG. 10 (i) is drilled by a laser processing method, and copper plating is performed to provide a copper plating layer 24, a via hole 23 is formed, and etching is performed. The state (j) is assumed. As for the etching method and via hole formation at this time, a conventional method can be adopted. As described above, the printed wiring board 10 including the built-in capacitor circuit can be manufactured. In addition, although it specifies clearly here, manufacture of the printed wiring board which concerns on this invention is not limited to the said manufacturing method, and can manufacture all the manufacturing methods. Examples will be described below.

  In this example, the oxide dielectric layer is formed on the surface of a nickel foil which is a metal substrate (lower electrode forming layer), and an upper electrode forming layer is further provided on the surface of the dielectric layer to produce a capacitor layer forming material. did. And the capacitor circuit was formed by the etching method using this capacitor layer forming material, and various dielectric properties were evaluated.

<Manufacture of metal substrate (lower electrode forming layer)>
Here, a nickel foil having a thickness of 50 μm manufactured by a rolling method was used. In addition, the thickness of the nickel foil manufactured by the rolling method is shown as a gauge thickness. This nickel foil constitutes the second conductive layer when it becomes the capacitor layer forming material.

<Formation of dielectric layer>
A dielectric layer was formed on the surface of the nickel foil using a sol-gel method. The nickel foil before forming the dielectric layer by the sol-gel method was heated at 250 ° C. for 15 minutes as a pretreatment, and irradiated with ultraviolet rays for 1 minute to clean the surface.

(A) Process: In this solution preparation process, the sol-gel solution used for a sol-gel method was prepared. Here, it was prepared so that an oxide dielectric layer having a composition of Ba _0.7 Sr _0.3 TiO ₃ could be obtained using a trade name BST thin film forming agent 7 wt% BST manufactured by Mitsubishi Materials Corporation.

(B) Step: In this step, the sol-gel solution is applied to the surface of the metal substrate, dried in an oxygen-containing atmosphere at 150 ° C. for 2 minutes, and then in an oxygen-containing atmosphere at 330 ° C. × 15. A series of steps in which thermal decomposition was performed under the conditions of 1 minute was defined as one unit step. Then, in repeating this one unit process six times, the film thickness adjustment is performed by providing at least one pre-baking treatment with inert gas replacement at 650 ° C. for 15 minutes at least once between one unit process and one unit process. went. And Sample 1-1 to Sample 1-8 were obtained as a plurality of samples.

For Sample 1-1 and Sample 1-2, one pre-baking step is provided between the first one unit step and the second one unit step.
For sample 1-3, one pre-baking step is provided between the second one unit step and the third one unit step.
For sample 1-4, one pre-baking step is provided between the third unit unit and the fourth unit unit.
For Sample 1-5, one pre-baking step is provided between the fourth one unit step and the fifth one unit step.
For Sample 1-6, a total of two pre-baking steps between the first unit step and the second one unit step and between the third unit step and the fourth one unit step Is provided.
And for sample 1-7 and sample 1-8, a total of five pre-baking steps are provided between each step between the first unit step of the first time and the first unit step of the sixth time. .

(C) Process: And each sample of the said sample 1-1, the sample 1-3, the sample 1-4, the sample 1-5, the sample 1-6, and the sample 1-7 is 650 degreeC x 15 minutes of inert gas Baking treatment was performed in a substitution atmosphere (nitrogen substitution atmosphere), and a dielectric layer was formed on the surface of the nickel foil as the metal substrate. Samples 1-2 and 1-8 were fired in an inert gas replacement atmosphere (nitrogen replacement atmosphere) at 700 ° C. for 30 minutes to form a dielectric layer on the surface of the nickel foil as the metal substrate. did.

<Formation of upper electrode>
As described above, a copper layer having a thickness of 2 μm is formed as a first conductive layer on the dielectric layer formed on each sample by sputtering vapor deposition, and the first conductive layer and the second conductive layer are formed on both sides of the dielectric layer. And 8 types of capacitor layer forming materials.

<Formation of capacitor circuit>
An etching resist layer was provided on the surface of the first conductive layer of each capacitor forming material, and an etching pattern for forming the upper electrode shape was exposed and developed. Thereafter, the first conductive layer is etched with a copper chloride based copper etchant, and the etching resist is peeled off, whereby 100 capacitor circuits each having an upper electrode area of 1 mm × 1 mm size and an upper electrode area of 4 mm × 4 mm size are obtained. Formed.

<Evaluation of dielectric properties>
Electrode yield: After the capacitor circuit is formed, a predetermined voltage is applied to 100 capacitor circuits of each sample, interlayer withstand voltage measurement is performed, and no short-circuit phenomenon is observed between the upper electrode and the lower electrode. I saw the ratio. As a result, the production yield of 1 mm × 1 mm size capacitor circuits was 80% to 100%, and the production yield of 4 mm × 4 mm size capacitor circuits was 10% to 83%.

Electric capacity density: The initial average capacity density was as high as 1330 nF / cm ^{2 to} 1920 nF / cm ² .

Dielectric loss: When the dielectric loss of the capacitor circuit was measured, it was in the range of 2.2% to 16%.

Residual Dielectric Layer After Etching: It was examined whether or not the dielectric layer remained in the inter-circuit gap after the capacitor circuit was formed. In order to examine the presence or absence of this residue, it is performed by looking between the circuits with a metal microscope. If the dielectric layer remains, an iridescent interference color can be observed. As a result, it was confirmed that the dielectric layer remained in any of Samples 1-1 to 1-8.

Crystallization level of dielectric layer: The surface of the dielectric layer is measured by X-ray diffraction (CuKα), and the half width of the peak of the (101) plane indexed by the tetragonal structure is measured. did. As a result, 0.268 deg. ~ 0.299deg. It became the value of. From this result, the half width of the peak of the (101) plane is 0.3 deg. If it is as follows, it is considered that crystallization without any practical problem has been achieved. In Example 2 below, the same process is adopted until the formation of the dielectric layer. Therefore, it is clearly stated that the half-value width of the peak on the (101) plane is the same.

Observation of Dielectric Layer with Transmission Electron Microscope: The cross sections of the capacitor layer forming materials of Sample 1-1 and Sample 1-6 were processed with a focused ion beam and observed with a transmission electron microscope. This observation image is shown in FIG.1 and FIG.2. As is clear from FIG. 1 which is a cross section of the sample 1-1, the first layer in which pre-baking was performed after completing one unit process in the dielectric layer 1 between the upper electrode 3 and the lower electrode 4. 2 is observed clearly distinct from the other layers. 2 which is a cross section of the sample 1-6 is observed as being divided into three layers (first layer 2, second layer 2 ', and third layer 2 ").

  As described above, in the cross-sectional image of the sample 1-1 (FIG. 1), the first layer 2 is observed clearly separated from the other layers. On the other hand, in the cross-sectional image of sample 1-6 (FIG. 2), although it appears to be divided into three layers, the crystal particles appear to be growing in columnar form as compared with sample 1-1. The division of the three layers is not clear. However, the present inventors consider that it is better that defects such as voids exist in the dielectric layer as much as possible from various viewpoints such as effectively preventing leakage current. In this way, it is considered that the layered portion is a portion containing many defects such as voids, and it is better that the layer cannot be confirmed as clearly as possible. Here, when the cross section of the sample 1-7 shown in FIG. 3 is seen, even when compared with the cross-sectional image of the sample 1-6 (FIG. 2), further columnar growth of crystal grains is observed, and there is a problem with each preliminary firing. There is almost no continuity. That is, judging from the adjustment conditions of these samples, the continuity between layers is uniform in the film thickness direction by setting the final crystallization temperature high for samples 1-1 and 1-6 and setting the time longer. It is considered that a simple dielectric layer can be formed.

  Each characteristic described above is listed in Table 1 so that it can be compared with Comparative Example 1 described later.

  In this embodiment, the oxide dielectric layer is formed on the surface of a nickel foil that is a metal substrate (lower electrode forming layer), and an upper electrode is formed on the surface of the dielectric layer by a mask method to form a capacitor circuit. Various dielectric properties were evaluated.

<Manufacture of metal substrate (lower electrode forming layer)>
Here, the same 50 μm-thick nickel foil produced by the rolling method as in Example 1 was used. This nickel foil constitutes the lower electrode when the capacitor layer circuit is formed.

<Formation of dielectric layer>
A dielectric layer was formed on the surface of the nickel foil using the same sol-gel method and sol-gel solution as in Example 1. Therefore, the same dielectric layer as in the case of Example 1 should be obtained, and a duplicate description here is omitted. Samples 2-1 to 2-8 were obtained as a plurality of samples.

For sample 2-1 and sample 2-2, one pre-baking step is provided between the first one unit step and the second one unit step.
For the sample 2-3, one pre-baking step is provided between the second one unit step and the third one unit step.
For the sample 2-4, one pre-baking step is provided between the third unit step and the fourth one unit step.
For sample 2-5, one pre-baking step is provided between the fourth unit unit and the fifth unit unit.
For sample 2-6, a total of two pre-baking steps between the first unit process of the first time and the first unit process of the second time and between the first unit process of the third time and the first unit process of the fourth time Is provided.
And for sample 2-7 and sample 2-8, a total of five pre-baking steps are provided between each step between the first unit step and the first one unit step. .

(C) Process: And each sample of the said sample 2-1, sample 2-3, sample 2-4, sample 2-5, sample 2-6, sample 2-7 is 650 degreeC x 15 minutes of inert gas Baking treatment was performed in a substitution atmosphere (nitrogen substitution atmosphere), and a dielectric layer was formed on the surface of the nickel foil as the metal substrate. Samples 2-2 and 2-8 were baked in an inert gas replacement atmosphere (nitrogen replacement atmosphere) at 700 ° C. for 30 minutes to form a dielectric layer on the surface of the nickel foil as the metal substrate. did.

<Formation of capacitor circuit>
As described above, a metal mask for vapor deposition having an upper electrode shape opened at the position where the upper electrode is formed is disposed on the dielectric layer formed on each sample, and a copper layer having a thickness of 2 μm is formed by sputtering vapor deposition. A capacitor circuit was formed as an upper electrode. At this time, 100 capacitor circuits each having an upper electrode area of 1 mm × 1 mm and an upper electrode area of 4 mm × 4 mm were formed.

<Evaluation of dielectric properties>
Electrode yield: After the capacitor circuit is formed, a predetermined voltage is applied to 100 capacitor circuits of each sample, interlayer withstand voltage measurement is performed, and no short-circuit phenomenon is observed between the upper electrode and the lower electrode. I saw the ratio. As a result, the production yield of 1 mm × 1 mm size capacitor circuits was 60% to 100%, and the production yield of 4 mm × 4 mm size capacitor circuits was 10% to 70%.

Electric capacity density: The initial average capacity density was as high as 1040 nF / cm ^{2 to} 1710 nF / cm ² .

Dielectric loss: When the dielectric loss of the capacitor circuit was measured, it was in the range of 2.8% to 7.5%.

Dielectric layer crystallization level: Since it is the same as in Example 1, the description is omitted.

  Among the characteristics described above, the electrical characteristics were measured with a 4261A LCR meter (1 kHz, 1 V) manufactured by Hued Packard and listed in Table 2 so that they can be compared with Comparative Example 2 described later. did.

Comparative example

[Comparative Example 1]
In Comparative Example 1, the same manufacturing flow as in Example 1 is employed, but the steps (b) and (c) are different. Therefore, only different processes will be described.

(B) Step: In this step, the sol-gel solution is applied to the surface of a nickel foil as a metal substrate, dried in an oxygen-containing atmosphere at 150 ° C. for 2 minutes, and then in an oxygen-containing atmosphere. A series of steps for performing thermal decomposition under conditions of 330 ° C. × 15 minutes was defined as one unit step. And this 1 unit process was repeated 6 times and the film thickness adjustment was performed. Three samples were obtained.

Step (c): One of the above samples is fired in an inert gas replacement atmosphere (nitrogen replacement atmosphere) at 650 ° C. for 15 minutes to form a dielectric layer on the surface of the nickel foil that is the metal substrate. It was set as Sample 3-1. In addition, one of the above samples is subjected to a firing treatment in an inert gas replacement atmosphere (nitrogen replacement atmosphere) at 650 ° C. for 30 minutes, and a dielectric layer is formed on the surface of a nickel foil as a metal base, did. Further, one of the above samples is subjected to a baking treatment in an inert gas replacement atmosphere (nitrogen replacement atmosphere) at 700 ° C. for 60 minutes, and a dielectric layer is formed on the surface of a nickel foil as a metal base, did. Thereafter, similarly to Example 1, a capacitor circuit was manufactured using an etching method.

<Evaluation of dielectric properties>
Electrode yield: After the capacitor circuit was formed in the same manner as in Example 1, a predetermined voltage was applied to 100 capacitor circuits of each sample to perform interlayer withstand voltage measurement, and between the upper electrode and the lower electrode. We saw the rate at which the short-circuit phenomenon was not seen. As a result, the production yield of 1 mm × 1 mm size capacitor circuits was 25% to 80%, and the production yield of 4 mm × 4 mm size capacitor circuits was 0%.

Electric capacity density: The initial average capacity density was as high as 1715 nF / cm ^{2 to} 2090 nF / cm ² .

Dielectric loss: When the dielectric loss of the capacitor circuit was measured, it exceeded 20%.

Dielectric layer remaining after etching: As a result of evaluation in the same manner as in Example 1, no dielectric layer remained in any of Samples 3-1 to 3-3.

Crystallization level of dielectric layer: As in Example 1, the half-value width of the peak of the (101) plane indexed by the tetragonal structure of the dielectric layer was measured to obtain an index of crystallization level. As a result, 0.337 deg. -0.683 deg. It became the value of. In Comparative Example 2 below, the same process is adopted until the formation of the dielectric layer. Therefore, it is clearly stated that the half-value width of the peak on the (101) plane is the same.

Observation of Dielectric Layer with Transmission Electron Microscope: The cross section of the capacitor layer forming material of Sample 3-1 was processed with a focused ion beam in the same manner as in Example 1 and observed with a transmission electron microscope. This observation image is shown in FIG. As is clear from FIG. 4, which is a cross section of the sample 3-1, the dielectric layer 1 has a crystal grain size of 50 nm or less, and can be observed as being composed of extremely fine crystals.

  Each characteristic described above is listed in Table 1 so that it can be compared with the first embodiment.

[Comparative Example 2]
In Comparative Example 2, the same manufacturing flow as that of Example 2 is adopted, but the steps (b) and (c) are different. Therefore, only different processes will be described.

(B) Step: In this step, the sol-gel solution is applied to the surface of a nickel foil as a metal substrate, dried in an oxygen-containing atmosphere at 150 ° C. for 2 minutes, and then in an oxygen-containing atmosphere. A series of steps for performing thermal decomposition under conditions of 330 ° C. × 15 minutes was defined as one unit step. And this 1 unit process was repeated 6 times and the film thickness adjustment was performed. Three samples were obtained.

Step (c): One of the above samples is fired in an inert gas replacement atmosphere (nitrogen replacement atmosphere) at 650 ° C. for 15 minutes to form a dielectric layer on the surface of the nickel foil that is the metal substrate. It was set as Sample 4-1. In addition, one of the above samples is fired in an inert gas replacement atmosphere (nitrogen replacement atmosphere) at 650 ° C. for 30 minutes, and a dielectric layer is formed on the surface of a nickel foil as a metal base material. did. Further, one of the above samples is subjected to a baking treatment in an inert gas replacement atmosphere (nitrogen replacement atmosphere) at 700 ° C. for 60 minutes, and a dielectric layer is formed on the surface of a nickel foil as a metal base, did. Thereafter, a capacitor circuit was manufactured using the mask method in the same manner as in Example 2.

<Evaluation of dielectric properties>
Electrode yield: After the capacitor circuit is formed, a predetermined voltage is applied to 100 capacitor circuits of each sample, interlayer withstand voltage measurement is performed, and no short-circuit phenomenon is observed between the upper electrode and the lower electrode. I saw the ratio. As a result, the production yield of 1 mm × 1 mm size capacitor circuits was 50% to 90%, and the production yield of 4 mm × 4 mm size capacitor circuits was 0% to 20%.

Electric capacity density: The initial average capacity density was as high as 1010 nF / cm ^{2 to} 1240 nF / cm ² .

Dielectric loss: When the dielectric loss of the capacitor circuit was measured, it was in the range of 5% to 8%.

Dielectric layer crystallization level: Since it is the same as Comparative Example 1, description thereof is omitted.

  Each characteristic described above is listed in Table 2 so that it can be compared with Example 2 above.

<Contrast between Example and Comparative Example>
Hereinafter, in the comparison between the example and the comparative example, the above example and the comparative example will describe the reason why both the etching method and the mask method are used for forming the capacitor shape. The essential effect of the pre-baking of the manufacturing method according to the present invention is that the etching solution passes through the film during the etching and damages the substrate. Therefore, this phenomenon causes damage to the dielectric layer itself (specifically, the dielectric layer disappears). Is that it can be prevented. If only this phenomenon is evaluated, it is considered that only the evaluation result of the capacitor created by the etching method is sufficient.

  However, the capacitor method was intentionally formed by the mask method, and the evaluation result was shown that the superiority of the capacitor circuit obtained by adopting the pre-firing process is related to the capacity density that impairs the reliability of the evaluation by the etching method. It is for showing. That is, in the etching method, the dielectric loss is large due to damage of the dielectric layer, and the leakage current tends to increase. The capacitance density in such a case is unlikely to be a true capacitance density, and it is considered that a capacitor obtained by a mask method without etching exhibits a true dielectric property.

Comparison between Example 1 and Comparative Example 1 Example 1 and Comparative Example 1 are evaluation results when a capacitor circuit is formed using an etching method. As is apparent from Table 1, when only the capacitance density is observed, Comparative Example 1 (Sample 3-1 to Sample 3-3) is more in comparison with Example 1 (Sample 1-1 to Sample 1-8). It is high. However, looking at the dielectric loss, it can be seen that the dielectric loss of Comparative Example 1 (Sample 3-1 to Sample 3-3) exceeds 20% and lacks stability as a capacitor. On the other hand, the dielectric loss of Example 1 (Sample 1-1 to Sample 1-8) is 16% or less, achieving a high capacity at a certain level, and improving the quality stability as a capacitor. It is clear that it is excellent.

  When the production yield after the capacitor circuit is formed by the etching method is seen, Example 1 (Sample 1-1 to Sample 1-8) is more comparative example 1 (Sample 3-1 to Sample 3-3). It can be understood that the production stability is also excellent. Further, comparing the crystallization level of the dielectric layer, the half width of Example 1 (Sample 1-1 to Sample 1-8) is larger than that of Comparative Example 1 (Sample 3-1 to Sample 3-3). It can be seen that a sharp diffraction peak is obtained. This is supported by the fact that the crystallization level is improved, the oxide dielectric layer constituting the dielectric layer is dense and the film density is high, and structural defects are reduced. As in the case of Sample 3-1 to Sample 3-3, firing is performed at the end, and no matter how long the firing time is taken, unless a pre-baking step as applied to Sample 1-1 to Sample 1-8 is provided, The crystallinity cannot be improved.

  Next, as is clear from observation of the dielectric layer with a transmission electron microscope, the dielectric layer of the capacitor layer forming material of Sample 1-1 and Sample 1-3 of Example 1 is large and dense, The flow path of the leak current is reduced, and the permeability of the etching solution is also lowered. On the other hand, in the case of the sample 3-1 of the comparative example 1, since it is composed of extremely fine crystals, the crystals are not dense and there are many structural defects, the number of leakage current channels is increased, and the permeability of the etching solution is increased. Also gets higher.

  Further, regarding the permeability of the etching solution to the dielectric layer, it was examined whether or not the dielectric layer remained in the inter-circuit gap after the capacitor circuit was formed. In any of the cases 8, the residual dielectric layer could be confirmed. On the other hand, the dielectric layer did not remain in any of Samples 3-1 to 3-3 of Comparative Example 1. This supports the hypothesis made from the observation image of the transmission electron microscope.

Comparison between Example 2 and Comparative Example 2 Example 2 and Comparative Example 2 are evaluation results when a capacitor circuit is formed using a mask method. As is apparent from Table 2, even when the electric capacity density is seen, Comparative Example 2 (Sample 4-1 to Sample 4-3) is more in Example 2 (Sample 2-1 to Sample 2-8). In comparison, it is relatively low. On the other hand, looking at the dielectric loss, it can be said that the dielectric loss of Comparative Example 2 (Sample 4-1 to Sample 4-3) and the dielectric loss of Example 2 (Sample 2-1 to Sample 2-8) are at the same level. . However, considering the balance between the capacitance density and the dielectric loss, it is clear that Example 2 achieves a higher capacity at a certain level and is superior in quality stability as a capacitor. is there.

  The above contents will be explained more strictly and concretely. Pre-baking was performed once, and pre-baking was performed between one unit process (first time) and one unit process (second time). It can be said that the dielectric loss is low and the capacity density is clearly superior to any sample of Comparative Example 2. On the other hand, by bringing the firing timing to the second, third, and fourth layers, the dielectric loss does not change, but the difference from the comparative example of the capacitance density is not clear. In other words, it seems that the capacity density tends to decrease as the timing of the pre-firing is delayed during a plurality of one-unit processes. That is, if the comparison is made under the condition of pre-baking once, it can be determined that the above-described data is excellent and preferable in that the pre-baking is performed at the initial stage of the film forming cycle because of the effect of improving the electrical characteristics. On the other hand, when the preliminary firing timing is delayed, the capacity density decreases. It is considered that the firing conditions for the thickness of the dielectric film approach the comparative example 2 as the firing timing is delayed.

  Then, looking at the production yield after the capacitor circuit is formed by the mask method, Example 2 (Sample 2-1 to Sample 2-8) is more comparative example 2 (Sample 4-1 to Sample 4-3). It can be understood that the production stability is also excellent. Further, when comparing the crystallization level of the dielectric layer, the half width of Example 2 (Sample 2-1 to Sample 2-2) is the half width of Comparative Example 2 (Sample 4-1 to Sample 4-3). It can be seen that a sharp diffraction peak is obtained. This is supported by the fact that the crystallization level is improved, the oxide dielectric layer constituting the dielectric layer is dense and the film density is high, and structural defects are reduced. When firing is performed last as in Sample 4-1 to Sample 4-3, no matter how long the firing time is taken, unless a pre-baking step is applied as in Sample 2-1 to Sample 2-8, It is not possible to improve the performance.

  Example 2 and Comparative Example 2 are cases in which a capacitor circuit is formed by a mask method. When the entire data in such a case is viewed, assuming that the dielectric loss is the same regardless of the presence or absence of preliminary firing, With firing, the crystallinity is excellent, that is, the capacity density is larger (unlike the etching method, the mask method shows the same tendency as the half width, and the capacity density is also shown. That is, the smaller the half width, the larger the capacity density). In addition, the total calorie is smaller in the case of 650 ° C. × 15 minutes + 650 ° C. × 15 minutes in the pre-baking than in 700 ° C. × 60 minutes without the pre-baking, but the latter seems to be better in the crystallinity and capacity density.

Comparison between etching method and mask method: Finally, a comparison between the etching method and the mask method used in the above-described embodiments and the like is performed. When the capacitor circuit is formed by the etching method, it can be seen that, in comparison with Example 1, in Comparative Example 1, the dielectric loss is significantly increased and the electrode yield is decreased due to the damage caused by the etching solution. When the capacitor circuit is formed by the mask method, the dielectric loss does not increase even in Comparative Example 2. However, it can be seen that Example 2 is superior in terms of capacitance density and electrode yield. Thus, by comparing the evaluation results of the capacitor circuit formed by the etching method and the mask method, the dielectric layer according to the present invention has the effect of not only reducing etching damage but also improving the quality of the dielectric layer itself. It becomes clear that.

  The method for forming an oxide dielectric layer by the sol-gel method according to the present invention is capable of forming a high-quality oxide dielectric layer with a high yield, and supplying various electronic materials having a high-quality dielectric layer to the market. It is possible to do. The method for forming an oxide dielectric layer by a sol-gel method according to the present invention enables the production of an oxide dielectric layer using a sol-gel method that does not require excessive capital investment. Therefore, inexpensive and high-quality electronic and electrical products can be supplied to the market. The dielectric layer obtained by the method for forming an oxide dielectric layer according to the present invention has a characteristic that it is not easily damaged by an etching solution, and is particularly suitable for forming a capacitor circuit by an etching method. That is, the capacitor layer forming material in which the dielectric layer is formed by using the method for forming an oxide dielectric layer by the sol-gel method according to the present invention is suitable for forming a capacitor layer of a printed wiring board and has a high electric capacity. This makes it possible to manufacture a capacitor circuit exhibiting a low dielectric loss. Therefore, a printed wiring board or the like obtained using this capacitor layer forming material contributes to power saving of electronic and electric products.

It is an observation image when the cross section of the capacitor layer forming material in which the oxide dielectric layer is formed by the sol-gel method according to the present invention is processed with a focused ion beam and observed with a transmission electron microscope. It is an observation image when the cross section of the capacitor layer forming material in which the oxide dielectric layer is formed by the sol-gel method according to the present invention is processed with a focused ion beam and observed with a transmission electron microscope. It is an observation image when the cross section of the capacitor layer forming material in which the oxide dielectric layer is formed by the sol-gel method according to the present invention is processed with a focused ion beam and observed with a transmission electron microscope. It is an observation image when the section of a capacitor layer forming material is processed with a focused ion beam and observed with a transmission electron microscope (conventional example). It is an observation image when the interface part of the 2nd conductive layer of a capacitor layer forming material and a dielectric layer is processed with a focused ion beam, and observed with a transmission electron microscope. It is an observation image when the interface part of the 2nd conductive layer of a capacitor layer forming material and a dielectric layer is processed with a focused ion beam, and observed with a transmission electron microscope. It is a schematic diagram showing the manufacturing flow of a printed wiring board provided with the built-in capacitor circuit using the capacitor layer forming material which concerns on this invention. It is a schematic diagram showing the manufacturing flow of a printed wiring board provided with the built-in capacitor circuit using the capacitor layer forming material which concerns on this invention. It is a schematic diagram showing the manufacturing flow of a printed wiring board provided with the built-in capacitor circuit using the capacitor layer forming material which concerns on this invention. It is a schematic diagram showing the manufacturing flow of a printed wiring board provided with the built-in capacitor circuit using the capacitor layer forming material which concerns on this invention.

Explanation of symbols

1,13 Dielectric layer 2 First layer
3, 15 Upper electrode 4, 19 Lower electrode 5 Different phase 10 Printed wiring board 11 Capacitor layer forming material 12 First conductive layer
14 Second conductive layer 16 Copper foil layer 17 Semi-cured resin layer 17 ′ Insulating layer 18 Copper foil with resin 21 Etching resist layer 22 Outer layer circuit 23 Via hole 24 Copper plating layer

Claims (9)

In the method of forming an oxide dielectric layer by a sol-gel method,
A method for forming an oxide dielectric layer comprising the following steps (a) to (c):
(A) A solution preparation step for preparing a sol-gel solution for producing a desired oxide dielectric layer.
(B) A series of coating the sol-gel solution on the surface of a metal substrate, drying at 120 ° C. to 250 ° C. in an oxygen-containing atmosphere, and performing thermal decomposition at 270 ° C. to 390 ° C. in an oxygen-containing atmosphere. When the process is a single unit process and this single unit process is repeated a plurality of times, an inert gas replacement at 550 ° C. to 1000 ° C. or a pre-baking process in vacuum is optionally provided between the single unit process and the single unit process. Coating process to adjust the film thickness.
(C) A firing step of finally performing a firing process at 550 ° C. to 1000 ° C. to obtain a dielectric layer. The method for forming an oxide dielectric layer according to claim 1, wherein an atmosphere of the firing treatment of (c) is in an inert gas substitution or vacuum. The sol - gel solution, the oxide as a dielectric layer _{(Ba 1-x Sr x)} TiO 3 (0 ≦ x ≦ 1) according to claim 1 or claim 2 and forms a film or BiZrO ₃ film Method for forming an oxide dielectric layer. The sol-gel solution forms an oxide dielectric layer containing 0.01 mol% to 5.00 mol% of one or more selected from manganese, silicon, nickel, aluminum, lanthanum, niobium, magnesium, and tin. The method for forming an oxide dielectric layer according to claim 1 . The method for forming an oxide dielectric layer according to claim 1 , wherein the dielectric layer has a thickness of 20 nm to 2 μm. The metal substrate, nickel foil thickness of 1 m to 100 m, a nickel alloy foil, a composite foil having a nickel layer on the surface layer, claims 1 to either a composite foil with a nickel alloy layer on the surface layer 6. The method for forming an oxide dielectric layer according to any one of 5 above. The method for forming an oxide dielectric layer according to claim 6 , wherein the nickel alloy layer of the composite foil including the nickel alloy foil or the nickel alloy layer as a surface layer is made of a nickel-phosphorus alloy. In the capacitor layer forming material comprising a dielectric layer between the first conductive layer used for forming the upper electrode and the second conductive layer used for forming the lower electrode,
The said dielectric layer is obtained by the formation method of the oxide dielectric layer in any one of Claims 1-7, The capacitor layer forming material characterized by the above-mentioned. A printed wiring board comprising a built-in capacitor layer obtained using the capacitor layer forming material according to claim 8 .