JP2006324383A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To sufficiently improve sensitivity for a light up to a long wavelength. <P>SOLUTION: A solid-state imaging apparatus including a photoelectric conversion element and a modulating section formed so as to be adjacent to the photoelectric conversion element is provided with a substrate having a projection portion having a surface formed on a position higher than that of other portions in the photoelectric conversion element forming region, the photoelectric conversion element formed on the lower part of the projection portion, and the modulating section formed so as to be adjacent to the photoelectric conversion element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device having high image quality characteristics and low power consumption characteristics.

  As a solid-state imaging device mounted on a cellular phone or the like, there are a CCD (charge coupled device) type image sensor and a CMOS type image sensor. A CCD type image sensor has excellent image quality, and a CMOS type image sensor has low power consumption and low process cost. In recent years, a MOS type solid-state imaging device of a threshold voltage modulation method that has both high image quality and low power consumption has been proposed. A threshold voltage modulation type MOS solid-state imaging device is disclosed in, for example, Patent Document 1.

  The image sensor obtains an image output by arranging sensor cells in a matrix and repeating three states of initialization, accumulation, and readout. In the image sensor disclosed in Patent Document 1, each unit pixel includes a light receiving diode for performing accumulation and a transistor for performing readout.

  FIG. 8 is a schematic cross-sectional view showing the image sensor disclosed in Patent Document 1. As shown in FIG.

  In the image sensor of FIG. 8, a light receiving diode 111 and an insulated gate field effect transistor 112 are adjacently arranged for each unit pixel on the substrate 100. The gate electrode 113 of the transistor 112 is formed in a ring shape, and a source region 114 is formed in the central opening of the gate electrode 113. A drain region 115 is formed around the gate electrode 113.

Charges (photogenerated charges) generated by light incident from the opening region of the light receiving diode 111 are transferred to the P-type well region 116 below the gate electrode 113 and accumulated in the carrier pocket 117 formed in this portion. . The threshold voltage of the transistor 112 is changed by the photo-generated charges accumulated in the carrier pocket 117. As a result, a signal (pixel signal) corresponding to the incident light can be extracted from the source region 114 of the transistor 112.
JP 2001-177085 A

  By the way, the carrier pocket 117 is formed at a relatively high concentration, and the potential is sufficiently low (or deep) on the basis of the hole potential. As a result, photogenerated charges generated in the light receiving diode 111 are accumulated in the carrier pocket 117.

  On the other hand, photogenerated charges based on light having a short wavelength among incident light of the light receiving diode 111 are generated on the substrate surface, and photogenerated charges are generated at deeper positions from the substrate surface as the wavelength becomes longer. Therefore, the sensitivity to light having a longer wavelength can be increased as the substrate depth increases. The photo-generated charges generated in the light receiving diode 111 are transferred to the carrier pocket in the depleted well region according to the potential change.

  However, the hole potential is high (or shallow) on the basis of the hole potential at a position where the substrate depth is deep, and the photogenerated charges generated at the deep position of the substrate cannot be collected in the well region. It cannot be transferred to the pocket 117.

  That is, there is a limit to the depth of the substrate that can transfer photogenerated charges, and there is a problem that the sensitivity to light having a long wavelength cannot be sufficiently increased. This problem is not limited to a CMOS type image sensor, but is a problem common to all image devices including a CCD type and the like and having a light receiving diode.

  A method of increasing the sensitivity of light having a long wavelength by increasing the depletion layer without changing the substrate thickness is also conceivable. However, in order to widen the depletion layer, it is necessary to increase the applied voltage. That is, it is necessary to increase the power supply voltage, which causes a problem in system design.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a solid-state imaging device capable of sufficiently improving the light receiving sensitivity with respect to light having a long wavelength.

  The solid-state imaging device according to the present invention is a solid-state imaging device including a photoelectric conversion element and a modulation unit formed adjacent to the photoelectric conversion element, and has a surface at a position higher than other portions in the light conversion element formation region. And a photoelectric conversion element formed below the protrusion, and a modulation part formed adjacent to the photoelectric conversion element.

  According to such a configuration, the substrate has a protruding portion having a surface formed at a high position in the photoelectric conversion element formation region. A photoelectric conversion element is formed below the protrusion. That is, the photoelectric conversion element formation region is thicker than the other parts, and the distance from the surface of the protrusion to the lower part of the photoelectric conversion element can be made relatively large. Thereby, in the photoelectric conversion element, photogenerated charges due to light having a long wavelength can be collected, and sensitivity to light having a long wavelength can be improved.

  Moreover, the solid-state imaging device according to the present invention is a solid-state imaging device including a photoelectric conversion element and a modulation unit formed adjacent to the photoelectric conversion element, and is positioned higher than other portions in the light conversion element formation region. Formed on the first impurity layer in the region where the photoelectric conversion element is formed, and a reverse conductivity type first impurity layer formed on the substrate. A second impurity layer of one conductivity type, and a third impurity layer of one conductivity type formed on the first impurity in the transistor formation region, to which photogenerated charges are transferred from the second impurity layer, A gate electrode formed on the substrate above the third impurity layer and having an opening; a source formed on the substrate surface side of the opening; and a source spaced from the source; A drain electrically connected to one impurity layer Characterized by comprising a down.

  According to such a configuration, the photogenerated charges generated in the first impurity layer in the photoelectric conversion element formation region are transferred from the second impurity layer to the third impurity layer. The threshold voltage of the channel of the transistor is controlled by the photogenerated charge transferred to the third impurity layer, and a pixel signal corresponding to the photogenerated charge is output from the transistor. The photoelectric conversion element region is thicker than other parts, and the distance from the surface of the protrusion to the lower part of the photoelectric conversion element is relatively large. Thereby, in the photoelectric conversion element, photogenerated charges due to light having a long wavelength can be collected, and sensitivity to light having a long wavelength can be improved.

  The lower portion of the second impurity layer and the lower portion of the third impurity layer may be formed at substantially the same height.

  According to such a configuration, the gradient of potential can be set relatively easily from the second impurity layer to the third impurity layer, and the photo-generated charges generated in the photoelectric conversion element region can be reliably supplied to the third impurity. Can be transferred to the layer.

  The distance from the top of the second impurity layer to the surface of the protrusion may be greater than the distance from the top of the third impurity layer to the surface of the substrate.

  According to such a configuration, photogenerated charges can be effectively obtained even above the second impurity layer.

  Further, the gate electrode is formed in a ring shape.

  The semiconductor device may further include a fourth impurity layer formed at a higher concentration than the third impurity layer below the gate electrode in the third impurity layer.

  According to such a configuration, photogenerated charges can be transferred reliably below the gate electrode, and modulation efficiency can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 6 relate to a first embodiment of the present invention. FIG. 1 is a schematic sectional view showing a sectional shape of one sensor cell of a solid-state imaging device according to the present embodiment. FIG. It is explanatory drawing which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on a form. 1 is a cross-sectional view taken along line A-A ′ of FIG. 2. FIG. 3 is a circuit block diagram showing the entire structure of the element by an equivalent circuit. 4 to 6 are process diagrams for explaining the manufacturing method by the sectional shape of the element and the planar shape of the mask. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

<Structure of sensor cell>
The solid-state imaging device according to the present embodiment has a sensor cell array in which sensor cells that are unit pixels are arranged in a matrix. Each sensor cell collects and accumulates photogenerated charges generated according to incident light, and outputs a pixel signal at a level based on the accumulated photogenerated charges. An image signal of one screen can be obtained by arranging the sensor cells in a matrix.

  First, the structure of each sensor cell will be described with reference to FIGS. 1 and 2 show one sensor cell. This embodiment shows an example in which holes are used as photogenerated charges. Even in the case where electrons are used as the photo-generated charges, the same configuration is possible. FIG. 1 shows a cross-sectional structure of the cell cut along the line A-A ′ of FIG. 2.

  As shown in the plan view of FIG. 2, a photodiode PD and a modulation transistor TM are provided adjacent to each other in a sensor cell 3 that is a unit pixel. As the modulation transistor TM, for example, an N-channel depletion MOS transistor is used.

  In the photodiode PD formation region, which is a photoelectric conversion element formation region, an opening region that transmits light is formed in the step of forming a wiring layer on the surface of the substrate 1. A P-type well wider than the opening region is formed at a relatively shallow position on the surface of the substrate 1, and a collection well 4 as a second impurity layer for collecting photogenerated charges generated by the photoelectric conversion element is formed. Yes. An N-type diffusion layer 32 that also functions as a pinning layer is formed on the surface of the substrate 1 on the collection well 4.

  A P-type well is formed in the modulation transistor TM formation region at a position substantially the same substrate depth as that of the collection well 4, and the photo-generated charges collected in the collection well 4 are transferred to control the modulation transistor TM. A modulation well 5 is formed as a three impurity layer.

An annular gate (ring gate) 6 is formed on the surface of the substrate 1 on the modulation well 5, and a region near the surface of the substrate 1 in the central opening of the ring gate 6 is a high-concentration N-type region. A source region 7 is formed. In FIG. 2, the ring gate 6 and carrier pockets, which will be described later, are shown in a circular shape, but may be any polygonal shape such as an elliptical shape or an octagonal shape. An N-type drain region 8 is formed around the ring gate 6. An N ⁺ drain contact region (not shown) is formed near the surface of the substrate 1 at a predetermined position of the drain region 8.

  The modulation well 5 controls the threshold voltage of the channel of the modulation transistor TM. In the modulation well 5, a carrier pocket 10 (shaded portion in FIG. 2) as a fourth impurity layer which is a P-type high concentration region is formed below the ring gate 6. The modulation transistor TM is constituted by the modulation well 5, the ring gate 6, the source region 7 and the drain region 8, and the threshold voltage of the channel changes according to the electric charge accumulated in the modulation well 5 (carrier pocket 10). It is like that.

  The drain region 8, N-type wells 21, 21 ′, which will be described later, and the diffusion layer 32 are biased to a positive potential by applying a drain voltage, so that the diffusion layer 32 and the collection well 4 are located below the opening region of the photodiode PD. From the boundary surface between the N-type well 21 serving as the first impurity layer and the collection well 4, the depletion layer extends over and around the collection well 4. In the depletion region, photogenerated charges due to light incident through the opening region are generated. As described above, the generated photo-generated charges are collected in the collection well 4.

  The charges collected in the collection well 4 are transferred to the modulation well 5 and held in the carrier pocket 10. As a result, the source potential of the modulation transistor TM is in accordance with the amount of charge transferred to the modulation well 5, that is, the incident light to the photodiode PD.

<Sensor cell cross section>
Furthermore, the cross-sectional structure of the sensor cell 3 will be described in detail with reference to FIG.

  A P-type buried layer 23 is formed on the substrate 1 in the modulation transistor TM formation region. An N-type well 21 ′ is formed on the P-type buried layer 23. The P-type buried layer 23 limits the N-type well 21 'to a relatively shallow position on the substrate. A P-type modulation well 5 is formed on the N-type well 21 '. A carrier pocket 10 is formed in the modulation well 5.

The carrier pocket 10 has a ring shape as shown in FIG. 2 below the ring gate 6. The carrier pocket 10 is a sufficiently high concentration diffusion layer by P ⁺ diffusion. For example, the P-type concentration of the modulation well 5 is 1 × 10 ¹⁶ atoms / cm ^3, and the P-type concentration of the carrier pocket 10 is 1 × 10 ¹⁷ atoms / cm ³ .

  In the modulation transistor TM formation region, the ring gate 6 is formed on the substrate surface via the gate oxide film 31, and the N-type diffusion layer 27 constituting the channel is formed on the substrate surface below the ring gate 6.

An N ⁺ diffusion layer is formed on the substrate surface at the center of the ring gate 6 to form the source region 7. Further, an N-type diffusion layer is formed on the substrate surface around the ring gate 6 to constitute the drain region 8. The N type diffusion layer 27 constituting the channel is electrically connected to the source region 7 and the drain region 8.

  An isolation region 22 is provided between the photodiode PD formation region and the modulation transistor TM formation region of adjacent cells.

The isolation region 22 is electrically connected to the N-type wells 21, 21 ′ and the drain region 8.

  On the other hand, the photodiode PD formation region has an N-type well 21 and a collection well 4 that are successively formed in the N-type well 21 ′ and the modulation well 5 in the modulation transistor TM formation region. The buried layer 23 is not formed on the photodiode PD formation region side, and the N-type well 21 is formed up to a relatively deep position of the substrate 1.

  A P-type collection well 4 is formed on the N-type well 21. An N-type diffusion layer 32 that also functions as a pinning layer is formed on the substrate surface side above the collection well 4.

  In the present embodiment, the substrate 1 has a protrusion 45 whose surface position is higher in the photodiode PD formation region than in the modulation transistor TM formation region. The protrusion 45 is provided in the whole area of the photodiode PD formation region in plan view. With this configuration, in the photodiode PD formation region, the depth (thickness) of the substrate can be made deeper (thicker) than the modulation transistor TM formation region.

  Even in this case, the relationship between the N-type well 21 and the N-type well 21 ′ in the substrate depth direction is the same as in the conventional case, that is, the substrate depth above both of them is based on the substrate surface of the modulation transistor TM formation region. Set to be approximately the same. Further, the substrate depth below the collection well 4 and the substrate depth below the modulation well 5 are substantially matched with each other with the substrate surface of the modulation transistor TM formation region as a reference.

  On the other hand, in the present embodiment, since the projecting portion 45 is provided in the photodiode PD formation region, there is a margin in the arrangement of each layer in the substrate depth direction, and the collection well 4 in the substrate depth direction. While increasing the thickness, the thickness of the diffusion layer 32 in the substrate depth direction can be increased.

  That is, in the present embodiment, photogenerated charges are sufficiently generated even above the collection well 4, and most of the photogenerated charges generated near the substrate surface in the photodiode PD formation region are collected in the collection well 4. Can be made possible. The substrate depth of the N-type well 21 in the photodiode PD formation region is increased by the thickness of the protrusion 45, and photogenerated charges due to light in a high wavelength region are generated.

  Further, the positional relationship among the N-type wells 21 and 21 ′, the collection well 4 and the modulation well 5 is the same as in the prior art, and the photogenerated charges generated in the deep position of the N-type well 21 are the same as in the prior art. Can be transferred to the modulation well 5 through the collection well 4.

<Circuit configuration of the entire device>
Next, a circuit configuration of the entire solid-state imaging device according to the present embodiment will be described with reference to FIG.

  The solid-state imaging device 61 includes a sensor cell array 62 including the sensor cells 3 of FIG. 2 and circuits 63 to 65 for driving the sensor cells 3 in the sensor cell array 62. The sensor cell array 62 is configured by arranging the cells 3 in a matrix. The sensor cell array 62 includes, for example, a 640 × 480 cell 3 and an optical black (OB) region (OB region). When the OB region is included, the sensor cell array 62 is composed of, for example, 712 × 500 cells 3.

  Each sensor cell 3 includes a photodiode PD that performs photoelectric conversion and a modulation transistor TM for detecting and reading out an optical signal. The photodiode PD generates a charge (photogenerated charge) corresponding to the incident light, and the generated charge is collected in the collection well 4 (corresponding to the connection point PDW in FIG. 3). The photo-generated charges collected in the collection well 4 are transferred to and held in the carrier pocket 10 in the modulation well 5 (corresponding to the connection point TMW in FIG. 3) for threshold modulation of the modulation transistor TM.

  The modulation transistor TM is equivalent to a change in the back gate bias due to the photogenerated charge held in the carrier pocket 10, and the channel threshold voltage changes according to the amount of charge in the carrier pocket 10. As a result, the source voltage of the modulation transistor TM corresponds to the charge in the carrier pocket 10, that is, corresponds to the brightness of the incident light of the photodiode PD.

  In this manner, each cell 3 exhibits operations such as accumulation, transfer, readout, and discharge by applying drive signals to the ring gate 6, the source region 7, and the drain region 8 of the modulation transistor TM. As shown in FIG. 3, signals are supplied to each part of the cell 3 from a vertical drive scanning circuit 63, a drain drive circuit 64, and a horizontal drive scanning circuit 65. The vertical drive scanning circuit 63 supplies a scanning signal to the gate line 67 in each row, and the drain drive circuit 64 applies a drain voltage to the drain region 8 in each column. The horizontal drive scanning circuit 65 supplies a drive signal to the switch 68 connected to each source line 66.

  Each cell 3 is provided corresponding to the intersection of a plurality of source lines 66 arranged in the horizontal direction in the sensor cell array 62 and a plurality of gate lines 67 arranged in the vertical direction. In each cell 3 of each line arranged in the horizontal direction, the ring gate 6 of the modulation transistor TM is connected to a common gate line 67, and each cell 3 in each column arranged in the vertical direction is the source of the modulation transistor TM. Are connected to a common source line 66.

  By supplying an ON signal (selection gate voltage) to one of the plurality of gate lines 67, the cells commonly connected to the gate line 67 to which the ON signal is supplied are simultaneously selected, and these selected cells are selected. A pixel signal is output from each source via each source line 66. The vertical drive scanning circuit 63 supplies an ON signal to the gate line 67 while sequentially shifting it in one frame period. Pixel signals from each cell of the line to which the ON signal is supplied are simultaneously read from each source line 66 for one line and supplied to each switch 68. The pixel signals for one line are sequentially output (line output) for each pixel from the switch 68 by the horizontal drive scanning circuit 65.

  The switch 68 connected to each source line 66 is connected to the video signal output terminal 70 via a common constant current source (load circuit) 69. The source of the modulation transistor TM of each sensor cell 3 is connected to the constant current source 69, and the source follower circuit of the sensor cell 3 is configured.

<Operation>
Next, photodetection of the photodiode PD of the sensor cell 3, collection operation of photogenerated charges, and readout operation of the modulation transistor TM will be described.

  A low gate voltage is applied to the ring gate 6 of the modulation transistor TM, and a voltage (VDD) of approximately 2 to 4 V, for example, necessary for the operation of the transistor is applied to the drain region 8. As a result, the N-type well 21 is depleted. An electric field is generated between the drain region 8 and the source region 7.

  Light incident through the opening region 2 of the photodiode PD enters the depleted N-type well 21 to generate electron-hole pairs (photogenerated charges).

  In the present embodiment, the depth of the substrate is deep in the photodiode PD formation region, and photogenerated charges due to light having a long wavelength can be generated. For example, the N-type well 21 that is depleted to a position of about 3 μm in the substrate depth direction can be formed on the basis of the substrate surface of the photodiode PD formation region, and photogenerated charges due to red light can be generated. .

  The P-type collection well 4 has a low potential due to the introduction of high-concentration P-type impurities, and the photogenerated charges generated in the N-type well 21 are collected in the collection well 4. Further, the photogenerated charges are transferred from the collection well 4 to the modulation well 5 in the modulation transistor formation region and accumulated in the carrier pocket 10.

  The potential varies with the impurity concentration. Even with the same impurity concentration, it varies depending on the level of the fixed potential applied around the impurity and the distance to the fixed potential. In the present embodiment, the distance from the lower part of the N-type well 21 to the collection well 4 and the potential gradient between the collection well 4 and the modulation well 5 are the same as those in the conventional case, and are generated in the N-type well 21. Most of the generated photocharge can be collected in the collection well 4 and transferred to the modulation well 5.

  The threshold voltage of the modulation transistor TM is changed by the photo-generated charges accumulated in the carrier pocket 10. In this state, a gate voltage (selection gate voltage) of about 2 to 4 V, for example, is applied to the ring gate 6 of the selected pixel, and a voltage VDD of about 2 to 4 V, for example, is applied to the drain region 8. Further, a constant current is passed through the source region 7 of the modulation transistor TM by the constant current source 69. As a result, the modulation transistor TM forms a source follower circuit, and the source potential changes following the change in the threshold voltage of the modulation transistor TM due to the photo-generated charges, so that the output voltage changes. That is, an output corresponding to the incident light can be obtained.

  Photogenerated charges based on light having a long wavelength are collected in the photodiode PD formation region, and an output having sufficient sensitivity can be obtained even for light having a long wavelength.

  At the time of initialization, the charge remaining in the carrier pocket 10, the collection well 4, and the modulation well 5 is discharged. For example, a positive voltage of 5 V or more is applied to the drain region 8 and the ring gate 6 of the modulation transistor TM. The N-type well 21 ′ below the modulation well 5 is thin, and a high concentration P-type buried layer 23 is formed on the substrate 1 facing the N-type well 21 ′ so that a depletion layer toward the substrate 1 is formed. Therefore, the voltage applied to the ring gate 6 acts only on the modulation well 5 and its adjacent region. That is, an abrupt potential change occurs in the modulation well 5, and a strong electric field that sweeps out the photogenerated charge toward the substrate 1 is mainly applied to the modulation well 5, and the remaining photogenerated charge has a relatively low reset voltage. Thus, it is more reliably discharged onto the substrate 1.

  After initialization, a non-selection gate voltage having a relatively low voltage value is applied to the ring gate of the non-selection pixel, and a selection gate voltage having a relatively high voltage value is applied to the ring gate 6 of the selection pixel. Then, a signal output after initialization of the selected pixel is obtained from the commonly connected source line 66.

<Process>
Next, a method for manufacturing the element will be described with reference to the process diagrams of FIGS. 4 to 6, the cross-sectional shape of the element is shown on the left side, and the planar shape of a mask or the like used in the manufacturing process of the left element is shown on the right side. 4 to 6, the cross section at the position of the right AA ′ cutting line is shown by the left cross-sectional shape. 4 to 6, arrows on the substrate indicate that ion implantation is performed.

  In this embodiment, first, as shown in FIGS. 4A and 4E, a resist 91 that masks the photodiode PD formation region of the prepared P substrate 1 is formed. Then, portions other than the photodiode PD formation region are removed by etching. Thus, the protrusion 45 is formed in the photodiode PD formation region.

  Next, a resist mask 92 is formed in a portion other than the photodiode formation region, and, for example, phosphorus (phosphorus (P)) ions are implanted to form the N-type well 21 (FIGS. 4B and 4F). ). This ion implantation is performed up to a relatively deep position in the photodiode formation region. Further, using the same resist mask 92, for example, boron (B) ions are implanted to form the P-type collection well 4 on the surface of the substrate 1.

  Next, as shown in FIGS. 4C and 4G, using the resist mask 93, P-type impurities are deeply ion-implanted in the modulation transistor formation region to form the P-type buried layer 23. Further, using the same resist mask 93, phosphorus ions are implanted on the P-type buried layer 23 to form an N-type well 21 '. Thus, the N-type well 21 is formed in the photodiode formation region, and the N-type well 21 'is formed in the modulation transistor formation region. With reference to the substrate surface of the modulation transistor TM formation region, the substrate depths above the N-type wells 21, 21 'are substantially the same.

  Further, using the same resist mask 93, boron ions are implanted on the N-type well 21 to form the modulation well 5. The substrate depths below the collection well 4 and the modulation well 5 are substantially the same with respect to the substrate surface of the modulation transistor TM formation region. The upper portion of the collection well 4 is formed to a position slightly higher than the modulation well 5.

  Further, an N-type diffusion layer 27 for obtaining a channel of the modulation transistor TM is formed in the vicinity of the surface of the substrate 1 using the same resist mask 93.

  Next, a resist mask 94 is formed, and an isolation region 22 for element isolation is formed as shown in FIGS. 4D and 4H. Further, N-type impurities are ion-implanted to drain region 8. Form.

  Next, as shown in FIG. 5A, a gate oxide film 31 is formed on the surface of the substrate 1 by thermal oxidation.

Next, as shown in FIGS. 5B and 5E, a carrier pocket 10 made of a dense P ⁺ diffusion layer is formed in the modulation well 5 below the ring gate 6 using a resist mask 95.

  Next, as shown in FIGS. 5C and 5F, the ring gate 6 of the modulation transistor TM is formed on the gate oxide film 31. As the ring gate 6, an example of a two-layer structure including a lower layer 6a made of a conductive material and an upper layer 6b made of an insulating layer is shown, but a single-layer structure or a multilayer structure may be used.

  Next, as shown in FIGS. 5D and 5G, N-type impurities are ion-implanted using the resist mask 96 and the ring gate 6 formed so as to close the central opening of the ring gate 6 as masks. An N-type diffusion layer 32 that also functions as a pinning layer is formed on the surface of the substrate 1.

Next, after forming an interlayer insulating film 41 on the surface of the substrate 1, a contact hole 42 reaching the center of the opening of the ring gate 6 is formed (FIG. 6A). Then, N ⁺ impurity implantation using phosphorus is performed using the contact hole 42 to form the source region 7 (FIGS. 6A and 6B).

<Effect of Embodiment>
As described above, in the present embodiment, by forming the protrusion on the substrate surface in the photodiode formation region, the thickness of the substrate in the photodiode formation region is increased, and photogenerated charges due to light having a long wavelength are generated. . In addition, by making the substrate depths of the N-type well and P-type modulation well constituting the modulation transistor substantially coincide with the substrate depths of the N-type well and the collection well in the photodiode formation region, Facilitates collection and transfer to carrier pocket. By these, it is possible to obtain a solid-state imaging device having high sensitivity even for light having a long wavelength.

<Second Embodiment>
FIG. 7 is a cross-sectional view showing a cross-sectional shape of a solid-state imaging device according to the second embodiment of the present invention. The embodiment of FIG. 7 is an example applied to another imaging device of the CMOS type.

  Also in the present embodiment, the substrate 201 has a protrusion 204 protruding from the substrate surface of the modulation portion in the photodiode formation region. An N-type well 202 is formed on a P-type substrate 201 in the photodiode formation region. A P-type well 203 is formed on the N-type well 202.

  In the modulation section, an electrode 205 is formed on the surface of the substrate 201, and a diffusion layer 206 and a diffusion layer 207 having a high concentration are formed on the substrate surface between the electrodes 205.

  In the present embodiment, the P-type well 203 is formed up to a position higher than the substrate surface on the modulation unit side, and the substrate is sufficiently thick in the photodiode portion.

  Thereby, in the photodiode, it is possible to generate photogenerated charges due to light having a sufficiently long wavelength.

  With such a configuration, the same operation and effect as in the first embodiment can be obtained also in the present embodiment.

  In each of the above-described embodiments, an example in which the modulation transistor does not form a sidewall is shown, but the modulation transistor may have a sidewall.

1 is a cross-sectional view showing a cross-sectional shape of a solid-state imaging device according to a first embodiment of the present invention. The top view which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on this Embodiment. It is a circuit block diagram which shows the whole structure of an element with an equivalent circuit. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. Sectional drawing which shows the cross-sectional shape of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. FIG. 6 is a schematic cross-sectional view showing an image sensor disclosed in Patent Document 1.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Collection well, 5 ... Modulation well, 6 ... Ring gate, 7 ... Source region, 8 ... Drain region, 10 ... Carrier pocket, 27 ... Diffusion layer, 45 ... Projection, PD ... Photodiode, TM: Modulation transistor.

Claims (6)

In a solid-state imaging device including a photoelectric conversion element and a modulation unit formed adjacent to the photoelectric conversion element,
A substrate having a protrusion having a surface formed at a position higher than the other part in the light conversion element formation region;
A photoelectric conversion element formed below the protrusion,
A solid-state imaging device comprising: a modulation unit formed adjacent to the photoelectric conversion element. In a solid-state imaging device including a photoelectric conversion element and a modulation unit formed adjacent to the photoelectric conversion element,
A substrate of one conductivity type having a protrusion having a surface formed at a position higher than the other part in the light conversion element formation region;
A first impurity layer of a reverse conductivity type formed on the substrate;
A second impurity layer of one conductivity type formed on the first impurity layer in the formation region of the photoelectric conversion element;
A third impurity layer of one conductivity type formed on the first impurity in the transistor formation region to which photogenerated charges are transferred from the second impurity layer;
A gate electrode formed on the substrate above the third impurity layer and having an opening;
A source formed on the substrate surface side of the opening;
A solid-state imaging device comprising: a drain formed apart from the source and electrically connected to the first impurity layer.   The solid-state imaging device according to claim 2, wherein the lower portion of the second impurity layer and the lower portion of the third impurity layer are formed at substantially the same height.   3. The solid according to claim 2, wherein a distance from an upper portion of the second impurity layer to a surface of the protruding portion is larger than a distance from an upper portion of the third impurity layer to the surface of the substrate. Imaging device.   The solid-state imaging device according to claim 2, wherein the gate electrode is formed in a ring shape.   The solid-state imaging device according to claim 2, further comprising a fourth impurity layer formed at a higher concentration than the third impurity layer below the gate electrode in the third impurity layer.

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