JP2006313560A - Microcomputer control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a program or data of a mask ROM built in one-chip microcomputer correctable from outside. <P>SOLUTION: Execution of a program (task, subroutine) of a new version and utilization of updated data of a new version can be performed by adding version information to a mask ROM 2 and an external EPROM 5 which are built in a one-chip microcomputer 6 respectively and comparing those version numbers. Moreover, responding individually to each user can also be made. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a microcomputer control system controlled based on a program or data stored in a predetermined storage means.

  Conventionally, as a conventional example of a microcomputer control system in which a built-in ROM can be changed in a pseudo manner, there is a control device described in Patent Document 1, for example.

JP-A-7-182153

  The control device includes a ROM that stores a control program indicating the control procedure, and a processing device that controls the device by executing the control program, and further replaces a part of the control program in the ROM. A nonvolatile memory storing a program and replacement designation information for instructing whether or not to perform the replacement is detachably provided, and a control program or a replacement program is executed in accordance with the replacement designation information. As a result, the program can be corrected without replacing the original program ROM.

  By the way, in the above-mentioned patent document 1, the program can be corrected without replacing the original program ROM. However, since this correction is determined by replacement designation information stored in the nonvolatile memory, for example, When a part of the control program in the original program ROM is modified and a new version of the control device is created and this nonvolatile memory is used for this, the modified part is If the replacement instruction information of the non-volatile memory indicates that the replacement program is to be replaced, the corrected portion is not used. In order to prevent this, in addition to the correction of the control program in the program ROM, a non-volatile memory of a replacement program corresponding to this is required.

  As described above, in the conventional technique, no consideration has been given to independently changing the control program in the built-in ROM and the external replacement program.

  An object of the present invention is to provide a microcomputer control system in which a control program or data in a built-in memory and a replacement program or data in an external memory can be changed independently.

  In order to achieve the above object, the present invention adds version information to a control program or data in a built-in memory and a replacement program or data in an external memory, and the version information in the built-in memory It is determined whether a control program or data is used or a replacement program or data in an external memory is used.

  In the present invention, the present invention is not limited to the above version information, a plurality of programs or data are compared, a necessary program or data is determined, and an internal or external program or data is used based on the result. This achieves the above object.

  According to the present invention, the version information of the ROM in the one chip is compared with the version number in the external EPROM, the flash memory or the DRAM, so that a new version of the program (TASK, subroutine) can always be executed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a hardware block diagram showing an embodiment of a microcomputer control system according to the present invention, wherein 1 is a CPU (Central Processing Unit), 2 is a ROM (Read Only Memory), and 3 is a RAM (Random Access). Memory), 4 is an I / O (Input / Output) unit, 5 is an EPROM (Erasable Programmable ROM), 6 is a one-chip microcomputer, 7 is an address bus, 8 is a data bus, and 9 is a control bus.

  In this figure, this embodiment shows a one-chip microcomputer 6 in which a CPU 1, ROM 2, RAM 3, and I / O unit 4 are stored in one same chip, an address bus 7, a data bus 8, and a control bus 9. And an external EPROM 5 connected to each other. The CPU 1 controls the entire system, and procedures (programs), data, etc. for operating the CPU 1 are stored in the ROM 2. The ROM 2 is a memory that cannot be rewritten from the outside, and the RAM 3 is a rewritable memory that is used for storing data. The I / O unit 4 is used for input / output of external data and the like. The EPROM 5 stores programs and data for equivalently replacing programs and data in the ROM 2 that cannot be rewritten from the outside.

  In the chip, the CPU 1 includes an address bus 7 that represents an address signal group, a data bus 8 that represents an input / output data signal group of the CPU 1, and a control bus 9 that represents a control signal group such as a read / write signal. The ROM 2, the RAM 3, the I / O unit 4, and the EPROM 5 are combined.

  FIG. 2 (a) shows the information contents stored in the ROM 2, and FIG. 2 (b) shows the information contents stored in the EPROM 5.

  In FIG. 2 (a), the ROM 2 stores a reset vector in the storage area 200 in the address space, a version number a which is version information in the storage area 201, and the storage areas 202 and 203 respectively. It is assumed that TASK1a address and TASK2a address are stored, and TASK1a routine and TASK2a routine corresponding to these TASK1a address and TASK2a address are stored in the storage areas 204 and 205, respectively.

  In FIG. 2B, the EPROM 5 stores identification information (identification code) in the storage area 210 and version number b which is version information in the storage area 211. The storage areas 212 and 213 store the identification information. Assume that the TASK1b address and TASK2b address are stored, respectively, and the TASK1b routine and TASK2b routine corresponding to the TASK1b address and TASK2b address are stored in the storage areas 214 and 215, respectively.

  FIG. 3 is a flowchart showing the processing operation of this embodiment at the time of power-on or reset. The processing procedure will be described below with reference to FIGS.

  When the power is turned on or reset, the CPU 1 issues an address designating the storage area 200 in which the reset vector of the ROM 2 is stored, reads the information stored in the storage area 200 (that is, the reset vector), and resets it. Control is transferred to the vector (the first address in which the first operating program is stored).

  Then, in the program that operates first when the power is turned on or reset, initial setting such as initial setting of the internal register of the CPU 1, initial condition setting of the I / O unit 4, and internal initialization of the RAM 3 is performed (step 30).

  Next, it is determined whether or not the EPROM 5 is connected to the outside (step 31). Specifically, it is determined by reading the storage area of the connected EPROM 5 and confirming the existence of data. If the EPROM 5 is not externally connected, the process proceeds to step 36. If the EPROM 5 is externally connected, it is determined whether or not this is a predetermined EPROM that matches the microcomputer control system of this embodiment. Determine (step 32). This is because identification information (identification code) (for example, a character code “ΔΔΔΔ”, a hash value generated from data and program code in the EPROM 5, etc.) in a specific storage area (here, the storage area 210) of the EPROM 5. ) Is recorded, and whether or not the identification information (identification code) is predetermined is determined. If the connected EPROM 5 is not an EPROM that matches this microcomputer control system, the routine proceeds to step 36.

  When the EPROM 5 is a predetermined EPROM that matches the microcomputer control system, the version information (version number a) stored in the storage area 201 of the ROM 2 and the version information (version version) stored in the storage area 211 of the EPROM 5 No. b) is compared (step 33), and if the version number b of the EPROM 5 is newer as a result of the comparison, the process proceeds to step 35, and if the version number a of the ROM 2 is newer, the step The process proceeds to 36 (step 34).

  In step 35, the TASK addresses (here, the TASK1b address in the storage area 212 and the TASK2b address in the storage area 213) stored in the EPROM 5 are registered in the RAM 3. The state registered in the RAM 3 is shown in FIG. Here, since the registered TASK addresses are stored in the EPROM 5, for example, the TASK 1 b address is registered in the storage area 40 and the TASK 2 b address is registered in the storage area 41.

  In step 36, the TASK addresses recorded in the ROM 2 (here, the TASK 1a address in the storage area 202 and the TASK 2a address in the storage area 203) are registered in the RAM 3. In this case, the TASK address registered in the RAM 3 is different from the contents shown in FIG. 4. For example, the TASK 1 a address is registered in the mechanism area 40 and the TASK 2 a address is registered in the storage area 41.

  When reading the TASK registered in the RAM 3, the TASK is registered using the address of each TASK registered in the RAM 3. As shown in FIG. 4, when the TASK address registered in the RAM 3 is the TASK 1b address and the TASK 2b address in the EPROM 5, the TASK 1 executes the TASK 1b routine stored in the storage area 214 of the EPROM 5. TASK2 then executes the TASK2b routine stored in the storage area 215 of the EPROM 5. In this case, the entire program and data stored in the ROM 2 are replaced with the program and data stored in the EPROM 5, and the program and data stored in the EPROM 5 are used.

  Conversely, if the TASK addresses registered in the RAM 3 are the TASK 1a address and the TASK 2a address in the ROM 2, the TASK 1 executes the TASK 1a routine stored in the storage area 204 of the ROM 2, and the TASK 2 stores the storage area 205 in the ROM 2. The TASK2a routine stored in is executed. In this case, the program and data stored in the ROM 2 are used.

  Therefore, even if a microcomputer control system is developed in which a program and data stored in the ROM 2 are modified and upgraded, the version number a of the ROM 2 is changed to a new one each time. If the version number a is newer than the version number b of the EPROM 5 even if the external EPROM 5 is used in the microcomputer control system incorporating the ROM 2 storing programs and data, the modified program and data are used. Will be used. Of course, when the program and data in the external EPROM 5 are modified and the version number b becomes newer than the version number a in the ROM 2, the program and data in the EPROM 5 are used. In this way, any combination of the ROM 2 version number a and the EPROM 5 version number b is possible, and the ROM 2 program and data and the EPROM 5 program and data can be changed independently. Even if there is a change, the program and data in the ROM 2 and the program and data in the EPROM 5 are organically combined and used.

  As the ROM2 version number a becomes newer, it increases in units of a block such as 100, 200, 300,..., And the version number b becomes a fine value such as 101, 213, 365,. Increase it. As a result, there is always a difference between these version numbers a and b, and it is possible to determine whether the version is new or old based on the magnitude relationship. If the version numbers match, there is no inconvenience if the programs and data in the ROM 2 are used.

  In the embodiment of FIG. 2, the storage areas 200, 201, 202, 203, 210, 211, 212, and 213 are fixed in which the absolute value of the address is fixedly determined in the absolute address space. The address is more effective for system configuration. However, the implementation of the present invention is not limited to only fixed addresses.

  FIG. 5 (a) shows the information contents stored in the ROM 2 in the one-chip microcomputer 6 in another embodiment of the microcomputer control system according to the present invention, and FIG. 5 (b) shows the information content stored in the external EPROM 5. Each of the stored information contents is shown. The hardware configuration of this embodiment is the same as that shown in FIG.

  In FIG. 5 (a), the ROM 2 stores the reset vector and the version number a in the storage areas 500 and 501, respectively, and the TASK address is added to each version after the storage area 502. The TASK routine for these TASK addresses is stored in the storage area 506 and thereafter.

  Here, TASK1a address and TASK2a address are stored as TASK addresses, and TASK1a routine and TASK2a routine corresponding to these are stored, TASK1a address is stored in storage area 503, and TASK1a version number for this is stored in the previous storage. The TASK2a address is stored in the area 502, the TASK2a address is stored in the storage area 505, and the corresponding TASK2a version number is stored in the previous storage area 504.

  In FIG. 5 (b), the EPROM 5 stores the identification code and the version number b in the storage areas 510 and 511, respectively, and the TASK address is added to each version after the storage area 512. The TASK routine for these TASK addresses is stored in the storage area 516 and thereafter. Here, TASK1b address and TASK2b address are stored as TASK addresses, and TASK1b routine and TASK2b routine corresponding to these are stored, TASK1b address is stored in storage area 513, and TASK1b version number for this is stored in the previous storage. The TASK2b address is stored in the area 512, the TASK2b address is stored in the storage area 515, and the corresponding TASK2b version number is stored in the previous storage area 514.

  Also in this embodiment, the entire program and data are respectively stored in the ROM 2 and the EPROM 5 in the above-described form. In the embodiment shown in FIG. 2, the ROM 2 and the EPROM 5 are compared by comparing the version numbers a and b. In this embodiment shown in FIG. 5, the program and data stored in the ROM 2 are replaced with the above program and data. Thus, by providing a version number for each TASK address, the program and data stored in the EPROM 5 can be replaced partially (that is, in units of routines). Therefore, the TASK1b routine and TASK2b routine of EPROM5 can be replaced with the TASK1a routine and TASK2a routine of ROM2, respectively, and the TASK version number, TASK address, and TASK routine are stored in ROM2 and EPROM5 in association with each other. .

  Note that the reset vector, the identification code, and the version numbers a and b are the same as those in the above-described embodiment, but in this embodiment, the version number b of the EPROM 5 has a maximum value (for example, FFFF in hexadecimal). In the case of taking, as in the previous embodiment, all TASKs execute the TASK routine in the EPROM 5, and in other cases, the algorithm is used to compare the version numbers for each TASK. Therefore, as in the previous embodiment, when comparing these version numbers a and b, the version number a of the ROM 2 is, for example, one smaller than the maximum value (for example, FFFE in hexadecimal). Or the version number b may be read to determine whether this is the above maximum value without performing such a comparison.

  When the EPROM version number b is not the maximum value, the TASK1a version number stored in the storage area 502 of the ROM 2 and the TASK1b version number stored in the storage area 512 of the EPROM 5 in FIGS. And the address of TASK1 of the newer version number is registered in RAM3. If the TASK 1a version number is newer, the TASK 1a address corresponding to this is registered in the RAM 3. Here, it is assumed that the TASK1b version number of the EPROM 5 is newer, and the TASK1b address for this is registered in the RAM 3.

  Similarly, the TASK2a version number stored in the storage area 504 of the ROM 2 is compared with the TASK2b version number stored in the storage area 514 of the EPROM 5, and the address of the TASK2 of the newer version number is registered in the RAM 3. If the TASK2b version number is newer, the TASK2b address for this is registered in the RAM 3. Here, it is assumed that the TASK 2a version number of the ROM 2 is newer, and the TASK 2a address for this is registered in the RAM 3.

  As a result, as shown in FIG. 6, the TASK1b address of the EPROM5 is registered in the storage area 60 as the TASK1 address and the TASK2a address of the ROM2 is registered in the storage area 61 as the TASK2 address.

  Therefore, TASK1 executes the TASK1b routine of EPROM5, and TASK2 executes the TASK2a routine of ROM2.

  Of course, when the TASK1a address of ROM2 and the TASK2b address of EPROM5 are registered, the TASK1a routine of ROM2 and the TASK2b routine of EPROM5 are executed.

  In this embodiment, the program and data in the ROM 2 and the program and data in the EPROM 5 can be changed independently as in the previous embodiment, and even if there is such a change, the program in the ROM 2 can be changed. The data and the program and data of the EPROM 5 are organically combined and used.

  In the embodiment of FIG. 5, each of the storage areas 500, 501, 502, 503, 504, 505, 510, 511, 512, 513, 514, 515 has an absolute address value in the absolute address space. A fixed address that is fixedly determined is more effective in system configuration. However, the implementation of the present invention is not limited to only fixed addresses.

  Incidentally, since the access speed of the ROM 2 in the one-chip microcomputer 6 is generally faster than the access speed of the external EPROM 5, it is advantageous to use the ROM 2 in the one-chip microcomputer 6 as a system. FIG. 7 is a diagram showing the information contents of the memory section in still another embodiment of the microcomputer control system according to the present invention which realizes this. FIG. 7 (a) shows the ROM 2 in the one-chip microcomputer 6. FIG. 7 (b) shows the information contents stored in the external EPROM 5, respectively. Also in this embodiment, the hardware configuration is the same as in FIG.

  In this embodiment, as in the embodiment described with reference to FIG. 2, a program or data recorded in either ROM 2 or EPROM 5 is executed according to the comparison result of version numbers a and b. Assuming that some of the subroutines stored in the EPROM 5 are not changed from the corresponding subroutines in the ROM 2, the programs and data stored in the EPROM 5 are stored in the ROM 2. Subroutines that are used can also be used.

  7 (a) and 7 (b), the processing procedure in the external EPROM 5 is now the subroutine 1, the subroutine 2 and the subroutine 3, and the subroutine 2 is not changed, and the subroutine 2a of the ROM 2 is changed. Assuming that the EPROM 5 can be used, for example, the subroutines 1b and 3b are stored in the storage areas 713 and 714 thereof, and the subroutine 2a stored in the ROM 2 is used as the subroutine 2b. In the storage areas 710 to 712 of the EPROM 5, subroutine call instructions that are instructions for calling these subroutines are stored. In the storage areas 710 and 712, subroutines 1b and 3b stored in the EPROM 5 are stored. Subroutine 1b call instruction and subroutine 3b call instruction, which are instructions for calling, are stored. In the storage area 711, a subroutine 2a call instruction for reading out the subroutine 2a stored in the storage area 704 of the ROM 2 is stored.

  In this way, by storing the subroutine call instruction in the EPROM 5, when the EPROM 5 is newer and uses the program or data stored therein, the subroutine 1b call instruction stored in the EPROM 5, The subroutines 1b, 2b and 3b stored in the EPROM 5 are used by the subroutine 2b call instruction and the subroutine 3b call instruction. In the embodiment shown in FIG. Subroutine 2a is executed.

  When the external EPROM 5 is newer, the subroutine address of the ROM 2 is known and may be left as it is. However, as in this embodiment, the addresses of the subroutine 1a, subroutine 2a, and subroutine 3a are replaced with the subroutine 1a address, Needless to say, it is desirable to store the subroutine 2a address and subroutine 3a address in the ROM 2.

  As described above, in this embodiment, the program and data in the ROM 2 and the program and data in the EPROM 5 can be changed independently, and these can be used by organically combining them. In addition, since the EPROM 5 stores only the corrected portion of the program and data in the ROM 2, the storage capacity can be reduced.

In the embodiment of FIG. 7, the storage areas 700, 701, and 702 each have a fixed address in which the absolute value of the address is fixedly determined in the absolute address space. It is effective. However, the implementation of the present invention is not limited to only fixed addresses. (The storage areas 710, 711, and 712 need not be fixed addresses because they are programs that are arbitrarily arranged as necessary.)
FIG. 8 is an embodiment in which storage areas 251, 252, 261, and 262 are added to the embodiment of FIG.

  FIG. 8 (a) shows the information contents stored in the ROM 2 in the one-chip microcomputer 6 in another embodiment of the microcomputer control system according to the present invention, and FIG. 8 (b) shows the information content stored in the external EPROM 5. Each of the stored information contents is shown. The hardware configuration of this embodiment is the same as that shown in FIG.

In FIG. 8A, the ROM 2 has TASK? a address is stored, this TASK? aSK corresponding to a address? a routine is stored in the storage area 252.
In FIG. 8B, the EPROM 5 has a storage area 261 with a TASK? b address is stored, this TASK? TASK for b address? The b routine is stored in the storage area 262.

  TASK? The a routine is TASK having no processing entity, and TASK? The routine b is TASK having a processing entity. When producing ROM2, TASK? a The system is configured in such a way that there is no inconvenience due to the presence or absence of the routine. In this system, the TASK? When the b routine is added, a new TASK? The b routine is executed.

  Like this, TASK? When the b routine is added, an address is registered in the RAM 3 as shown in FIG. That is, a storage area 42 is added to the embodiment of FIG. 4 and TASK? The b address is registered.

  Of course, if there is no need to add a new process, TASK? The b routine may be registered as TASK having no processing entity. TASK? An address (for example, address 0) that cannot be obtained in the system configuration may be set as the b address. When an address that cannot be obtained in the system configuration is set as this address, it is necessary to determine the consistency of the TASK address every time the TASK is used. For example, if the set address is 0, is it 0? Since it is easy to determine whether or not, there is no problem in the system configuration.

  In the embodiment of FIG. 8, the storage areas 251 and 261 added to the embodiment of FIG. 2 are fixed addresses in which the absolute value of the address is fixedly determined in the absolute address space. It is more effective in system configuration. However, the implementation of the present invention is not limited to only fixed addresses.

  FIG. 10 is an embodiment in which storage areas 551, 552, 553, 561, 562, and 563 are added to the embodiment of FIG.

  FIG. 10 (a) shows the information contents stored in the ROM 2 in the one-chip microcomputer 6 in another embodiment of the microcomputer control system according to the present invention, and FIG. 10 (b) shows the information content stored in the external EPROM 5. Each of the stored information contents is shown. The hardware configuration of this embodiment is the same as that shown in FIG.

  In FIG. 10A, the ROM 2 stores TASK? a address is stored, this TASK? aSK corresponding to a address? a routine is stored in the storage area 553. This TASK? Is the version number for routine a TASK? It is stored in the storage area 551 which is the storage area immediately before the storage area 552 in which the a address is stored.

  In FIG. 10B, the EPROM 5 has a storage area 562 with a TASK? b address is stored, this TASK? TASK for b address? The b routine is stored in the storage area 563. This TASK? The version number for routine b is TASK? It is stored in the storage area 561 which is the storage area immediately before the storage area 562 in which the b address is stored.

  TASK? The a routine is TASK having no processing entity, and TASK? The routine b is TASK having a processing entity. When producing ROM2, TASK? a The system is configured in such a way that no inconvenience occurs due to the presence or absence of the routine. a TASK of EPROM5 with a version number newer than the version number? When the b routine is added, a new TASK? The b routine is executed.

  Like this, TASK? When the routine b is added, an address is registered in the RAM 3 as shown in FIG. That is, a storage area 62 is added to the embodiment of FIG. The b address is registered.

  Of course, if there is no need to add a new process, TASK? The b routine may be registered as TASK without a processing entity, or TASK? b Set the version number to the old version number (for example, 0) and set TASK? a routine may be registered. TASK? An address (for example, address 0) that cannot be obtained in the system configuration may be set as the b address. When an address that cannot be obtained in the system configuration is set as this address, it is necessary to determine the consistency of the TASK address every time the TASK is used. For example, if the set address is 0, is it 0? Since it is easy to determine whether or not, there is no problem in the system configuration.

  In the embodiment of FIG. 10, the storage areas 551 and 561 added to the embodiment of FIG. 5 are fixed addresses in which the absolute value of the address is fixedly determined in the absolute address space. It is more effective in system configuration. However, the implementation of the present invention is not limited to only fixed addresses.

8 to 11, processing can be added by the EPROM 5 even after the ROM 2 is produced, and it is possible to cope with an unexpected situation at the time of the ROM 2 production.
FIG. 12 is a diagram showing another registration method for FIG. 4, FIG. 6, FIG. 9 and FIG. A TASK registration table (8 bits in this embodiment) is prepared, and each TASK corresponds to each bit. “0” means TASK stored in the internal ROM 2, and “1” means TASK stored in the external EPROM 5. The most significant bit (bit 7) is a bit indicating the presence of the external EPROM 5, 0 means that the external EPROM 5 does not exist, and 1 means that the external EPROM 5 exists.

  FIG. 12 (a) shows information equivalent to FIG. That is, since the bit (least significant bit 0) corresponding to TASK1 is 1, TASK1b stored in the external EPROM 5 is used, and since the bit (bit 1) corresponding to TASK2 is 0, it is stored in the internal ROM2. It means to use TASK2a.

  Similarly, FIG. 12 (b) shows information equivalent to FIG. In FIG. 12 (a), TASK added to FIG. A bit (bit 2) corresponding to is added. That is, TASK added to FIG. Since the bit (bit 2) corresponding to 1 is 1, TASK? Stored in the external EPROM 5? It means to use b.

  In FIG. 12, if all the bits of the corresponding TASK are all 1, it is needless to say that the information is equivalent to those in FIGS.

  The embodiment of FIG. 12 has an effect that the occupied storage area in the internal RAM 3 can be reduced as compared with the embodiments of FIGS. 4, 6, 9 and 11.

  FIG. 13 is a block diagram showing another embodiment of the present invention, which is an example in which an external device 10 is connected to the embodiment of FIG. In addition, the same thing as FIG. 1 attaches | subjects the same number. However, the address bus and the control bus are omitted. Further, although EPROM is used in FIG. 1, an electrically rewritable flash memory 11 is used in FIG.

  Information from the external device 10 is transmitted to the data bus 8 of the one-chip microcomputer 6 via the interface 12 and stored in the flash memory 11.

  FIG. 14 shows the processing operation stored in the flash memory 11. The same processing contents as those in the flowchart of FIG. 3 are denoted by the same reference numerals.

  Here, processing different from the processing content of FIG. 3 will be described.

  (Step 141) The connection of the external device 10 is confirmed. In an external device that reads an information recording medium such as a CD-ROM, information cannot be read even when the information recording medium is not loaded, so it is determined that the external device is not connected.

  (Step 142) Information (identification information and version information) is read from the external device 10 and stored in the internal RAM 3. However, if the information (identification information and version information is not stored in the flash memory 11), the information is directly stored in the flash memory 11 and the process proceeds to step 146.

  (Step 143) It is determined whether the information stored in the internal RAM 3 is predetermined information (identification information). As the predetermined information, for example, a copyright display recorded in a volume descriptor of a CD-ROM can be used. If it is not predetermined information, the process proceeds to step 147. If it is predetermined information, the version information (version number) stored in the internal RAM 3 and the version information (version number) stored in the flash memory 11 are obtained. The comparison is made (step 144).

  As a result of the comparison in step 142, if the version information stored in the internal RAM 3 is newer, the process proceeds to step 146. If the version information in the flash memory 11 is newer, the process proceeds to step 147 ( Step 146).

  (Step 146) After reading information (identification information and version information) from the internal RAM 3 and storing it in the flash memory 11, the processing program (TASK) whose version has been changed is additionally read from the external device 10 and added to the flash memory 11. Store.

  However, in step 142, since the information (identification information and version information is not stored in the flash memory 11), the version-changed processing program (TASK) is added from the external device 10 when directly stored in the flash memory 11. Only the process of reading and additionally storing in the flash memory 11 is performed.

  (Step 147) The process ends. Thereafter, the TASK address in the external flash memory 11 or the TASK address in the internal ROM 2 is transferred to the internal RAM 3 by the same processing procedure as in FIG. 3 (however, the EPROM in FIG. 3 is replaced with the flash memory). sign up.

  In the present embodiment, as the information recording medium, a pressed CD-ROM disc or DVD-ROM disc, a write-once CD-R disc or DVD-R disc, a rewritable CD-RW disc, a DVD-RAM disc, or the like. Compared with the case of using EPROM, the additional work accompanying the version change is simplified. In addition, as an external device, an information reproducing apparatus that calls information from an information recording medium such as a CD-ROM is assumed, but even if an apparatus that receives and reproduces information transmitted by broadcasting or communication is used, It is clear that there is a category.

  In the embodiment shown in FIG. 13, the system information can be constructed by storing the control program or data only in the flash memory 11 without storing the version information, control program or data in the internal ROM 2.

  In this case, the relationship between the internal ROM 2 and the EPROM 5 in FIG. 3 can be considered similarly to the relationship between the flash memory 11 and the external device 10, respectively. Therefore, as a result, the system uses the control program or data stored in the flash memory 11.

  FIG. 15 shows an embodiment in which a DRAM 13 is added to the embodiment of FIG.

  In the embodiment of FIG. 15, the control program or data stored in the flash memory 11 is moved to the DRAM 13 and the control program or data stored in the DRAM 13 is used. In this embodiment, the control program or data stored in the flash memory 11 is an encrypted control program or data, and the DRAM 13 stores the decrypted control program or data.

When the version information is also encrypted, the version information is decrypted only when it is necessary to compare the version information, and it is determined whether or not the version information should be stored in the flash memory 11.
In the embodiment of FIG. 15, after the version information comparison, the latest version of the control program or data is stored in the flash memory 11 while being encrypted.

  The actual processing flow will be described with reference to the flowchart of FIG.

  (Step 161) The encrypted information (identification information, version information, control program, data, etc.) stored in the external flash memory 11 is read out to the internal RAM 3.

  (Step 162) The read encrypted information is decrypted and stored in the external DRAM 13.

  (Step 163) The process ends. Thereafter, the TASK address in the external DRAM 13 or the TASK address in the internal ROM 2 is registered in the internal RAM 3 by the same processing procedure as in FIG. 3 (however, EPROM in FIG. 3 is replaced with DRAM).

  The amount of data read from the flash memory 11 at step 161 is limited by the buffer capacity of the internal RAM 3, but if the encryption can be completed within the buffer capacity, step 161 and step 162 are performed several times. It can be solved by repeatedly executing.

  By using the encrypted information, it becomes impossible to know the contents of the flash memory 11 from the outside. Further, the decrypted information stored in the DRAM 13 requires a refresh process peculiar to the DRAM and disappears when the power is turned off. To do. Further, the processing program for decrypting the encryption is stored in the internal ROM 2 and cannot be easily read out to the outside, so that the system is configured in consideration of security. However, the processing of FIG. 16 is required every time the power is turned on.

  In the embodiment of FIG. 15, the system information can be constructed by storing the control program or data only in the DRAM 13 without storing the version information, control program or data in the internal ROM 2.

  In this case, the relationship between the internal ROM 2 and the EPROM 5 in FIG. 3 can be considered similarly to the relationship between the DRAM 13 and the external device 10, respectively. Therefore, as a result, the system uses the control program or data stored in the DRAM 13.

  Although the version information is the same (the essence of the control program or data has not changed), the contents can be made different depending on the revision information (revision number). Table 1 is an embodiment showing a specific example.

  Table 1 shows an embodiment in which the language used is different depending on the revision number.

  When all the data corresponding to each revision number is prepared in the EPROM 5, the flash memory 11 or the DRAM 13 and the version number is the same and only the revision number is different, the control stored in the EPROM 5, the flash memory 11 or the DRAM 13 is stored. You only need to change the revision number of the program or data.

  However, it is necessary to incorporate an algorithm for changing the language to be used according to the revision number into the control program.

  In Table 1, the revision number is used to identify the language used, but the identification of the country of use (Japan, USA, China, etc.), the identification of the function used (function A, function A + B, etc.), Identification (for A company, B company, etc.) can also be identified using the revision number.

  When each user uses the above-described embodiment for each purpose, the one-chip microcomputer 6 is shared (that is, the program and data stored in the ROM 2 are shared), and the external EPROM 5 and the flash are used. The memory 11 or the DRAM 13 can individually correspond to each user.

  In this case, as shown in FIG. 5 and FIG. 10, only TASK that should be individually handled should be listed in the EPROM 5, the flash memory 11 or the DRAM 13, or should be individually handled as shown in FIG. Only the subroutine may be placed in the EPROM 5, the flash memory 11 or the DRAM 13.

  Further, in the above embodiment, the update of the processing program (TASK, subroutine) in the ROM 2 in the one-chip microcomputer 6 and the external EPROM 5 has been described. It is obvious that the flash memory 11 or the DRAM 13 can cope.

  Further, in the above embodiment, a mask ROM that cannot be rewritten is used as the ROM 2, but a memory such as a rewritable EPROM or flash memory may be used, and a rewritable EPROM may be used as an external memory. Although the memory, the flash memory 11 or the DRAM 13 is used, a mask ROM that cannot be rewritten may be used.

  Furthermore, in the above embodiment, the address of the program (TASK, subroutine) to be executed is registered in the RAM 2 in the one-chip microcomputer 6, but the information content to be registered is not only the address but also the program to be executed (TASK). , Subroutine) The main body may be registered. Further, RAM, flash memory, DRAM, etc. are added outside the one-chip microcomputer 6, and the address of the program (TASK, subroutine) to be executed and the program (TASK, subroutine) body to be executed are registered there. You can also.

  In the above description of the embodiment of the present invention, version information is used. However, the present invention is not limited to version information, and comparison can also be made using program or data information. For example, information such as a comment sentence, copyright notice, program size, data size, program start address, and data start address in the program or data can be used.

  As described above, according to the present invention, the ROM version information in one chip is compared with the version number in the external EPROM, flash memory, or DRAM, so that a new version of a program (TASK, subroutine) is always obtained. It can be executed and new versions of update data can be used. In addition, each user can be handled individually.

  In addition, since only the program or data to be updated or changed is added to the outside, the program or data to be added can be minimized.

  In addition to version information, version information can be made unnecessary by making comparisons using information in a program or data.

FIG. 1 is a hardware block diagram showing an embodiment of a microcomputer control system according to the present invention. FIG. 2 is a diagram showing information contents stored in the ROM and EPROM in FIG. FIG. 3 is a flowchart showing the processing operation at power-on or reset in one embodiment of the microcomputer control system according to the present invention using the information contents shown in FIG. FIG. 4 is a diagram showing a specific example of information contents stored in the RAM in FIG. 1 by the processing operation shown in FIG. FIG. 5 is a diagram showing information contents stored in the ROM and the EPROM in FIG. 1 in another embodiment of the microcomputer control system according to the present invention. FIG. 6 is a diagram showing a specific example of information contents stored in the RAM in FIG. 1 in another embodiment of the microcomputer control system according to the present invention. FIG. 7 is a diagram showing information contents stored in the ROM and the EPROM in FIG. 1 in another embodiment of the microcomputer control system according to the present invention. FIG. 8 is a diagram showing information contents stored in the ROM and the EPROM in FIG. 1 in another embodiment of the microcomputer control system according to the present invention. FIG. 9 is a diagram showing a specific example of information contents stored in the RAM in FIG. 1 in another embodiment of the microcomputer control system according to the present invention. FIG. 10 is a diagram showing information contents stored in the ROM and the EPROM in FIG. 1 in another embodiment of the microcomputer control system according to the present invention. FIG. 11 is a diagram showing a specific example of information contents stored in the RAM in FIG. 1 in another embodiment of the microcomputer control system according to the present invention. FIG. 12 is a diagram showing a specific example of information contents stored in the RAM in FIG. 1 in another embodiment of the microcomputer control system according to the present invention. FIG. 13 is a block diagram showing another embodiment of the present invention, and is a block diagram showing an embodiment in which an external device 10 is connected to the embodiment of FIG. FIG. 14 is a flowchart showing the processing operation stored in the flash memory 11. FIG. 15 is a block diagram showing an embodiment in which a DRAM 13 is added to the embodiment of FIG. FIG. 16 is a flowchart showing a processing procedure of the embodiment of FIG.

Explanation of symbols

1 CPU part 2 ROM part 3 RAM part 4 I / O part 5 EPROM part 6 One-chip microcomputer

Claims (12)

In a microcomputer control system in which a program built in a microcomputer or the like can be modified equivalently from the outside of the microcomputer,
Version information is added to the entire program built in the microcomputer or the like and the entire program to be corrected prepared outside the microcomputer, and the version information is used to build in the microcomputer or the like. A microcomputer control system for determining whether to use a program to be corrected or a program to be corrected prepared outside the microcomputer. In a microcomputer control system in which data built in a microcomputer or the like can be corrected equivalently from the outside of the microcomputer,
Version information is added to the entire data stored in the microcomputer or the like and the entire data to be corrected prepared outside the microcomputer, and the version information is used to store the data in the microcomputer or the like. A microcomputer control system for determining whether to use data to be corrected or to use data to be corrected prepared outside the microcomputer. The microcomputer control system according to claim 1, wherein
Version information is added to each program built in the microcomputer or the like and each program to be corrected prepared outside the microcomputer, and built into the microcomputer or the like using the version information. A microcomputer control system for determining whether to use a stored program or a program to be corrected prepared outside the microcomputer. The microcomputer control system according to claim 2,
Version information is added to individual data stored in the microcomputer or the like and data to be corrected prepared outside the microcomputer, and the microcomputer is built in the microcomputer or the like using the version information. A microcomputer control system for determining whether to use the data to be corrected or to use the data to be corrected prepared outside the microcomputer. In the microcomputer control system according to claim 1, 2, 3, or 4,
Identification information is added to a storage unit that stores a program or data to be corrected prepared outside the microcomputer, and a program or data to be corrected that matches the microcomputer control system is obtained using the identification information. A microcomputer control system for determining whether or not a storage unit is stored. In the microcomputer control system according to claim 1, 2, 3, or 4,
A microcomputer control system, wherein a storage area for storing the version number is a fixed address. The microcomputer control system according to claim 5, wherein
A microcomputer control system, wherein a storage area for storing the identification information is a fixed address. In the microcomputer control system according to claim 1, 2, 3, 4, 5, 6 or 7,
A microcomputer control system characterized in that some programs or data incorporated in the microcomputer or the like are constituted by intangible programs or data. The microcomputer control system according to claim 1, 2, 3, 4, 5, 6, 7 or 8.
A microcomputer control system, wherein an external device is added outside the microcomputer, and a program or data to be corrected is supplied from the external device. The microcomputer control system according to any one of claims 1, 2, 3, 4, 5, 6, 7, 8, or 9.
A microcomputer control system, wherein a program or data to be modified is encrypted and stored in a storage unit connected to the outside of the microcomputer. The microcomputer control system according to claim 9.
A microcomputer control system characterized in that an information recording medium reproducing apparatus is used as the external device, and a program or data to be corrected is recorded on an information recording medium stored in the information recording medium reproducing apparatus. 12. The microcomputer control system according to claim 11, wherein an optical disk is adopted as the information recording medium.

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