JP2006310510A - Compound semiconductor switch circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor switch circuit device in which leakage of high frequency signal is suppressed and degradation in strain characteristics is prevented. <P>SOLUTION: One end of the interdigital teeth of two gate electrodes is connected with a gate connection metal layer on a nitride film. The gate connection metal layer is arranged between a first source electrode and a second source electrode and a drain interconnect line or between a first drain electrode and a second drain electrode and a source interconnect line. Since the gate electrode of the off side FET has GND potential as high frequency signal, leakage of high frequency signal is prevented between drain and source. The gate connection metal layer and the two gate electrodes (interdigital teeth) surround the interdigital teeth of one source electrode (gate electrode) thus preventing leakage of high frequency signal. Since resist removing liquid enters between adjacent gate electrodes sufficiently during formation of the gate electrode, lift-off is facilitated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a compound semiconductor switch circuit device, and more particularly to a compound semiconductor switch circuit device that suppresses leakage of high-frequency signals and prevents deterioration of distortion characteristics.

  In mobile communication devices such as cellular phones, microwaves in the GHz band are often used, and switching elements for switching these high-frequency signals are used in antenna switching circuits and transmission / reception switching circuits. There are many cases. As the element, a field effect transistor (hereinafter referred to as FET) using gallium arsenide (GaAs) is often used because it handles high frequency, and accordingly, the monolithic microwave integration in which the switch circuit itself is integrated. A circuit (MMIC) is being developed.

  FIG. 8 shows a switch MMIC composed of two switching elements in which FETs are connected in a plurality of stages as an example of a conventional compound semiconductor chip.

  Two FET groups serving as the first and second switching elements SW1 and SW2 are arranged on the compound semiconductor substrate. Each FET group consists of three FETs connected in series. A first control resistor CR1 and a second control resistor CR2 are connected to the six gate electrodes constituting each FET group. Further, electrode pads I, O1, and O2 connected to the common input terminal IN and the output terminals OUT1 and OUT2, and two electrode pads C1 and C2 connected to the control terminals Ctl1 and Ctl2, respectively, are provided around the substrate. .

  The wiring of the second metal layer indicated by the dotted line is the gate metal layer 220 forming the gate electrode of each FET, and the wiring of the third metal layer indicated by the solid line is the connection of each element and the pad The wiring metal layer 230 is formed. The ohmic metal layer which is the first metal layer and is in ohmic contact with the substrate forms the source electrode and drain electrode of each FET, and is not shown in FIG. 8 because it overlaps with the wiring metal layer. .

  The FET 1-1 of the first switching element SW1 is a source electrode 215 (or drain electrode) connected to the common input terminal pad I by three comb-shaped wiring metal layers 230 extending from the upper side, and an ohmic metal layer below this A source electrode (or a drain electrode) formed in (1) is provided. Each source electrode 215 is connected by a source wiring 231 made of a wiring metal layer 230.

  Further, the three comb-like wiring metal layers 230 extending from the lower side are the drain electrodes 216 (or source electrodes) of the FET 1-1, and the drain electrodes (or source electrodes) formed of the ohmic metal layers are below this. Provided. Each drain electrode 216 is connected by a drain wiring 232 made of a wiring metal layer 230.

  The source electrode 215 and the drain electrode 216 are arranged in a shape in which comb teeth are engaged, and the gate electrode 217 formed of the gate metal layer 220 is arranged in the shape of five comb teeth. The gate electrodes 217 are connected to each other by a gate wiring 221 outside the operation region 300 indicated by a one-dot chain line (see, for example, Japanese Patent Application No. 2004-371831).

  In the above switch MMIC, there is a problem that a high frequency analog signal (hereinafter referred to as a high frequency signal) leaks between the source electrode and the drain electrode in the vicinity of each other, and this causes deterioration in electrical characteristics. .

  Specifically, when the first switching element SW1 is an on-side switching element, a high-frequency signal passes from the common input terminal pad I through the channel layer of each FET as indicated by an arrow and propagates to the first output terminal pad O1. To do.

  In the second switching element SW2 serving as the off-side switching element, the high frequency signal does not pass through the channel layer of the FET. That is, in the operation region 300 indicated by the alternate long and short dash line, a high frequency signal does not leak between adjacent source and drain electrodes. Further, the X region surrounded by the two-dot chain line is closest to the common input terminal pad I and is exposed to a high-power high-frequency signal. However, high-frequency signal leakage does not occur even in the X region.

  Therefore, in the signal path between the common input terminal IN on the ON side and the first output terminal OUT1, the linearity characteristic of the output signal can ensure a designed value.

  However, it has been found that high-frequency signal leakage occurs outside the channel layer of the FET at locations where the source electrode and drain electrode of the high power switch circuit device in which FETs are connected in multiple stages are adjacent and directly facing each other.

  That is, high-frequency signal leakage occurs between the source electrode and the drain electrode (specifically, between the source electrode 215 and the drain wiring 232) in the solid Y region where the source electrode and the drain electrode are adjacent and directly opposed to each other. For this reason, the distortion level of the output signal cannot be ensured as designed, and there is a problem that the harmonic level is too high.

  FIG. 9 shows another pattern of the conventional switch MMIC shown in FIG. In the switch MMIC of FIG. 8, the gate wiring 221 is arranged on the common input terminal pad I side with respect to the comb teeth of the gate electrode 217, and the tips of the comb teeth of the gate electrode 217 are the first output terminal pad O1 and the second output terminal. Arranged on the pad O2 side.

  On the other hand, in the switch MMIC of FIG. 9, the gate wiring 221 is arranged on the first output terminal pad O1 and second output terminal pad O2 side with respect to the comb teeth of the gate electrode 217, and the tips of the comb teeth of the gate electrode 217 are common. Arranged on the input terminal pad I side. Since other components are the same, description thereof is omitted.

In this case, since the X ′ region closest to the common input terminal pad I is exposed to a high-power high-frequency signal, the source electrode and the drain electrode are adjacent and directly opposed to each other, so that the X ′ region is large. It was found that high frequency signal leakage occurred. Specifically, in the signal path between the ON-side common input terminal IN and the first output terminal OUT1, only Pin _0.1 dB can be ensured by a value lower than the design by several dB. In addition, in the Y region, a high frequency signal leaks between the source electrode 215 and the drain electrode 216, and there is a problem in that the distortion characteristics are poor.

  The present invention has been made in view of the various circumstances described above, and includes a switching element in which a comb-like source electrode, gate electrode, and drain electrode are provided on an operation region of a compound semiconductor substrate, and the substrate surface outside the operation region. An insulating film provided on the switching element; a first RF port connected to a source electrode or a drain electrode of the switching element; a second RF port connected to a drain electrode or a source electrode of the switching element; and a gate electrode of the switching element. A control terminal, wherein the gate electrode has one end of each comb tooth extending outside the operation region, and the one end of one comb tooth and one end of another adjacent comb tooth are insulated from each other. This is solved by connecting to a metal layer disposed on the film.

According to the present invention, the following effects can be obtained.

  First, one end of the comb teeth of adjacent gate electrodes extends outside the operation region and is connected by a metal layer, and the metal layers are connected between the tips of the comb teeth of all the source electrodes and the drain wiring and of all the drain electrodes. It arrange | positions between the front-end | tip of a comb tooth-source wiring.

  Thereby, the high frequency current flowing through the substrate can be blocked by the metal layer between the source electrode and the drain wiring and between the drain electrode and the source wiring. That is, in the switch MMIC, all of the conventional high-frequency signal leakage paths between the source electrode and the drain electrode can be blocked by the metal layer, the gate electrode, or the gate wiring.

  In the off-side FET, the gate electrode, the gate wiring, and the metal layer are at a GND potential as a high-frequency signal. Therefore, the GND potential is arranged between the potentials of the source electrode and the drain electrode in all leak paths of the conventional high-frequency signal of the off-side FET. That is, since the electric field of the direct high-frequency signal between the source electrode and the drain electrode is greatly weakened by arranging the gate electrode, the gate wiring, and the metal layer of the GND potential as the high-frequency signal between the source electrode and the drain electrode, High-frequency signal leakage between the source electrode and the drain electrode can be prevented.

  Since the gate electrode is formed by lift-off of the gate metal layer, an accurate pattern cannot be formed if the penetration of the resist removal liquid is insufficient.

  In the present embodiment, since the gate electrode is formed in a comb-like pattern, the resist removal liquid penetrates between the gate electrodes, and lift-off is facilitated. Then, after forming the gate electrode pattern, a metal layer is formed, and the tip of the source or drain electrode is surrounded by the GND potential of the high-frequency signal. Therefore, the lift-off is easy and the leakage of the high frequency signal can be cut off.

  An embodiment of the present invention will be described in detail with reference to FIGS.

  First, FIG. 1 is a circuit diagram showing an example of a DPDT (Double Pole Double Throw) switch MMIC composed of four switching elements in which FETs are connected in a plurality of stages.

  The DPDT is a switch MMIC used for a CDMA mobile phone or the like, and includes first to fourth switching elements SW1, SW2, SW3, SW4, two first RF ports (first common input terminal IN1, second common input terminal IN2). And two second RF ports (first output terminal OUT1, second output terminal OUT2). The SPDT switch composed of the first and second switching elements SW1 and SW2 and the other SPDT switch composed of the third and fourth switching elements SW3 and SW4 are connected to each other via the second RF port.

  Each switching element SW1, SW2, SW3, SW4 is a group of FETs in which FETs are connected in series in three stages. For example, in the first switching element SW1, FET1-1, FET1-2, and FET1-3 are connected in series. In the second switching element SW2, FET2-1, FET2-2, and FET2-3 are connected in series. The third switching element SW3 is connected to FET3-1, FET3-2, and FET3-3, and the fourth switching element SW4 is connected to FET4-1, FET4-2, and FET4-3 in series.

  The drain electrode (or source electrode) of one end (FET1-3) of the first switching element SW1 is connected to the drain electrode (or source electrode) of one end (FET3-3) of the third switching element SW3, and the second switching element The drain electrode (or source electrode) of one end (FET2-3) of SW2 is connected to the drain electrode (or source electrode) of one end (FET4-3) of the fourth switching element SW4.

  The source electrodes (or drain electrodes) of the other ends (FET1-1, FET2-1) of the first and second switching elements SW1, SW2 are connected to the first common input terminal IN1, and the third and fourth switching elements SW3, The source electrode (or drain electrode) of the other end of SW4 (FET3-1, FET4-1) is connected to the second common input terminal IN2.

  The first output terminal OUT1 is common to the first and third switching elements SW1 and SW3, and the second output terminal OUT2 is common to the second and fourth switching elements SW2 and SW4. In the switch MMIC, the source electrode and the drain electrode are equivalent. Therefore, hereinafter, the source electrode and the drain electrode are the same even if they are interchanged.

  The control resistors CR are connected to the gate electrodes of the FETs of the first switching element SW1 and the fourth switching element SW4, respectively, and are connected to the control terminal Ctl via the logic circuit L indicated by the broken line. The gate electrodes of the second switching element SW2 and the third switching element SW3 are also connected to the point CP of the logic circuit L through the control resistor CR.

  The control resistor CR is disposed for the purpose of preventing leakage of a high-frequency signal through the gate electrode with respect to the DC potential of the control terminal Ctl serving as AC ground and the DC potential of the point CP of the logic circuit L. The resistance value of the control resistor CR is about 5 KΩ to 10 KΩ, respectively.

  The switch MMIC of this embodiment includes a logic circuit L. The logic circuit L is an inverter circuit, and has the following configuration.

The drain electrode of the enhancement type (E type) FET (E-FET) whose source electrode is connected to the GND terminal is the point CP, one end of the load resistor Rl is connected to the point CP, and the other end of the load resistor Rl is the power source Connect to terminal V _DD . The gate electrode of the E-FET is connected to the control terminal Ctl via the input resistance Ri.

  A capacitor Ci and a capacitor Cr are connected between the control terminal Ctl and the GND terminal and between the point CP and the GND terminal for noise absorption and oscillation prevention, respectively. The input resistor Ri is disposed for preventing electrostatic breakdown, absorbing noise, and preventing oscillation.

  The operation of the logic circuit L (inverter circuit) is as follows. The logic signal applied to the control terminal Ctl is inverted by the inverter, and an inverted signal of the control signal is generated at the point CP. That is, when the control terminal Ctl is 3V, the point CP is 0V, and when the control terminal Ctl is 0V, the point CP is 3V.

  The circuit operation of the DPDT switch MMIC in FIG. 1 is as follows. When 3V is applied to the control terminal Ctl, the first switching element SW1 and the fourth switching element SW4 in which the signal of the control terminal Ctl is directly input to the gate electrode are turned on. As a result, the first common input terminal IN1 and the first output terminal OUT1 and the second common input terminal IN2 and the second output terminal OUT2 become conductive, and a signal path is formed.

  On the other hand, the signal at the point CP, that is, the second switching element SW2 and the third switching element SW3 to which the inverted signal 0V is input to the gate electrode are turned off. Accordingly, the first common input terminal IN1 and the second output terminal OUT2 and the second common input terminal IN2 and the first output terminal OUT1 are blocked. When 0V is applied to the control terminal Ctl, the reverse operation is performed.

  In such DPDT, the first RF port and the second RF port can be used interchangeably. In this case, the high-frequency signal path from the common input terminal to the output terminal is reversed.

  FIG. 2 is a plan view in which the above-mentioned DPDT is integrated on one chip of a compound semiconductor substrate. The pattern arrangement of each element constituting the circuit is substantially the same as the arrangement of the circuit diagram of FIG. The FET may be any of MESFET (Metal Semiconductor Field Effect Transistor), GaAs JFET (Junction FET), and HEMT (High Electron Mobility Transistor), but here, HEMT is mainly used for explanation.

  The substrate structure of the HEMT is obtained by stacking a buffer layer, an electron supply layer, a channel (electron travel) layer, a cap layer, etc. on a semi-insulating GaAs substrate, for example. In the HEMT, an isolation region 50 reaching the buffer layer is used to form impurity regions such as an operation region 100, a control resistor CR, a load resistor Rl, and an input resistor Ri.

  The first switching element SW1 to the fourth switching element SW4 are each a group of FETs in which three FETs are connected in series. A control resistor CR is connected to each of the gate electrodes of the switching elements SW1 to SW4. The first common input terminal IN1, the second common input terminal IN2, the first output terminal OUT1, the first common input terminal pad I1, the second common input terminal pad I2, and the first output terminal pad connected to the second output terminal OUT2. O1 and a second output terminal pad O2 are provided around the substrate. As shown in FIG. 1, the logic circuit L surrounded by a broken line includes E-FETs, pads V, G, C, load resistors R1, input resistors Ri, capacitors Cr, Ci, and the like corresponding to the terminals. The details of the logic circuit L are not described here.

  Since each switching element has the same configuration, the first switching element SW1 will be described below.

  Each of FET1-1, FET1-2, and FET1-3 is a first metal electrode and a first drain electrode by an ohmic metal layer (AuGe / Ni / Au) that is in ohmic contact with the substrate. Is formed. In FIG. 2, the ohmic metal layer is not shown because it overlaps the wiring metal layer 30.

  The second metal layer is a gate metal layer (for example, Pt / Mo) 20 and forms the gate electrode G. The gate electrode G has a comb shape, and each comb tooth (hereinafter referred to as a gate electrode 17) of the gate electrode G is connected by a gate wiring 21. The gate wiring 21 is also formed by the gate metal layer 20, that is, the gate electrode 17 and the gate wiring 21 are continuous.

  The third metal layer is a wiring metal layer (Ti / Pt / Au) 30 and forms a second source electrode S and a second drain electrode D overlapping the ohmic metal layer. The second source electrode S has a comb shape, and each comb tooth (hereinafter, second source electrode 15) of the second source electrode S is connected by the source wiring 31. The source wiring 31 is also formed by the wiring metal layer 30, that is, the second source electrode 15 and the source wiring 31 are continuous.

  The second drain electrode D has a comb shape, and each comb tooth (hereinafter, second drain electrode 16) of the second drain electrode D is connected by the drain wiring 32. The drain wiring 32 is also formed by the wiring metal layer 30, that is, the second drain electrode 16 and the drain wiring 32 are continuous. The wiring metal layer 30 also forms pads.

  In the operation region 100 indicated by the alternate long and short dash line, the FET 1-1 has three wiring metal layers 30 extending from the left side as the second source electrode 15 connected to the first common input terminal pad I1, and below this is an ohmic metal layer. There is a first source electrode formed. Further, the three wiring metal layers 30 extending from the right side are the second drain electrodes 16 of the FET 1-1, and the first drain electrode is below this. These electrodes are arranged in a shape in which comb teeth are engaged, and five gate electrodes 17 are arranged therebetween.

  In the FET 1-2, the three second drain electrodes 16 extending from the left side are connected to the second drain electrode 16 of the FET 1-1. Here, since this electrode is only a high-frequency signal passing point and generally does not need to be led to the outside, no pad is provided. The four second source electrodes 15 extending from the right side are connected to the second source electrode 15 of the FET 1-3. Similarly, this electrode is merely a high-frequency signal passing point and generally does not need to be led out, so no pad is provided. There is an ohmic metal layer under both electrodes. These are arranged in a shape in which comb teeth are engaged, and the gate electrode 17 is arranged in the form of six combs therebetween.

  A switch circuit device in which FETs are connected in series in multiple stages is a high output switch circuit device because it can withstand a larger voltage amplitude when the FET group is OFF, as compared with a switch circuit device having one FET. At that time, there is no need to provide a pad because the source electrode or drain electrode of the FET that becomes a connection portion when the FETs are connected in series does not generally need to be led out to the outside.

  In the FET 1-3, the three wiring metal layers 30 extending from the left side are the second source electrodes 15, and the first source electrode is below this. Further, the four comb-like wiring metal layers 30 extending from the right side are the second drain electrodes 16 connected to the first output terminal pads O1, and the first drain electrodes are below them. These two electrodes are arranged in a shape in which comb teeth are engaged, and six gate electrodes 17 are arranged therebetween. The gate wiring 20 is connected to the control terminal pad C through the control resistor CR.

  The control resistor CR is constituted by the impurity region separated by the insulating region 50 as described above, and is a high resistance in this embodiment. The high resistance body is formed by removing the cap layer having the HEMT structure and using only the lower semiconductor layer having a high sheet resistance as a resistance layer. The control resistor CR needs to have a high resistance value in order to prevent leakage of high-frequency signals. However, the resistance value can be increased over a short distance by using a high resistance body. On the other hand, the load resistance Rl and the input resistance Ri are constituted by impurity regions in which the cap layer of the HEMT structure is not removed in order to obtain a highly accurate resistance value.

  Further, a peripheral impurity region 51 is disposed around each of the pads I1, I2, O1, and O2 to prevent leakage of high frequency signals and improve isolation. Similarly, peripheral impurity regions 51 are formed between each pad and each FET, between each pad and source (drain) wiring, and between each resistance and resistance.

  Further, the peripheral impurity region 51 is also arranged between the first switching element SW1 and the second switching element SW2 and the logic circuit L to improve isolation. These peripheral impurity regions 51 are also separated by the insulating region 50. The peripheral impurity region 51 is connected to a metal layer such as an adjacent pad in a direct current or is at a floating potential.

  The wiring metal layer includes the wiring metal layer 30 as the first layer and the second wiring metal layer (Ti / Pt / Au) 40 indicated by hatching. The second source electrode S and the second drain electrode D are formed by only the first-layer wiring metal 30, but each pad is formed by stacking two layers of the wiring metal layers 30 and 40. Further, the wiring metal layers 30 and 40 also form a wiring having a desired pattern for connecting the first switching element SW1 to the fourth switching element SW4 and the logic circuit L.

  FIG. 3 is a cross-sectional view taken along the line aa in FIG. 2 and shows a set of source electrode, gate electrode, and drain electrode.

  The substrate is formed by laminating a non-doped buffer layer 132 on a semi-insulating GaAs substrate 131. On the buffer layer 132, an n + type AlGaAs layer 133 serving as an electron supply layer, a non-doped InGaAs layer 135 serving as a channel (electron transit) layer, An n + type AlGaAs layer 133 serving as an electron supply layer is laminated. A spacer layer 134 is disposed between the electron supply layer 133 and the channel layer 135.

The buffer layer 132 is a high-resistance layer to which no impurity is added, and its film thickness is about several thousand Å. On the electron supply layer 133, a non-doped AlGaAs layer serving as the barrier layer 136 is stacked to ensure a predetermined breakdown voltage and pinch-off voltage. Further, an n + type GaAs layer 137 serving as a cap layer is laminated on the uppermost layer. A high concentration impurity is added to the cap layer 137, and the impurity concentration is about 1 to 5 × 10 ¹⁸ cm ⁻³ .

For the electron supply layer 133, the barrier layer 136, and the spacer layer 134, a material having a band gap larger than that of the channel layer 135 is used. Further, an n-type impurity (for example, Si) is added to the electron supply layer 133 at about 2 to 4 × 10 ¹⁸ cm ⁻³ .

The HEMT operating region 100 is formed by isolation by an insulating region 50 reaching the buffer layer 132. The HEMT epitaxial structure includes a cap layer 137. Since the impurity concentration of the cap layer 137 is as high as about 1 to 5 × 10 ¹⁸ cm ⁻³ , it can be said that the region where the cap layer 137 is disposed is functionally a high concentration impurity region.

  Hereinafter, the HEMT operation region 100 is separated by the insulating region 50, and the first source electrode 13, the second source electrode 15, the first drain electrode 14, the second drain electrode 16, and the gate electrode 17 of the HEMT are disposed. A semiconductor layer in a certain region. That is, the total region including all semiconductor layers constituting the HEMT such as the electron supply layer 133, the channel (electron transit) layer 135, the spacer layer 134, the barrier layer 136, and the cap layer 137 is defined as the operation region 100.

  The insulating region 50 is not electrically completely insulated, but is a region where carrier traps are provided in the epitaxial layer by ion implantation of impurities (B +). In other words, impurities exist in the insulating region 50 as an epitaxial layer, but are inactivated by impurity (B +) implantation for insulation. In the case where the FET is a GaAs MESFET, the insulating region 50 corresponds to a part of a semi-insulating substrate in which no impurity region is formed.

  In the operation region 100, as shown in the drawing, the source region 137s and the drain region 137d are provided by removing the cap layer 137 to which the high concentration impurity is added. A first source electrode 13 and a first drain electrode 14 formed of an ohmic metal layer 10 are connected to the source region 137s and the drain region 137d, and a second source electrode 15 and a second drain are formed on the upper layer by a wiring metal layer 30. An electrode 16 is formed.

  Further, a part of the cap layer 137 in the operation region 100 is removed by etching, the non-doped AlGaAs layer 136 is exposed, and the gate metal layer 20 is Schottky connected to form the gate electrode 17. Although illustration is omitted here, the gate metal layer 20 is similarly Schottky connected to the non-doped AlGaAs layer 136 in a predetermined pattern.

  FIG. 4 is an enlarged plan view of the operation region 100 of the FET 1-1 of FIG.

  A first source electrode 13 and a first drain electrode 14 are disposed on the operation region 100 and are in contact with a source region and a drain region (not shown here), respectively. In addition, a second source electrode 15 and a second drain electrode 16 are disposed so as to overlap with them. The second source electrode 15 and the second drain electrode 16 are connected to the source wiring 31 and the drain wiring 32, respectively.

  Each gate electrode 17 is formed to have a uniform width and has one end (tip) extending outside the operation region 100. Then, the tip of another gate electrode adjacent to one gate electrode 17 is connected by a gate connection metal layer 18. The gate connection metal layer 18 connects two adjacent gate electrodes 17, and the adjacent gate connection metal layers 18 are not continuous. As will be described later, the gate connection metal layer 18 is provided with a contact hole CH in a nitride film on the gate electrode 17 provided on the substrate surface outside the operation region 100, and is in contact with the gate electrode 17 through the contact hole CH.

  Further, the other end of one gate electrode 17 is connected to the other end of the other gate electrode 17 by a gate wiring 21, and each comb tooth is bundled.

  Here, the gate connection metal layer 18, a part of the tip of the gate electrode 17, and the tips of the first drain electrode 14 and the second drain electrode 16 are also arranged outside the operation region 100. Although one ends (tips) of the gate wiring 21, the first source electrode 13, and the second source electrode 15 are disposed in the operation region 100, they may be disposed outside the operation region 100.

  In the FET 1-1, one end (tip) of the first source electrode 13 and the second source electrode 15 is disposed in the vicinity of the gate wiring 21. The other end of the second source electrode 15 is connected to the other end of the other second source electrode 15 by a source wiring 31. One end (tip) of the first drain electrode 14 and the second drain electrode 16 is disposed in the vicinity of the gate connection metal layer 18. The other end of the second drain electrode 16 is connected to the other end of the other second drain electrode 16 by a drain wiring 32. One end (tip) of the first source electrode 13 and the second source electrode 15 and the drain wiring 32 are close to each other, and one end (tip) of the first drain electrode 14 and the second drain electrode 16 and the source wiring 31 are close to each other.

  That is, the gate connection metal layer 18 is disposed in the vicinity of the tips of the first drain electrode 14 and the second drain electrode 16 of the FET 1-1. The gate connection metal layer 18 is disposed along the width of the first drain electrode 14 and the second drain electrode 16. The extending direction is a direction perpendicular to the extending direction of the comb teeth of the first drain electrode 14 and the second drain electrode 16 and the gate electrode 17.

  Accordingly, one second drain electrode 16 (comb teeth) is surrounded by two adjacent gate electrodes 17 and the gate connection metal layer 18. The gate connection metal layer 18 is disposed between the tips of the first drain electrode 14 and the second drain electrode 16 and the source wiring 31.

  In the FET 1-2, the first source electrode 13, the second source electrode 15, the first drain electrode 14, and the second drain electrode 16 are opposite to the FET 1-1. That is, in the FET 1-2, the gate connection metal layer 18 is disposed in the vicinity along the tips of the first source electrode 13 and the second source electrode 15. The gate connection metal layer 18 connects the tips of two gate electrodes 17 adjacent to the first source electrode 13 and the second source electrode 15. One second source electrode 15 (comb teeth) is surrounded by two adjacent gate electrodes 17 and a gate connection metal layer 18. The gate connection metal layer 18 is disposed between the first source electrode 13 and the second source electrode 15 and the drain wiring 32. The tips of the first drain electrode 14 and the second drain electrode 16 are disposed in the vicinity of the gate wiring 21.

  The FET1-3 is the same as the FET1-1. Here, the drains of the FET 1-1 and the FET 1-2 are connected and the drain wiring 32 is shared, and the sources of the FET 1-2 and the FET 1-3 are connected and the source wiring 31 is shared.

  5 is a cross-sectional view taken along line bb of FIG.

  In the HEMT structure, an insulating region 50 is disposed outside the operation region 100. That is, the tip of the gate electrode 17 (comb teeth) is disposed on the insulating region 50. Then, two gate electrodes 17 arranged on both sides of one first source electrode and second source electrode (or first drain electrode and second drain electrode) are connected by a gate connection metal layer 18.

  A nitride film 60 is provided on the gate electrode 17. The gate connection metal layer 18 is disposed on the nitride film 60 outside the operation region 100 and is in contact with two adjacent gate electrodes 17 through contact holes CH provided in the nitride film 60.

  Although not shown, in the case of a GaAs MESFET, the substrate surface with which the gate electrode 17 contacts is a GaAs semi-insulating substrate. The gate connection metal layer 18 is provided on the semi-insulating substrate outside the operation region 100 which is an impurity region via an insulating film, and is in contact with the gate electrode 17.

  Thus, in the present embodiment, the end (tip) opposite to the end connected to the gate wiring 21 in the gate electrode 17 is connected to the gate connection metal layer 18. Then, the gate connection metal layer 18 is disposed near the tips of the first source electrode 13 and the second source electrode 15 or the first drain electrode 14 and the second drain electrode 16.

  As a result, the gate connection metal layer 18 or the gate wiring 21 is always provided between the first source electrode 13 and the second source electrode 15 and the drain wiring 32 or between the first drain electrode 14 and the second drain electrode 16 and the source wiring 31. Arranged patterns can be realized.

  In the operation region 100, the high-frequency signal propagates along the path indicated by the arrow in FIG. That is, when the FET is off, the high-frequency signal does not pass through the channel layer of the FET, but in the prior art (FIG. 8), a leak path of the high-frequency signal is formed outside the channel layer of the FET as indicated by an arrow in the X region. In the present embodiment, the gate connection metal layer 18 is disposed between the second source electrode S and the second drain electrode D in the conventional X-region high-frequency signal leakage path.

  Accordingly, it is possible to prevent a high frequency current from flowing between the second source electrode S and the second drain electrode D through the substrate, and it is possible to prevent leakage of a high frequency signal.

  Similarly, a gate electrode G (gate wiring 21) is disposed between the second source electrode S and the second drain electrode D in the Y region outside the channel layer of the FET. Therefore, high-frequency signal leakage does not occur in the Y region.

  Thereby, outside the channel layer of the FET (except for the operation region between the first source electrode 13 and the first drain electrode 14), the gate electrode G is interposed between the second source electrode S and the second drain electrode D in both the X region and the Y region. Since (the gate connection metal layer 18 or the gate wiring 21) is disposed, it is possible to prevent a high-frequency current from flowing between the second source electrode S and the second drain electrode D through the substrate, Leakage can be prevented.

  Hereinafter, further description will be given with reference to FIGS. 6 and 7.

  FIG. 6 is a cross-sectional view showing this embodiment. 6A is a cross-sectional view taken along line cc in FIG. 4, and FIG. 6B is a cross-sectional view taken along line dd in FIG.

  As shown in FIG. 6A, the tips of the first drain electrode 14 and the second drain electrode 16 and the source wiring 31 are arranged outside the operation region 100. A high-frequency signal passes through the first drain electrode 14, the second drain electrode 16, and the source wiring 31 on the insulating region 50 (a part of the semi-insulating substrate in the case of GaAs MESFET).

  Here, consider a case where the gate electrode G (gate connection metal layer 18) is not disposed between the second source electrode S and the second drain electrode D in FIG. The high frequency signal is transmitted to the insulating region 50 through the nitride film 60. The insulating region 50 transmits a high-frequency signal as a dielectric like the nitride film 60. That is, in this case, leakage of a high-frequency signal occurs between the second source electrode S and the second drain electrode D.

  In this state, since the second source electrode S and the second drain electrode D are directly opposed to each other, a direct electric field exists between the second source electrode S and the second drain electrode D. For this reason, a leak current of a high frequency signal flows. In the case of this embodiment, the high-frequency switch MMIC is a high-power switch MMIC composed of FETs connected in multiple stages, so that the amplitude of the high-frequency signal is large and the amplitude of the high-frequency leakage current is also large.

  Further, the second drain electrode 16 is connected to the first drain electrode 14 below it. The tip of the first drain electrode 14 is Schottky connected to the insulating region 50 (a part of the semi-insulating substrate in the case of GaAs MESFET). Accordingly, a large high-frequency leakage current flows between the source line 31 and the first drain electrode 14 as well as between the source line 31 and the second drain electrode 16.

  For this reason, when the source wiring 231 and the tip of the comb tooth of the second drain electrode 216 are arranged to face each other as in the conventional Y region (FIG. 8), leakage of the high frequency signal occurs.

  The same applies to the X ′ region and the Y region in FIG. 9. That is, in the X ′ region, the source wiring 231 and the tip of the comb teeth of the second drain electrode 216 are arranged to face each other even though the X ′ region is closest to the common input terminal pad I and exposed to a high-power high-frequency signal. Therefore, a large high frequency leakage current is generated. Further, the Y region is not exposed to a high-frequency high-frequency signal as much as the X ′ region, but has a similar structure to the X ′ region, so that some leakage occurs and the leakage of the high-frequency signal becomes large.

  In this embodiment, as shown in FIG. 6A, a gate connection metal layer 18 connected to the gate electrode 17 is disposed between the source wiring 31 and the first drain electrode 14 and the second drain electrode 16. Accordingly, leakage of high-frequency signals between the source wiring 31 and the first drain electrode 14 and the second drain electrode 16 can be blocked by the gate connection metal layer 18. The mechanism will be described below.

  First, the gate electrode G is connected to the control terminal Ctl via a control resistor CR of 5 to 10 KΩ. (See FIG. 2) A control signal is applied to the control terminal Ctl. Since the control signal is a DC signal, the control terminal becomes the GND potential of the high-frequency signal. The same applies when the gate electrode G is connected to the point CP of the logic circuit L.

  In the on-side FET, the gate electrode 17 directly contacts the surface of the operation region 100 to form a Schottky junction. That is, the potential of the gate electrode 17 vibrates at a high frequency under the influence of a high frequency current flowing through the channel layer of the FET. However, in the off-side FET, no current flows in the channel layer, and therefore the potential on the surface of the operating region 100 hardly oscillates at high frequency. That is, the gate electrode 17 does not vibrate at a high frequency like the on-side FET, and can be regarded as a GND potential of a high-frequency signal almost like the control terminal Ctl. Further, the gate connection metal layer 18 connected to the gate electrode 17 can also be regarded as the GND potential of the high frequency signal.

  Therefore, by disposing the gate connection metal layer 18 between the source wiring 31 of the off-side FET and the first drain electrode 14 and the second drain electrode 16, the arrangement as a planar pattern is the source wiring 31-the GND potential as the high frequency signal. -The first drain electrode 14 and the second drain electrode 16 are formed.

  The gate connection wiring 18 is formed on the nitride film 60 between the gate electrodes 17 as shown in the figure. However, since the high-frequency signal passes through the nitride film 60, the electric field is the same as when the nitride film 60 is not present. Therefore, leakage of high frequency signals between the second source electrode S and the second drain electrode D can be prevented.

  When the gate connection metal layer 18 is not disposed, an electric field of a direct high-frequency signal exists between the source wiring 31 and the first drain electrode 14 and the second drain electrode 16, but a GND potential as a high-frequency signal is sandwiched therebetween. Thus, the direct electric field between the source wiring 31 and the first drain electrode 14 and the second drain electrode 16 is greatly weakened. Accordingly, it is possible to prevent a high frequency current from flowing between the source wiring 31 and the first drain electrode 14 and the second drain electrode 16 through the substrate, and to prevent leakage of a high frequency signal. In particular, in the high power switch MMIC in which FETs are connected in multiple stages, the amplitude of the high frequency signal is large. Therefore, a strong electric field of the high frequency signal is generated between the source wiring 31 and the first drain electrode 14 and the second drain electrode 16. When the layer 18 is not disposed, a large high-frequency current flows. In the present embodiment, high-frequency signal leakage can be prevented even with a multi-stage high power switch MMIC.

  As shown in FIG. 6B, since the gate wiring 21 is similarly disposed between the drain wiring 32 and the first source electrode 13 and the second source electrode 15, leakage of high frequency signals can be prevented. Thus, according to the present embodiment, the gate electrode G (gate electrode 17, gate wiring 21) and the gate connection metal layer 18 are always provided in any path between the second source electrode S and the second drain electrode D. Since it is disposed, leakage of a high-frequency signal between the second source electrode S and the second drain electrode D can be prevented.

  The reason why high frequency signal leakage did not occur in the X region of the conventional structure is also due to the above mechanism. In the present embodiment, the high-frequency signal can be blocked by disposing the gate electrode G between the source electrode and the drain electrode, which has been a leakage path for the high-frequency signal in the conventional structure.

  The above mechanism works similarly when the gate wiring 21 is outside the operation region 100 in the present embodiment (FIG. 4). That is, it is possible to prevent leakage of a high-frequency signal between the second source electrode S and the second drain electrode D by sandwiching the gate wiring 21 or the gate connection metal layer 18 outside the operation region 100.

  Further, as shown in FIG. 7, a layout in which the gate electrode G ′ is not provided in a comb shape and one gate electrode G ′ is bent and extends between the second source electrode S and the second drain electrode D is considered.

  In this layout, the gate electrode G ′ is always sandwiched between the second source electrode S and the second drain electrode D, and the leakage of the high-frequency signal between the second source electrode S and the second drain electrode D by the gate electrode G ′. Can be prevented.

  However, this layout has a problem that it is extremely vulnerable to static electricity applied from the outside between the gate and the drain or between the gate and the source. The reason is that, in the case of such a pattern of the gate electrode G ′, the electrostatic energy applied to the control terminal Ctl concentrates on the start point ST (portion closest to the control resistor CR) of the gate electrode G ′ on the channel layer. Because. Accordingly, since the gate electrode G 'has a low electrostatic voltage and the start point ST of the gate electrode G' is destroyed, the electrostatic breakdown voltage is low as an MMIC, resulting in an unfavorable layout.

  On the other hand, in the present embodiment, a plurality of comb-like gate electrodes 17 are bundled by the gate wiring 21. Thereby, the electrostatic energy applied to the control terminal Ctl can be distributed evenly over the entire FET via the gate wiring 21.

  Thus, according to this embodiment, a comb-like gate electrode structure can be maintained. That is, it is possible to prevent leakage of high-frequency signals between the second source electrode S and the second drain electrode D without impairing reliability.

In particular, in the case of DPDT as in this embodiment, the input / output of signals is reversed, and the first RF port and the second RF port may be used interchangeably. In the present embodiment, any conventional leak path between the second source electrode S and the second drain electrode D can be completely blocked even when the high-frequency signal propagates in the opposite direction. That is, even if the terminal pad of any RF port becomes an input terminal pad having the strongest electric field of the high frequency signal, it is possible to completely prevent the leakage of the high frequency signal, so that the Pin _0.1 dB and the distortion characteristic as designed can be obtained. Obtainable.

  In order to prevent leakage of the high-frequency signal, it is desirable that the gate electrode G is continuously arranged without interruption in the leakage path between the second source electrode S and the second drain electrode D. However, the gate electrode G is formed by lift-off of the gate metal layer 20. That is, at the time of lift-off, the resist removing liquid is allowed to penetrate into the resist under the unnecessary gate metal layer 20, and the gate metal layer is removed together with the resist. Therefore, when the resist removing liquid does not sufficiently penetrate, an accurate pattern cannot be formed.

  In the present embodiment, the gate electrode G has a comb-like pattern. That is, when the gate electrode G is formed, the tip of the gate electrode 17 opposite to the gate wiring 21 is separated. Therefore, when the pattern of the gate electrode 1G is formed by lift-off, the resist removal liquid sufficiently permeates between the gate electrodes 17, so that the lift-off can be easily performed.

  Then, by connecting the two adjacent gate electrodes 17 with the gate connection metal layer, the linear leak path between the second source electrode S and the second drain electrode D is completely cut off, and the leakage of the high frequency signal is completely prevented. can do.

  Although illustration is omitted, when the FET is a GaAs MESFET, an impurity region may be formed by ion implantation in a non-doped GaAs substrate.

  For example, the operation region 100 is an n-type impurity region formed by ion implantation, and the source region 137s and the drain region 137d are n + -type impurity regions formed by ion implantation. The peripheral impurity region 51 for improving isolation is an n + type impurity region formed by ion implantation at the same time as the source region 137s and the drain region 137d, and the control resistance (high resistance body) is formed by ion implantation at the same time as the operation region 100. N-type impurity region.

  Alternatively, the impurity region may be formed by stacking an epitaxial layer having a predetermined impurity concentration on a non-doped GaAs substrate and separating the epitaxial layer by an insulating region.

  Further, in the source electrode and the drain electrode on the channel layer, the case where the first source electrode 13, the second source electrode 15, the first drain electrode 14, and the second drain electrode 16 overlap each other has been described as an example. The second source electrode and the second drain electrode are not necessarily required on the layer. That is, as the pattern shape in the vicinity of the gate connection metal layer 18, there is no tip portion of the second source electrode and there is only one end of the first source electrode, and there is no tip portion of the second drain electrode and only one end of the first drain electrode is present. good.

Although the DPDT switch MMIC provided with the logic circuit has been described above as an example, the configuration of the switch circuit device is not limited to the above example, and the switch circuit device having different input ports and output ports such as SP3T, SP4T, DP4T, and DP7T It is also possible to have a logic circuit or not. Furthermore, a shunt FET that prevents leakage of high-frequency signals may be connected to the off-side output terminal.

It is a circuit diagram for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a top view for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is sectional drawing for demonstrating this invention. It is a top view for demonstrating this invention. It is a top view for demonstrating a prior art. It is a top view for demonstrating a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Ohmic metal layer 13 1st source electrode 15 2nd source electrode 14 1st drain electrode 16 2nd drain electrode 17 Gate electrode 18 Gate connection metal layer 20 Gate metal layer 21 Gate wiring 30 Wiring metal layer 31 Source wiring 32 Drain wiring 40 Wiring metal layer 50 Insulating region 51 Peripheral impurity region 60 Nitride film 100 Operating region 131 GaAs substrate 132 Buffer layer 133 Electron supply layer 134 Spacer layer 135 Channel layer 136 Barrier layer 137 Cap layer 137s Source region 137d Drain region 215 Source electrode 216 Drain Electrode 217 Gate electrode 220 Gate metal layer 221 Gate wire 230 Wire metal layer 231 Source wire 232 Drain wire 260 Nitride film 300 Operating region IN Common input terminal IN1 First common input Child IN2 Second common input terminal Ctl Control terminal OUT1 First output terminal OUT2 Second output terminal I Common input terminal pad I1 First common input terminal pad I2 Second common input terminal pad C Control terminal pad C1 First control terminal pad C2 2nd control terminal pad O1 1st output terminal pad O2 2nd output terminal pad CR Control resistance SW1 1st switching element SW2 2nd switching element SW3 3rd switching element SW4 4th switching element CP Point

Claims (10)

A switching element provided with a comb-like source electrode, gate electrode, and drain electrode on the operating region of the compound semiconductor substrate;
An insulating film provided on the substrate surface outside the operating region;
A first RF port connected to a source electrode or a drain electrode of the switching element;
A second RF port connected to a drain electrode or a source electrode of the switching element;
A control terminal connected to the gate electrode of the switching element,
The gate electrode has a metal layer in which one end of each comb tooth extends outside the operation region, and one end of one comb tooth and one end of another adjacent comb tooth are arranged on the insulating film. A compound semiconductor switch circuit device, characterized by being connected to a semiconductor device.   2. The compound semiconductor switch circuit device according to claim 1, wherein the metal layer is arranged in the vicinity of one end of each comb tooth of the source electrode or the drain electrode in one operation region.   2. The compound semiconductor switch circuit device according to claim 1, wherein one comb tooth of the source electrode or the drain electrode is arranged between one comb tooth of the gate electrode and another comb tooth.   The other end of the comb teeth of one of the gate electrode, the source electrode, and the drain electrode is connected to the other end of the comb teeth of the other gate electrode, the source electrode, and the drain electrode by a gate wiring, a source wiring, and a drain wiring, respectively. The compound semiconductor switch circuit device according to claim 1.   5. The compound semiconductor switch circuit device according to claim 4, wherein the metal layer is disposed between one end of a comb tooth of the source electrode or the drain electrode and the drain wiring or the source wiring.   2. The compound semiconductor switch circuit device according to claim 1, wherein the switching element is formed by connecting FETs composed of the source electrode, the gate electrode, and the drain electrode in a multistage manner in series.   2. The compound semiconductor switch circuit device according to claim 1, wherein the gate electrode extends in a first direction, and the metal layer extends in a second direction.   The compound semiconductor switch circuit device according to claim 7, wherein the second direction is a direction perpendicular to the first direction.   The compound semiconductor switch circuit device according to claim 4, wherein the gate wiring is disposed on a surface of the compound semiconductor substrate. 2. The compound semiconductor switch circuit device according to claim 1, wherein a high-frequency analog signal propagates between the first RF port and the second RF port.