JP2006309575A5 - - Google Patents
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- JP2006309575A5 JP2006309575A5 JP2005132618A JP2005132618A JP2006309575A5 JP 2006309575 A5 JP2006309575 A5 JP 2006309575A5 JP 2005132618 A JP2005132618 A JP 2005132618A JP 2005132618 A JP2005132618 A JP 2005132618A JP 2006309575 A5 JP2006309575 A5 JP 2006309575A5
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- hardware
- mapped
- debug information
- information
- debug
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Claims (12)
前記複数のシミュレーションモデルは、ハードウェアにマッピングされる動作記述部と、
前記動作記述部を監視するハードウェアにマッピングされないデバッグ動作記述部と、
ハードウェアにマッピングされないインターフェイスとを有し、
前記インターフェイスを用いてデバッグ情報を転送し、デバッグ動作を行うことを特徴とするシステムLSIシミュレーション装置。 A system LSI simulation apparatus including a plurality of simulation models described at a transaction level in a system description language,
The plurality of simulation models include a behavior description part mapped to hardware;
A debug behavior description not mapped to hardware that monitors the behavior description;
An interface that is not mapped to hardware,
A system LSI simulation apparatus, wherein debug information is transferred using the interface to perform a debugging operation.
前記複数のシミュレーションモデルの一つが、前記ハードウェアにマッピングされないインターフェイスを介して受信した前記デバッグ情報に応じて前記デバッグ動作を行うことを特徴とする請求項1に記載のシステムLSIシミュレーション装置。 One of the plurality of simulation models transmits the debug information extracted by the debug behavior description unit not mapped to the hardware via an interface not mapped to the hardware,
2. The system LSI simulation apparatus according to claim 1, wherein one of the plurality of simulation models performs the debugging operation according to the debugging information received via an interface that is not mapped to the hardware.
転送手段が、ハードウェアにマッピングされないインターフェイスを用いてデバッグ情報を転送し、
デバック手段が、転送された前記デバッグ情報に対してデバッグ動作を行うことを特徴とするシステムLSIシミュレーション方法。 A system LSI simulation method in a system LSI simulation apparatus including a plurality of simulation models described at a transaction level in a system description language,
The transfer means transfers debug information using an interface that is not mapped to hardware,
A system LSI simulation method, wherein a debugging means performs a debugging operation on the transferred debug information.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005132618A JP4498206B2 (en) | 2005-04-28 | 2005-04-28 | System LSI simulation device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005132618A JP4498206B2 (en) | 2005-04-28 | 2005-04-28 | System LSI simulation device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006309575A JP2006309575A (en) | 2006-11-09 |
JP2006309575A5 true JP2006309575A5 (en) | 2008-06-19 |
JP4498206B2 JP4498206B2 (en) | 2010-07-07 |
Family
ID=37476376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005132618A Expired - Fee Related JP4498206B2 (en) | 2005-04-28 | 2005-04-28 | System LSI simulation device |
Country Status (1)
Country | Link |
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JP (1) | JP4498206B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120185820A1 (en) * | 2011-01-19 | 2012-07-19 | Suresh Kadiyala | Tool generator |
JP6615551B2 (en) * | 2015-09-24 | 2019-12-04 | 株式会社東芝 | Simulation apparatus and module thereof, simulation method and program |
-
2005
- 2005-04-28 JP JP2005132618A patent/JP4498206B2/en not_active Expired - Fee Related
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