JP2006302996A - Semiconductor integrated circuit, and circuit layout apparatus, method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent hold time error while suppressing increase in wiring length without inserting a buffer for adjusting delay. <P>SOLUTION: Assuming that a hold time error does not occurs between flipflops FF11 and FF13 but occurs between flipflops FF12 and FF13, the flipflops FF11 and FF13 reconnect scan paths P41-P44 in the order for shortening the wiring, and the flipflops FF12 and FF13 reconnect the scan paths P41-P44 in the order of late arriving time of clock. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, a circuit layout device, a circuit layout method, and a circuit layout program, and is particularly suitable for application to a scan design method for a semiconductor integrated circuit.

In the layout of the logic circuits and clock signal lines in the LSI, the logic circuits are arranged and wired so as to suppress clock skew (difference in clock signal arrival time) in order to prevent misshift during shifting. Yes.
Also, for example, in Patent Document 1, in order to allow LSI layout without losing the normal function timing, a delay adjustment buffer is inserted at a location where setup or hold has not converged to perform delay adjustment. A method for reconfiguring the scan chain by reordering the scan chain based on the value of the clock arrival time of the flip-flop taking into account the clock arrival time at the time of the flip-flop is disclosed.
JP 2003-256488 A

However, in the method disclosed in Patent Document 1, in order to reorder the scan chain in consideration of the clock arrival time, it is necessary to insert a delay adjustment buffer, which causes an increase in power consumption. It was.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit, a circuit layout device, a circuit layout method, and a circuit capable of preventing a hold time error and suppressing an increase in wiring length without inserting a delay adjustment buffer. To provide a layout program.

  In order to solve the above-described problem, according to a semiconductor integrated circuit according to one embodiment of the present invention, a clock arrival time of a plurality of flip-flops arranged in a semiconductor chip and a flip-flop in which a hold time error occurs is reduced. For the first wiring that sequentially connects the data input terminals of the flip-flops and the flip-flop that does not generate a hold time error, the data input terminals of the flip-flops are sequentially connected in an order that shortens the wiring length. Two wirings are provided.

  Thus, by reconnecting the wiring, it is possible to prevent a hold time error due to the clock skew while suppressing an increase in the wiring length. This eliminates the need to insert a delay adjustment buffer to prevent hold time errors caused by clock skew, and avoids wiring congestion, thus reducing layout design time. However, an increase in power consumption can be suppressed.

  In addition, according to the semiconductor integrated circuit of one embodiment of the present invention, a plurality of flip-flops arranged on a semiconductor chip, a clock tree that distributes a clock signal to the flip-flops, and a flip-flop that generates a hold time error For the first scan chain that connects the flip-flops in the slowest clock arrival time in the clock tree and the flip-flops that do not generate a hold time error, the data input to the flip-flops in such an order that the wiring length is shortened. And a second scan chain for sequentially connecting the terminals.

As a result, by reconnecting the scan chain, it is possible to prevent a hold time error due to clock skew while suppressing an increase in wiring length, and to shorten the time required for layout design. Thus, an increase in power consumption can be suppressed.
According to the circuit layout device of one aspect of the present invention, the clock tree generating means for generating a clock tree for distributing the clock signal to the cells arranged on the semiconductor chip, and the cells arranged on the semiconductor chip Arrangement information generating means for generating the arrangement information of the cell, wiring information generating means for generating the wiring information of the cells arranged in the semiconductor chip, and delay amount evaluating means for evaluating the delay amount of the wiring arranged in the cells A scan chain constructing means for constructing a scan chain in which the cells are reconnected in order from the latest clock arrival time based on the delay amount evaluated by the delay amount evaluating means, and the wiring length of the wiring arranged in the cell A scan chain correcting means for correcting the scan chain constructed by the scan chain constructing means, and the scan chain. Characterized in that it comprises a rerouting information generating means for generating a redistribution information of the cell based on the scan chain that is fixed in the chain modifying means.

  Thus, by reconnecting the scan chains, it is possible to prevent a hold time error caused by clock skew and to suppress an increase in wiring length. For this reason, it is not necessary to insert a delay adjustment buffer in order to prevent a hold time error due to clock skew, and it is possible to suppress an increase in power consumption and to avoid congestion of wiring. It becomes possible.

  According to the circuit layout method of one embodiment of the present invention, the step of generating a clock tree for distributing the clock signal to the cells arranged on the semiconductor chip and the arrangement information of the cells arranged on the semiconductor chip A step of generating wiring information of cells arranged on the semiconductor chip, a step of evaluating a delay amount of wirings wired to the cell, and a clock based on the evaluated delay amount Constructing a scan chain in which the cells are reconnected in the order of arrival time, modifying the constructed scan chain based on a wiring length of wiring arranged in the cell, and the modified scan Generating redistribution information of the cell based on a chain.

As a result, it is not necessary to insert a delay adjustment buffer, it is possible to prevent a hold time error, it is possible to suppress an increase in wiring length, and it is possible to suppress an increase in power consumption. In addition, it is possible to avoid wiring congestion.
According to the circuit layout program of one aspect of the present invention, the step of generating a clock tree for distributing the clock signal to the cells arranged on the semiconductor chip, and the arrangement information of the cells arranged on the semiconductor chip A step of generating wiring information of the cells arranged on the semiconductor chip, and a scan in which the cells are reconnected in the order of late arrival time of the clock based on the delay amount of the wiring wired to the cells. A step of constructing a chain; a step of modifying the constructed scan chain based on a wiring length of a wiring arranged in the cell; and generating rewiring information of the cell based on the modified scan chain And causing the computer to execute the step of performing.

  Thereby, by causing the computer to execute the circuit layout program, it is not necessary to insert a delay adjustment buffer, and it becomes possible to prevent a hold time error and to suppress an increase in the wiring length. It is possible to avoid congestion of wiring while suppressing an increase in power consumption.

Hereinafter, a circuit layout method according to an embodiment of the present invention will be described with reference to the drawings.
1 and 2 are diagrams for explaining a scan chain generation method according to an embodiment of the present invention. FIG. 3A is a timing chart for explaining a hold time error in the scan chain of FIG. ) Is a timing chart for explaining the improvement effect of the hold time error in the scan chain of FIG.

  In FIG. 1, a flip-flop FF2 is arranged at the subsequent stage of the flip-flop FF1. A clock path CP is connected via a buffer B to the clock signal input terminals CLKA and CLKB of the flip-flops FF1 and FF2. Further, the scan path P1 is connected to the data input terminal DA of the flip-flop FF1, and the data output terminal QA of the flip-flop FF1 and the data input terminal DB of the flip-flop FF2 are connected via the scan path P2, and the flip-flop FF2 A scan path P3 is connected to the data output terminal QB.

  In FIG. 3A, data input to the data input terminal DA via the scan path P1 is held in the flip-flop FF1 and output from the data output terminal QA. The data output from the data output terminal QA of the flip-flop FF1 is input to the data input terminal DB of the flip-flop FF2 via the scan path P2. The data input to the data input terminal DB is held in the flip-flop FF2 in synchronization with the clock signal input to the clock signal input terminal CLKB, and is output from the data output terminal QB.

  Here, it is assumed that the clock signal is input to the clock signal input terminal CLKB of the flip-flop FF2 with a delay of DL1 from the clock signal input terminal CLKB of the flip-flop FF2. The data output from the data output terminal QA of the flip-flop FF1 is input to the data input terminal DB of the flip-flop FF2 with a delay of the delay time DL2. In this case, when the clock signal input to the clock signal input terminal CLKB rises, the next data is input to the data input terminal DB of the flip-flop FF2 before the current data is held in the flip-flop FF2. Therefore, data omission occurs.

  Therefore, the scan paths P1 to P3 of the flip-flops FF1 and FF2 are reconnected in order of late clock arrival time. That is, in FIG. 2, the clock path CP is connected via the buffer B to the clock signal input terminals CLKA and CLKB of the flip-flops FF1 and FF2 of FIG. Further, the scan path P11 is connected to the data input terminal DB of the flip-flop FF2, and the data output terminal QB of the flip-flop FF2 and the data input terminal DA of the flip-flop FF1 are connected via the scan path P12, and the flip-flop FF1. A scan path P13 is connected to the data output terminal QA.

  In FIG. 3B, the data input to the data input terminal DB via the scan path P11 is held in the flip-flop FF2 and output from the data output terminal QB. The data output from the data output terminal QB of the flip-flop FF2 is input to the data input terminal DA of the flip-flop FF1 via the scan path P12. The data input to the data input terminal DA is held in the flip-flop FF1 in synchronization with the clock signal input to the clock signal input terminal CLKA, and is output from the data output terminal QA.

  Here, as in FIG. 3A, the clock signal is input to the clock signal input terminal CLKB of the flip-flop FF2 with a delay of the delay time DL1 from the clock signal input terminal CLKB of the flip-flop FF2. To do. On the other hand, the data output from the data output terminal QB of the flip-flop FF2 is input to the data input terminal DA of the flip-flop FF1 with a delay of a delay time DL3 larger than the delay time DL2 of FIG. In this case, when the clock signal input to the clock signal input terminal CLKA rises, the next data is input to the data input terminal DA of the flip-flop FF1 before the current data is held in the flip-flop FF1. Since there is nothing, there is no data omission.

Here, if only all the flip-flops are connected in order of the clock arrival time taking into consideration only the clock arrival time, the distance that must be bypassed increases and the wiring becomes congested. For this reason, flip-flops can be connected in consideration of not only the clock arrival time but also the wiring length.
FIG. 4 is a diagram showing a scan chain connection method according to an embodiment of the present invention.

  4A, the scan path P31 is connected to the input of the flip-flop FF11, the output of the flip-flop FF11 and the input of the flip-flop FF12 are connected via the scan path P32, and the output of the flip-flop FF12 is flip-flops. Assume that the input of the flip-flop FF13 is connected via the scan path P33, and the output of the flip-flop FF13 is connected to the scan path P34.

  Here, assuming that the clock arrival time is delayed in the order of the flip-flop FF13, the flip-flop FF11, and the flip-flop FF12, the scan paths P31 to P34 are reconnected in the order of the flip-flop FF13, the flip-flop FF11, and the flip-flop FF12. That is, in FIG. 4B, the scan path P41 is connected to the input of the flip-flop FF13, the output of the flip-flop FF13 and the input of the flip-flop FF11 are connected via the scan path P42, and the output of the flip-flop FF11 The input of the flip-flop FF12 is connected via the scan path P43, and the scan path P44 is connected to the output of the flip-flop FF12.

  As a result, it is possible to reconnect the wirings of the flip-flops FF11 to FF13 in order of late real time for reaching the clock, and it is possible to prevent a hold time error due to clock skew. For this reason, it is not necessary to insert a delay adjustment buffer to prevent a hold time error due to clock skew, so it is possible to reduce the time required for layout design and increase power consumption. Can be suppressed.

  Furthermore, if a hold time error does not occur between the flip-flops FF11 and FF13, but a hold time error occurs between the flip-flops FF12 and FF13, the flip-flops FF11 and FF13 are wired. In the order of shortening, the flip-flops FF12 and FF13 reconnect the scan paths P41 to P44 in order of late clock arrival time. 4C, the scan path P51 is connected to the input of the flip-flop FF11, the output of the flip-flop FF11 and the input of the flip-flop FF13 are connected via the scan path P52, and the output of the flip-flop FF13 is connected. The input of the flip-flop FF12 is connected via the scan path P53, and the scan path P54 is connected to the output of the flip-flop FF12.

  As a result, it is possible to reconnect the wirings of the flip-flops FF11 to FF13 in consideration of not only the clock arrival time but also the wiring length, and it is possible to prevent a hold time error due to clock skew while suppressing an increase in the wiring length. It becomes possible to do. This eliminates the need to insert a delay adjustment buffer to prevent hold time errors caused by clock skew, and avoids wiring congestion, thus reducing layout design time. However, an increase in power consumption can be suppressed.

FIG. 5 is a flowchart illustrating a scan chain generation method according to an embodiment of the present invention.
In FIG. 5, a clock tree for distributing clock signals to cells arranged on the semiconductor chip is generated (step S1). Note that a flip-flop can be used as a constituent element of the cell. Next, arrangement information of cells arranged on the semiconductor chip is generated (step S2). Next, wiring information of cells arranged on the semiconductor chip is generated (step S3). Next, the delay amount of the wiring wired to the cell is evaluated (step S4). Next, the arrangement coordinates of the cells arranged on the semiconductor chip are extracted (step S5). Then, the scan chains are reconnected while taking into account the delay amount of the wiring wired to the cells and the arrangement coordinates of the cells. That is, based on the evaluated delay amount of the wiring, a scan chain in which cells are reconnected in the order of the clock arrival time is constructed, and the constructed scan chain is modified based on the cell arrangement coordinates (step S6). . As a method for reconnecting the scan chain, for the cell in which the hold time error occurs, the scan chain is reconnected in order of the clock arrival time, and for the cell in which the hold time error does not occur, the wiring length is shortened. Scan chains can be reconnected in order. Then, cell rewiring information is generated based on the scan chain (step S7).

  Thus, by reconnecting the scan chains, it is possible to prevent a hold time error caused by clock skew and to suppress an increase in wiring length. For this reason, it is not necessary to insert a delay adjustment buffer in order to prevent a hold time error due to clock skew, and it is possible to suppress an increase in power consumption and to avoid congestion of wiring. It becomes possible.

The figure explaining the production | generation method of the scan chain which concerns on one Embodiment of this invention. The figure explaining the production | generation method of the scan chain which concerns on one Embodiment of this invention. 6 is a timing chart for explaining an improvement effect of a hold time error in a scan chain according to an embodiment of the present invention. The figure which shows the connection method of the scan chain which concerns on one Embodiment of this invention. 6 is a flowchart showing a scan chain generation method according to an embodiment.

Explanation of symbols

  FF1, FF2, FF11 to FF13 flip-flop, B buffer, P1 to P3, P11 to P13, P31 to P34, P41 to P44, P51 to P54 Scan campus, CP clock path, DA, DB data input terminal, QA, QB data Output terminal, CLKA, CLKB Clock signal input terminal, C Semiconductor chip

Claims (5)

A plurality of flip-flops arranged on a semiconductor chip;
For a flip-flop in which a hold time error occurs, a first wiring that sequentially connects the data input terminals of the flip-flop in order of late clock arrival time;
A flip-flop that does not generate a hold time error includes a second wiring that sequentially connects the data input terminals of the flip-flop in an order that shortens the wiring length. A plurality of flip-flops arranged on a semiconductor chip;
A clock tree for distributing a clock signal to the flip-flop;
For a flip-flop in which a hold time error occurs, a first scan chain that connects the flip-flops in order of late clock arrival time in the clock tree;
A flip-flop that does not generate a hold time error includes a second scan chain that sequentially connects the data input terminals of the flip-flop in an order that shortens the wiring length. Clock tree generating means for generating a clock tree for distributing a clock signal to cells arranged on a semiconductor chip;
Arrangement information generating means for generating arrangement information of cells arranged on the semiconductor chip;
Wiring information generating means for generating wiring information of cells arranged on the semiconductor chip;
A delay amount evaluating means for evaluating a delay amount of the wiring wired to the cell;
Based on the delay amount evaluated by the delay amount evaluating means, a scan chain constructing means for constructing a scan chain in which the cells are reconnected in order of late clock arrival time;
Based on the wiring length of the wiring arranged in the cell, scan chain correcting means for correcting the scan chain constructed by the scan chain constructing means,
A circuit layout apparatus comprising: rewiring information generation means for generating rewiring information of the cells based on the scan chain corrected by the scan chain correction means. Generating a clock tree for distributing clock signals to cells arranged on a semiconductor chip;
Generating arrangement information of cells arranged on the semiconductor chip;
Generating wiring information of cells arranged on the semiconductor chip;
Evaluating the amount of delay of wiring wired to the cell;
Based on the estimated delay amount, constructing a scan chain in which the cells are reconnected in order of slow clock arrival time;
Modifying the constructed scan chain based on the wiring length of the wiring placed in the cell;
Generating circuit rewiring information based on the modified scan chain. A circuit layout method comprising: Generating a clock tree for distributing clock signals to cells arranged on a semiconductor chip;
Generating arrangement information of cells arranged on the semiconductor chip;
Generating wiring information of cells arranged on the semiconductor chip;
Based on the delay amount of the wiring wired to the cell, constructing a scan chain in which the cells are reconnected in order of slow clock arrival time;
Modifying the constructed scan chain based on the wiring length of the wiring placed in the cell;
A circuit layout program causing a computer to execute the step of generating rewiring information of the cell based on the modified scan chain.

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