JP2006302330A - Method of measuring leakage current in sram - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of measuring a leakage current for efficiently obtaining the maximum value of a leak current varied depending on data stored in a plurality of memory cells included in an SRAM. <P>SOLUTION: The method comprises: a step (a) in which a first measurement value is obtained by measuring a leak current flowing in the SRAM after supplying a power source, a step (b) in which a second measurement value is obtained by storing the first data pattern into a plurality of memory cells and measuring the leakage current flowing in the SRAM, step (c) in which a third measurement value is obtained by storing the second data pattern being complementary to the first data pattern into the plurality of memory cells and measuring the leakage current flowing in the SRAM, and a step (d) in which the maximum value of the leakage current flowing in the SRAM is calculated based on the first measurement value, the second measurement value and the third measurement value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for measuring a leakage current flowing between power supplies in a static random access memory (SRAM), in particular, data stored in a plurality of memory cells included in the SRAM. The present invention relates to a leak current measuring method for obtaining a maximum value of a leak current that varies depending on the current.

  Conventionally, it is required to increase the operation speed of a semiconductor integrated circuit. A logic circuit and a memory circuit included in a semiconductor integrated circuit are constituted by a large number of transistors, and high-speed computation can be performed by speeding up a switching operation for turning on / off these transistors. In order to speed up the switching operation of the MOS transistor, it is effective to shorten the gate length between the source and the drain.

  Generally, the fineness of a semiconductor integrated circuit is expressed by a process rule (micron rule). In recent years, miniaturization of semiconductor integrated circuits has progressed, and the 0.18 micron rule with a basic wiring thickness of 0.18 μm, and the basic wiring thickness of 0.13 μm with 0.13 μm. Semiconductor integrated circuits such as rules are manufactured.

  In this way, by manufacturing a semiconductor integrated circuit with a fine structure, the gate length of the transistor is shortened to realize high-speed operation, but on the other hand, by shortening the gate length, between the gate and the source, A leakage current flowing between the gate and the drain or between the source and the drain when the transistor is off is increasing.

In an SRAM including a plurality of memory cells, there is a phenomenon that the value of the leakage current changes depending on the combination of data “1” and “0” stored in these memory cells. The value of the leakage current flowing between the power supplies in a state where the transistor is stationary is also referred to as “IQ”, and the maximum value IQ _MAX of the measured leakage current is a value representing one of the characteristics of the SRAM. It is managed in the inspection process for determining defective products of integrated circuits.

Conventionally, in order to obtain the maximum value IQ _MAX of the leakage current, various combinations of data “1” and “0” are stored in the memory cell, the leakage current is measured, and the leakage current in those cases is compared. Had gone. However, in order to find a combination of data in which the leakage current reaches the maximum value IQ _MAX , it is necessary to perform measurement with a huge amount of data, and a great amount of measurement time is consumed.

As a related technique, in Patent Document 1 below, information opposite to the information of all the cells written in the memory LSI at the time of power-on is written in all the cells of the memory LSI, and then the reverse from the memory LSI. A method for testing a memory LSI is disclosed in which it is checked whether or not the above information can be read normally. However, this test method improves the efficiency of the soft error test by α rays by testing the memory IC with the worst pattern in which the soft error is likely to occur for the memory IC, and obtains the maximum value of the leakage current. Is not disclosed at all.
JP-A-2-185800 (first and third pages, FIG. 1)

  Accordingly, in view of the above points, the present invention provides a leakage current measuring method capable of efficiently obtaining the maximum value of leakage current that varies depending on data stored in a plurality of memory cells included in an SRAM. For the purpose.

  In order to solve the above problems, a leakage current measuring method according to the present invention is a leakage current measuring method for obtaining a maximum value of a leakage current that varies depending on data stored in a plurality of memory cells included in an SRAM, Step (a) of obtaining a first measurement value by measuring the leakage current flowing in the SRAM after power-on, and measuring the leakage current flowing in the SRAM by storing the first data pattern in a plurality of memory cells. The step (b) of obtaining the second measurement value, the second data pattern complementary to the first data pattern stored in the plurality of memory cells, and the leakage current flowing through the SRAM are measured. Step (c) to obtain the measurement value of 3, the first measurement value obtained in step (a), the second measurement value obtained in step (b), and the step On the basis of the third measurement value obtained in flops (c), it comprises a step (d) of calculating the maximum value of the leakage current flowing SRAM.

  Here, in step (b), the data pattern of all “0” is stored in the plurality of memory cells and the leakage current flowing in the SRAM is measured. In step (c), all “1” is stored in the plurality of memory cells. A data pattern may be stored and a leakage current flowing through the SRAM may be measured.

  Alternatively, in step (b), an alternating data pattern of “01” is stored in each row of a memory cell array composed of a plurality of memory cells, and a leakage current flowing through the SRAM is measured. In step (c), a plurality of memories An alternating data pattern of “10” may be stored in each row of the memory cell array composed of cells, and the leakage current flowing in the SRAM may be measured.

  In step (d), the maximum value of the leakage current flowing in the SRAM may be calculated by subtracting the first measurement value from the sum of the second measurement value and the third measurement value. .

  According to the present invention, a leakage current that varies depending on data stored in a plurality of memory cells included in an SRAM by measuring a leakage current in three specific states and performing an operation based on the measured values. The maximum value of current can be obtained efficiently. As a result, the leakage current measurement time in the semiconductor integrated circuit inspection process can be significantly reduced.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a circuit diagram showing an equivalent circuit of a memory cell included in an SRAM. In order to simplify the explanation, only one memory cell is shown in FIG. 1, but actually a plurality of memory cells are arranged in a two-dimensional array to constitute a memory cell array.

  As shown in FIG. 1, this memory cell includes an inverter 10 constituted by a P channel MOS transistor QP11 and an N channel MOS transistor QN11, an inverter 20 constituted by a P channel MOS transistor QP21 and an N channel MOS transistor QN21, N channel MOS transistors QN31 and QN32 constituting a write / read port are included, and a first store node N1 and a second store node N2 for storing data are provided.

  The source-drain path of the transistor QN31 is connected between the first store node N1 and the bit line BLa, and the source-drain path of the transistor QN32 is connected between the second store node N2 and the bit line BLb. It is connected to the. The gates of the transistors QN31 and QN32 are connected to the word line WL.

In the inverter 10, the gates of the transistors QP11 and QN11 are connected to the first store node N1, and the drains of the transistors QP11 and QN11 are connected to the second store node N2. In addition, the source of the transistor QP11 is connected to the power supply potential _{V DD,} the source of the transistor QN11 is connected to the power supply potential _{V SS.}

In the inverter 20, the gates of the transistors QP21 and QN21 are connected to the second store node N2, and the drains of the transistors QP21 and QN21 are connected to the first store node N1. In addition, the source of the transistor QP21 is connected to the power supply potential _{V DD,} the source of the transistor QN21 is connected to the power supply potential _{V SS.}

  That is, the inverter 10 has an input connected to the first store node N1 and an output connected to the second store node N2. The inverter 20 has an input connected to the second store node N2 and an output connected to the first store node N1. For example, when data “0” is stored in the memory cell, the word line WL is set to the high level to turn on the transistors QN31 and QN32, and a voltage is applied to the store nodes N1 and N2 via the bit lines BLa and BLb. As a result, the first store node N1 is set to the low level, and the second store node N2 is set to the high level.

  On the other hand, when data “1” is stored in the memory cell, the word line WL is set to the high level to turn on the transistors QN31 and QN32, and a voltage is applied to the store nodes N1 and N2 via the bit lines BLa and BLb. As a result, the first store node N1 is set to the high level, and the second store node N2 is set to the low level. Thereafter, even if the transistors QN31 and QN32 are turned off, the state of the data stored in the store nodes N1 and N2 is maintained.

  The transistors QP11 to QP21 and QN11 to QN32 are formed in a semiconductor integrated circuit, and realize high-speed operation by shortening the gate length of the transistor. There is a leakage current flowing between the gate and the drain or between the source and the drain when the transistor is off.

  This leakage current is determined by the layout (cell structure) of the memory cell in the semiconductor integrated circuit. Here, it is assumed that the leakage current between the source and gate of the transistor QP11 is particularly large, and this is equivalent to resistance ( Leakage resistance). In this case, when the first store node N1 is at a low level, the leakage current due to the leakage resistance increases, but when the first store node N1 is at a high level, the leakage current due to the leakage resistance can be ignored. Thus, the value of the leakage current that actually flows through the memory cell varies depending on the state of the data stored in the store node.

In an SRAM including a plurality of memory cells, the value of the leakage current IQ flowing through the entire SRAM changes depending on the combination of data “1” and “0” stored in these memory cells. It is difficult to measure IQ _MAX . Therefore, in the present embodiment, the maximum value IQ _MAX of the leakage current IQ is efficiently obtained by measuring the leakage current IQ by the measurement method described below.

  Next, a leakage current measuring method according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a flowchart showing a leakage current measuring method according to the first embodiment of the present invention.

  First, in step S1, the SRAM is turned on. As a result, in the plurality of memory cells included in the SRAM, potentials are generated at the first and second store nodes N1 and N2. These potentials are not applied from the outside of the memory cell, but are determined by the magnitude of leakage current in a plurality of transistors constituting the memory cell. That is, the cell structures of the plurality of memory cells are different from each other, and the magnitude relation of the leakage current between the plurality of transistors is different. Accordingly, which one of the first and second store nodes N1 and N2 is at a high level and which is at a low level is determined by the magnitude relationship of leakage currents between a plurality of transistors in each memory cell. As a result, when power is supplied to the SRAM, the state of data stored in the plurality of memory cells is naturally determined.

  FIG. 3A is a diagram showing the state of data stored in a plurality of memory cells after the SRAM is powered on. Here, when the first store node N1 shown in FIG. 1 is at a low level and the second store node N2 is at a high level, data “0” is stored in the memory cell, and the first store node N1 When the second store node N2 is at the low level, data “1” is stored in the memory cell.

Next, in step S2, obtain measurements IQ ₁ by measuring the leakage current IQ flowing throughout SRAM in the state shown in (a) of FIG. In this state, since the sum of the leakage current is at the minimum in a plurality of transistors included in each memory cell, measurements IQ ₁ represents the minimum value of the leak current IQ flowing across SRAM.

  In step S3, data “0” is stored in all the memory cells included in the SRAM. FIG. 3B is a diagram illustrating a state where data “0” is stored in all the memory cells. Here, in the memory cells shown in gray, the data is inverted from the state after power-on shown in FIG.

In step S4, obtain measurements IQ ₂ by measuring the leakage current IQ flowing throughout SRAM in the state shown in (b) of FIG. In the state shown in FIG. 3 (b), as compared to the state after the power-on shown in FIG. 3 (a), since the leakage current is increased in the memory cell shown in gray, measurements IQ ₂ Is greater than the measured value IQ ₁ obtained in step S2.

  In step S5, data “1” is stored in all the memory cells included in the SRAM. FIG. 3C shows a state where data “1” is stored in all the memory cells. Here, in the memory cells shown in gray, the data is inverted as compared with the state after power-on shown in FIG.

In step S6, obtaining a measurement value IQ ₃ by measuring the leakage current IQ flowing throughout SRAM in the state shown in (c) of FIG. In the state shown in FIG. 3C, since the leakage current is increased in the memory cell shown in gray as compared with the state after turning on the power shown in FIG. The value IQ ₃ is larger than the measured value IQ ₁ obtained in step S2.

In step S7, based on the measured value IQ ₁ obtained in step S2, the measured value IQ ₂ obtained in step S4, and the measured value IQ ₃ obtained in step S6, the following equation (1) is obtained. The maximum value IQ _MAX of the leakage current IQ flowing through the entire SRAM is obtained.
IQ _MAX = IQ ₂ + IQ ₃ −IQ ₁ (1)

Here, the measurement value IQ _2, it min? Iq ₂ leakage current is increased by the memory cell shown in gray as shown in FIG. 3 (b) data "1" is replaced by data "0", the measured value IQ _It is added to ₁ .
IQ ₂ = IQ ₁ + ΔIQ ₂ (2)

The measurement value IQ _3, it min? Iq ₃ a leakage current is increased by the memory cell shown in gray data "0" is replaced by data "1" shown in FIG. 3 (c), the measured value IQ ₁ Is added.
IQ ₃ = IQ ₁ + ΔIQ ₃ (3)

When both sides of Formula (2) and Formula (3) are added together, the following Formula (4) is obtained.
IQ ₂ + IQ ₃ = 2 · IQ ₁ + ΔIQ ₂ + ΔIQ ₃ (4)
Therefore, the right side of Equation (1) is transformed as follows.
IQ ₂ + IQ ₃ −IQ ₁ = 2 · IQ ₁ + ΔIQ ₂ + ΔIQ ₃ −IQ ₁
= IQ ₁ + ΔIQ ₂ + ΔIQ ₃

This is indicated by the measured value IQ ₁ representing the minimum leakage current, the leakage current increment ΔIQ ₂ in the memory cell shown in gray in FIG. 3B, and the gray shown in FIG. 3C. represents a value obtained by adding the increment? Iq ₃ of leakage current in the memory cell. As apparent from FIG. 3, the memory cells shown in gray in FIG. 3B and the memory cells shown in gray in FIG. 3C have a complementary relationship. The sum of these increments (ΔIQ ₂ + ΔIQ ₃ ) corresponds to the increase in leakage current in all memory cells. As described above, the leakage current IQ in the three states is measured, and the maximum value IQ _MAX of the leakage current IQ is efficiently obtained by performing the calculation based on the measured values IQ ₁ , IQ ₂ , IQ _3. Can do.

  Next, a leakage current measuring method according to the second embodiment of the present invention will be described with reference to FIG. In the first embodiment, data “0” is stored in all memory cells in step S3, and data “1” is stored in all memory cells in step S5. However, the present invention is not limited to this. Instead, the data pattern stored in the memory cell in step S3 and the data pattern stored in the memory cell in step S5 need only be complementary.

FIG. 4 is a diagram showing data patterns stored in the memory cell in the leakage current measurement method according to the second embodiment of the present invention.
FIG. 4A is a diagram showing the state of data stored in a plurality of memory cells after the SRAM is powered on. Obtain a measure IQ ₁ by measuring the leakage current IQ flowing throughout SRAM in this state.

Next, as shown in FIG. 4B, the alternating data pattern “0101...” Is stored in each row of the memory cell array composed of a plurality of memory cells. Here, in the memory cells shown in gray, the data is inverted from the state after power-on shown in FIG. Obtain a measure IQ ₂ by measuring the leakage current IQ flowing throughout SRAM in this state.

Further, as shown in FIG. 4C, an alternating data pattern “1010...” Is stored in each row of the memory cell array composed of a plurality of memory cells. Here, in the memory cells shown in gray, the data is inverted as compared with the state after power-on shown in FIG. Obtain a measure IQ ₃ by measuring the leakage current IQ flowing throughout SRAM in this state.

Thereafter, similarly to the first embodiment, based on the measured values IQ ₁ , IQ ₂ , IQ ₃ , the maximum value IQ _MAX of the leakage current IQ flowing through the entire SRAM is obtained by the equation (1). Also in the present embodiment, the leakage current IQ in three states is measured, and the maximum value IQ _MAX of the leakage current IQ is efficiently obtained by performing calculations based on the measured values IQ ₁ , IQ ₂ , IQ _3. Can be sought.

The circuit diagram which shows the equivalent circuit of the memory cell contained in SRAM. 3 is a flowchart showing a leakage current measuring method according to the first embodiment of the present invention. The figure which shows the data pattern stored in a memory cell in 1st Embodiment. The figure which shows the data pattern stored in a memory cell in 2nd Embodiment.

Explanation of symbols

  10, 20 Inverter, QP11 to QP21 P channel MOS transistor, QN11 to QN32 N channel MOS transistor, N1, N2 store node, BLa, BLb bit line, WL word line

Claims (4)

A leakage current measurement method for obtaining a maximum value of a leakage current that varies depending on data stored in a plurality of memory cells included in an SRAM,
(A) obtaining a first measurement value by measuring a leakage current flowing in the SRAM after power-on;
(B) obtaining a second measurement value by storing a first data pattern in the plurality of memory cells and measuring a leakage current flowing in the SRAM;
(C) obtaining a third measurement value by storing a second data pattern complementary to the first data pattern in the plurality of memory cells and measuring a leakage current flowing in the SRAM;
Based on the first measurement value obtained in step (a), the second measurement value obtained in step (b), and the third measurement value obtained in step (c), it flows to the SRAM. Calculating the maximum value of the leakage current (d);
A leakage current measuring method comprising: Step (b) includes storing all “0” data patterns in the plurality of memory cells and measuring a leakage current flowing in the SRAM;
Step (c) includes storing all “1” data patterns in the plurality of memory cells and measuring a leakage current flowing in the SRAM;
The leakage current measuring method according to claim 1. Step (b) includes storing an alternating data pattern of “01” in each row of the memory cell array composed of the plurality of memory cells and measuring a leakage current flowing through the SRAM;
Step (c) includes storing an alternating data pattern of “10” in each row of the memory cell array constituted by the plurality of memory cells and measuring a leakage current flowing through the SRAM.
The leakage current measuring method according to claim 1.   The step (d) includes calculating a maximum value of a leakage current flowing through the SRAM by subtracting the first measurement value from the sum of the second measurement value and the third measurement value. The leakage current measuring method of any one of 1-3.

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