JP2006302321A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten processing time for booting an information processor. <P>SOLUTION: Relating to the information processor 50 comprising a storage device control part 51, a volatile storage device for recording information of operation, an operation interrupting switch 53, a non-volatile storage device 55 and a power switch 57 and having an operation state, a nap state, a hibernation state and a hibernation preparing state, the non-volatile storage device 55 is provided with a start flag storage area 551 and an area 552 for storing information stored in the volatile storage device and the power supply part 57 is provided with an external power supply operation switch 574 and a power supply interruption part 571, when the operation of the information processor 50 is interrupted, the information stored in the volatile storage device 52 is saved to the area 552 of the non-volatile storage device 55, the state of the information processor 50 is shifted to the nap state or the hibernation state, and when power supply is restarted in the state, the information stored in the non-volatile storage device 55 during the interruption of operation is automatically restored to the device 52 and the state of the information processor 50 is returned to the same state as the execution of operation for interrupting work during the operation of the information processor 50. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for reducing processing time when an information processing apparatus is activated.

  It is possible to interrupt the current work on the operating information processing device, store the internal information of the information processing device at that time in a non-volatile storage medium, and turn off the information processing device. There has been an information processing apparatus having a function of restoring internal information at the time of interruption from a non-volatile storage medium so that the suspended work can be resumed.

  There are some information processing devices that have the function of supplying power only to the part necessary to hold the internal information of the information processing apparatus and reducing the power of the part not necessary to hold the internal information of the information processing apparatus. It was.

  When starting up the information processing apparatus, there is a problem that it takes time from when the start switch is operated until it is actually usable.

  The internal information of the information processing device is stored in a non-volatile storage medium such as an external storage device, and the information processing device can be read from the non-volatile storage medium such as an external storage device even when returning from the hibernation state when the information processing device is turned off There is a problem that it takes time.

  If external power supply is not always possible, there is a problem that internal information of the information processing apparatus cannot be held in a nap state.

  Since power consumption exists even in the nap state, maintaining the nap state with the power of the power storage means has a problem of shortening the usage time of the power storage means.

  Since power consumption exists even in a nap state, there is a problem that maintaining a nap state for a long time becomes wasteful power consumption even if external power supply is possible.

  Further, in the conventional technology, when the information processing apparatus is started, it is not necessary to load the operating system or application program every time after operating the power switch, until the information processing apparatus can actually be used. Can be shortened. However, there is a great difference in the shortening time depending on whether the storage device for storing the operating state is volatile or non-volatile.

  If information is stored in a non-volatile storage device such as a magnetic disk, it returns to the previous state when the power is turned on, and it takes time in minutes to read the information to the volatile storage device. .

  Similarly, the process of storing information in the nonvolatile storage device also takes time, and there is a problem that nothing can be done during that time.

  When information is stored in a volatile storage device such as a main memory composed of DRAM, there is no procedure for reading information from the nonvolatile storage device, so the time to return to the previous state is shortened. However, since power must be continuously supplied to the DRAM during the operation interruption state, there is a problem that power is consumed and it is not suitable for long-term state storage.

  In addition, when storing information in a non-volatile storage device, if the information at the time of operation interruption is damaged for some reason, there is only a problem that the information processing device must be restarted, restoration to the state before the operation interruption is There is a problem that you can not.

  In an information processing apparatus having a volatile storage device and a non-volatile storage device for recording internal state information during operation, the information processing device is started, information processing device control software such as an OS is started up once, and the information processing device is When the information becomes usable, the internal information of the information processing apparatus is kept as it is even if the user operates the stop means.

  Provide external power supply detection means and internal state transition record storage means, and take into account the operation of the start / stop means performed by the user, the external power supply state, and the previous state transition. Recognize the state.

  As a state in which the internal information is kept, a nap state and a hibernation state are provided.

  When an AC adapter or the like is connected and power can be supplied from outside for a long time, the hibernation state shifts to the nap state.

  When power storage means such as a battery is built in and power supply from the outside such as an AC adapter suddenly stops, the power of the power storage means is used to shift to a hibernation state.

  Time measuring means capable of operating even in a nap state is provided.

  After the information processing device is activated, information in the volatile storage device inside the information processing device at a certain point in time is saved in the nonvolatile storage device. This is designated as hibernation file 1.

  When the user performs an operation to interrupt the operation during the operation of the information processing apparatus, information in the volatile storage device at that time is saved in the nonvolatile storage device. At that time, if the user performs an operation to resume the work on the information processing apparatus, the saving process is immediately stopped and the operation state is returned. If there is no input, the evacuation process is continued as it is, and this is designated as the hibernation file 2.

  After saving the information at the time of operation interruption to the non-volatile storage device, if power is continuously supplied to the information processing device, the power supply to the volatile storage device is not stopped, and the state at the time of operation interruption is restored. Disconnect power to parts unrelated to the function. This is hereinafter referred to as a nap state.

  If the user performs an operation of resuming work before the power supply to the information processing apparatus is interrupted, all power supply to the information processing apparatus is resumed, and the state before the interruption is restored.

  If the power supply to the information processing device is interrupted during a nap such as when a breaker is dropped, the information processing device loses operating information in the volatile storage device and operates only in the non-volatile storage device that was saved during the interruption. The information at the time of interruption is stored. This is hereinafter referred to as hibernation.

  When power supply from the outside is resumed during this state, the information processing apparatus automatically restores information (hibernation file 2) at the time of operation interruption in the nonvolatile storage device to the volatile storage device, Become. If the restoration fails or if it is desired to restore the state before the operation is interrupted by the user's will, the hibernation file 1 is restored to the volatile storage device, and the nap state is entered.

  According to the present invention, in the information processing apparatus, the activation work in the information processing apparatus after issuing the activation instruction can be completed in a short time, so that the user can immediately resume the previous work and the usability of the information processing apparatus is improved. . Further, according to the present invention, the end work in the information processing apparatus after issuing the end instruction can be completed in a short time, and the user can shorten the time restrained by the information processing apparatus after the end instruction. Furthermore, according to the present invention, even if power supply from the outside suddenly stops, the hibernation file is created and then the hibernation state S4 is entered. It can be minimized. In addition, according to the present invention, when the information processing apparatus is not used for a long period of time, the process shifts to the hibernation state S4, so that power consumption can be suppressed.

  According to the present invention, since the hibernation file is created when the information processing apparatus is terminated, it is possible to reduce the startup processing time when the operator performs an operation for resuming the operation of the information processing apparatus. It can be resumed and is easy to use. Further, according to the present invention, even when the power supply from the outside to the information processing apparatus is interrupted, the process shifts to the hibernation state S4 after the process of creating the hibernation file, so the information at the time of the previous operation interruption is lost. In addition, long-term state storage is possible. According to the present invention, when the user performs any information input operation during the operation of saving the information in the volatile storage device to the non-volatile storage device, the user immediately returns to the operation state and the responsiveness is good. Become. Furthermore, according to the present invention, when the information at the time of the operation interruption is damaged for some reason, it is possible to return to the state before the operation interruption without restarting the information processing apparatus.

  A first embodiment of an information processing apparatus according to the present invention will be described with reference to FIGS.

  FIG. 1 is a functional block diagram schematically showing a configuration of an electronic circuit, a power supply control unit, a nonvolatile external storage device, information to be handled, and a control unit for supplied power of the information processing apparatus main body.

  The information processing apparatus of the present invention includes at least an information processing apparatus main body electronic circuit 1, a nonvolatile external storage device 2, and a power supply control unit 3.

  The information processing apparatus main body electronic circuit 1 has internal storage device data 10, LSI internal information 11, and display memory data 101 as volatile information. Further, the information processing apparatus main body electronic circuit 1 includes a rewritable nonvolatile storage element 12 that stores state transitions of the information processing apparatus. The storage element 12 may be constituted by a battery backup memory or a flash memory. The storage element 12 stores identification information of the current internal state of the information processing apparatus and the internal state before the transition to the current state.

  The external storage device 2 has a data storage area 21 for the internal storage device, a data storage area 22 for the LSI internal information, and display memory data as areas for storing volatile information of the information processing apparatus main body electronic circuit 1 main body. A storage area 211 is provided.

  The power supply control unit 3 includes a power supply circuit unit 31 and a power storage unit 32 such as a battery, and includes a cable 45 connected to the external power supply unit and a power supply line 42 to the information processing apparatus main body electronic circuit 1. The power supply circuit unit 31 includes an external power detection unit 311, a start / stop switch 313, a start / stop control unit 312, and a power switching unit 314, and includes the external power detection unit 311 and the start / stop control unit 312. The state is transmitted to the information processing apparatus main body through power supply circuit state output lines 43 and 44.

  FIG. 2 is a diagram showing internal states and transition conditions of the information processing apparatus according to the first embodiment of the present invention. The information processing apparatus of the present invention transitions between the three states of the operation state S2, the nap state S3, and the hibernation state S4 under normal use conditions. While these three states are transiting, processing such as reconstruction and replacement of control software of an information processing apparatus such as an OS cannot be performed. Processing such as reconstruction and replacement of control software for an information processing apparatus such as an OS is performed while the internal state of the information processing apparatus is changed to the initial state S1 and then is changed to the operation state S2.

  The initial state S1 is a state immediately after the information processing apparatus is manufactured or when control software for the information processing apparatus such as an OS is reconstructed on the information processing apparatus.

  The operation state S2 is a state in which the information processing apparatus can perform information processing, and refers to a state in which power is supplied to all electronic circuits of the information processing apparatus.

  The nap state S3 refers to supplying power only to volatile storage elements such as internal storage devices and display memories and control circuits necessary for maintaining the storage, and stopping power supply to electronic circuits not related to storage of internal information. Refers to the state. FIG. 3 shows this state. 3 schematically shows hatched portions where power supply is stopped, internal storage device data 10, LSI internal information 11, display memory data 101, and power supply control unit. 3 shows that it is effective. The power supply control unit 3 is the same as the operation state S2 except that the amount of power supplied to the information processing apparatus main body electronic circuit 1 is different.

  The hibernation state S4 means that volatile information such as internal storage device data 10, LSI internal information 11, and display memory data 101 is stored in the storage areas 21, 22, 211 of the nonvolatile external storage device 2, respectively. The stored power is supplied only to the external power detection unit 311 and the start / stop control unit 312 of the power supply control unit 3. This state is shown in FIG. In FIG. 4, the portion where the power supply is stopped is schematically hatched, and in the hibernation state S4, the power to the external storage device 2 is also cut off, but since it is a nonvolatile storage device, it is stored. Each piece of information is valid.

  The information processing apparatus is in the initial state S1 immediately after manufacture, and is supplied with power by the start / stop switch 313 operated by the user, and transits to the operation state S2 (T7).

  The initial state S1 and the other three states are divided depending on whether or not the control software of the information processing apparatus such as the OS has started. In the initial state S1, information is not written in the nonvolatile storage element 12 that stores the state of the information processing apparatus. The startup period from when the normal information processing apparatus is turned on until it can be used by the user is the transition time from the initial state S1 to the operating state S2. When the state transitions to the operation state S2, the identification information indicating that the current state is the operation state S2 and that the previous state was the initial state S1 is stored in the nonvolatile storage element 12 that stores the state of the information processing apparatus. Write.

  The transition from the operation state S2 to the nap state S3 occurs at the start / stop switch operated by the user when there is an external power supply (T1).

  The transition from the operation state S2 to the hibernation state S4 uses the power of the internal power storage means 32, and when there is no external power supply, the start / stop switch 313 operated by the user and the internal power storage This occurs when the power stored in the means 32 decreases and it is determined that the operation state S2 cannot be maintained (T2).

  That is, when the transition is made to the operation state S2, the start / stop switch 313 operated by the user can transit only to the nap state S3 or the hibernation state S4. When power is supplied from the outside, the operation state S2 is changed to the nap state S3 (T1). At this time, identification information indicating that the current state is the nap state S3 and the previous state is the operation state S2 is written in the nonvolatile storage element 12 that stores the state of the information processing apparatus.

  Further, when the operation state S2 transits to the nap state S4, volatile information such as the internal storage device data 10, the LSI internal information 11, and the display memory data 101 is stored in the nonvolatile external storage device 2 respectively. Processing to store in the areas 21, 22, 211 may be performed.

  When operating with the power of the power storage means 32 such as an internal battery and no power is supplied from the outside, the state transitions from the operation state S2 to the hibernation state S4 in order to avoid power consumption in the nap state S3 (T2). At this time, identification information indicating that the current state is the hibernation state S4 and the previous state is the operation state S2 is written into the nonvolatile storage element 12 that stores the state of the information processing apparatus.

  When the information processing apparatus is shifted to the initial state S1 due to replacement or update of control software of the information processing apparatus such as the OS, the operation state S2 is shifted to the initial state S1 (T8). This transition can be realized by a process of invalidating information in the nonvolatile storage element 12 that stores the state of the information processing apparatus.

  When the information processing apparatus in the nap state S3 detects a change in the start / stop switch 313 operated by the user, the information processing apparatus transitions to the operation state S2 (T6). At this time, identification information indicating that the current state is the operation state S2 and the previous state is the nap state S3 is written in the nonvolatile storage element 12 that stores the state of the information processing apparatus.

  In the information processing apparatus in the nap state S3, when the power supply from the outside is cut off, the power of the power storage means 32 such as an internal battery is used to transition to the hibernation state (T3). At this time, identification information indicating that the current state is the hibernation state S4 and the previous state is the nap state S3 is written in the nonvolatile storage element 12 that stores the state of the information processing apparatus. The power of the power storage means 32 at this time is used until the process of storing volatile information in the external storage device 2 and the process of writing state transition information in the nonvolatile storage element 12 are completed.

  If the nap state S3 does not change after a predetermined time, the state transitions to the hibernation state S4 (T9). At this time, identification information indicating that the current state is the hibernation state S4 and the previous state is the nap state S3 is written in the nonvolatile storage element 12 that stores the state of the information processing apparatus. Thereby, the power consumption of the information processing apparatus which is not used for a long time can be reduced.

  When the information processing apparatus in the hibernation state S4 detects an external power supply, the information processing device transitions to the nap state S3 (T5). At this time, identification information indicating that the current state is the nap state S3 and the previous state is the hibernation state S4 is written in the nonvolatile storage element 12 that stores the state of the information processing apparatus.

  When the information processing apparatus in the hibernation state S4 detects a change in the start / stop switch 313 operated by the user, the external power is supplied if there is an external power supply, and the internal power if there is no external power supply. The power of the storage means 32 is used to make a transition to the operating state S2 (T4). At this time, identification information indicating that the current state is the operation state S2 and the previous state is the hibernation state S4 is written in the nonvolatile storage element 12 that stores the state of the information processing apparatus.

  After the transition from the hibernation state S4 to the nap state S3, when the external power supply is cut and the transition is made to the hibernation state S4, the internal storage device data 10, the LSI internal information 11, and the display memory data 101 are updated. Therefore, the process of storing these volatile information in the external storage device 2 is not performed, and the state transits to the hibernation state S4 (T3). This is identified by the fact that the information transitioned to the operation state S2 after the transition to the nap state S3 is not recorded in the nonvolatile storage element 12 that stores the state of the information processing apparatus.

  As an exceptional transition, if the state transition cannot be performed normally due to a soft error of the storage element in the nap state S3 or data corruption in the external storage device in the hibernation state S4, the state is forcibly set to the initial state. Transition (T10).

  The power supply circuit 31 uses the power supply line 42 when the start / stop control unit 312 detects a change in the start / stop switch 313 and when the external power detection unit 311 detects a change in power supply from the outside. Thus, power is supplied to the information processing apparatus main body electronic circuit 1. The power used at this time is selected from the power supplied from the outside or the power stored in the internal power storage means 32 by the power switching means 314.

  The external power detection unit 311 and the start / stop control unit 312 are configured to be operable as long as either the power of the internal power storage unit 32 or the externally supplied power is supplied.

  The information processing apparatus main body electronic circuit 1 to which the power is supplied checks the information of the nonvolatile storage element 12 that stores the state of the information processing apparatus and the states of the power supply circuit state output lines 43 and 44, and the internal state to be transited. And perform the necessary processing.

  In this process, in the transition from the operation state S2 to the nap state S3, power is supplied only to the volatile storage elements such as the internal storage device and the display memory and the control circuit necessary for maintaining the storage, and the internal information This is a process of stopping power supply to an electronic circuit not related to storage.

  In the transition from the operation state S2 or the nap state S3 to the hibernation state S4, volatile information such as the internal storage device data 10, the LSI internal information 11, and the display memory data 101 is transferred to each of the nonvolatile external storage devices 2. This is processing for stopping the power supply to the information processing apparatus main body electronic circuit 1 using the power cut signal 44, which is stored in the storage areas 21, 22, 211.

  The transition from the nap state S3 to the operation state S2 is a process of supplying power to all the information processing apparatus main body electronic circuits 1 and making the state usable by the user.

  The transition from the hibernation state S4 to the nap state S3 is a process of restoring the information stored in the respective storage areas 21, 22, 211 of the nonvolatile external storage device 2 to the internal storage device, the display memory, or the like. .

  In the transition from the hibernation state S4 to the operation state S2, the information stored in the respective storage areas 21, 22, 211 of the nonvolatile external storage device 2 is restored to the internal storage device, the display memory, etc. This is a process for supplying power to all the electronic circuit 1 of the apparatus main body and making it available to the user.

  As a result, when the external power supply can be received, the information processing apparatus is basically in the nap state S3, and therefore, there is a waiting time from the start by the start / stop switch 313 operated by the user until it can be used. An information processing apparatus that is shortened and easy to use can be realized.

  Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.

  FIG. 5 is an external perspective view schematically showing the external appearance of the information processing apparatus according to the second embodiment of the present invention.

  The information processing apparatus 5 includes a main body unit 50 including a CPU and a storage device, an information input unit 531, and a screen display unit 58. The main body 50 is provided with an operation interruption switch 533 and an external power supply operation unit 574, and is supplied with power from the outside through the power supply line 45. The external power supply operation unit 574 is a mechanical switch that determines whether to supply or shut off external power, and the information processing apparatus user normally keeps this switch on. A work interruption switch 533 for interrupting the operation of the information processing apparatus 5 and shifting to the nap state S3 is provided in the work interruption operation unit, which generates an interrupt signal to the main body unit 50. The transition from the nap state S3 to the operation state S2 is made by an input from the operation interruption switch 533 or the information input means 531.

  FIG. 6 is a functional block diagram schematically showing the structure of the information processing apparatus 5. This embodiment has a function to return to the state at the time of operation interruption and a function to return to the state at the time of start-up in case of failure to return to the state at the time of operation interruption for some reason And.

  The information processing apparatus 5 according to the second embodiment of the present invention includes at least an information processing apparatus body electronic circuit 50, a nonvolatile storage device 55, and a power supply unit 57. The information processing apparatus main body electronic circuit 50 includes a storage device control unit 51, a volatile storage device 52, and an operation interruption switch / information input unit 53. The volatile storage device 52 includes a main storage device 521 and a display memory 522, and device internal information 5211 is stored in the main storage device 521.

  The nonvolatile storage device 55 includes an area 552 for storing data in the volatile storage device and a start flag storage area 551 for storing a flag to be referred to during start processing.

  An area 552 for storing data in the volatile storage device of the nonvolatile storage device 55 is an area for storing information at the time of operation interruption, that is, a hibernation file region 5521 at the end of work, and an information processing device. An area for storing information at the time when the OS is activated, that is, a hibernation file area 5522 at the time of OS activation is prepared. In this specification, a portion in which information saved in the nonvolatile storage device is recorded is called a hibernation file.

  The power supply unit 57 includes at least two systems of a power supply line 421 to a part for holding a volatile storage device and its contents, and a power supply line 422 to the other part. The power supply line 422 to a portion other than the volatile storage device 52 and the portion for holding the contents thereof includes a power supply cutoff unit 571 that can be controlled by the information processing apparatus main body electronic circuit 50.

  A more detailed functional block configuration of the information processing apparatus 5 will be described with reference to FIG. The information processing apparatus 5 includes an information processing apparatus main body electronic circuit 50, a nonvolatile storage device 55, a power supply unit 57, and a screen display unit 58. The information processing apparatus main body electronic circuit 50 includes a storage device controller 51, a volatile storage device 52, and an operation interruption switch / information input means 53.

  The storage device control unit 51 in the information processing apparatus main body electronic circuit 50 has functions of a CPU 511, a BIOS ROM 512, a chip set 513 having functions of a memory controller and a bus controller, a super I / O, a keyboard controller, and an interrupt controller. The chip set 514 has a VGA controller 515.

  The volatile storage unit 52 includes a DRAM 521 serving as a main memory and a VRAM 522 serving as a display memory. The main memory 521 is provided with a device internal information storage area 5211 in which device internal information is stored. Yes.

  The operation interruption switch / information input means 53 includes a keyboard 531, a chattering prevention circuit 532, and an operation interruption switch 533 that drops a voltage normally set to high to the GND level.

  The nonvolatile storage device 55 includes a hard disk 553 and an RTC / CMOS memory 554. The hard disk 553 is provided with a hibernation file area when the operation is interrupted and a hibernation file area 5521 when the OS is started. An activation flag storage area 551 is provided in the RTC / CMOS memory 554.

  The power supply unit 57 includes a power supply cutoff unit 571 made of FET, a DC / DC converter 572 that works as a voltage conversion unit, an AC / DC converter 573 that works as a rectification unit, and a mechanical switch 574 that works as an external power supply operation switch. Prepare. Among the power supply lines 421 and 422, the volatile storage device 52 and the power supply line 422 other than for holding the contents are connected from the DC / DC converter 572 to the storage device control unit via the power supply cutoff unit (FET) 571. 51, the hard disk 553 of the non-volatile storage device 55, and each part of the screen display device 58.

  The states that can be taken by this embodiment and the transition conditions thereof will be described with reference to FIG. In this embodiment, there are a stop state S11, an operation state S2, a nap state S3, a hibernation state S4, and a hibernation file creation state S5.

  The stop state S11 is a state where no external power is supplied to the information processing apparatus 5 and the external power supply operation switch 574 is off. This is the state when the information processing apparatus 5 is first turned on, and external power is supplied and the switch 574 is turned on to start the startup process. After the boot process, a hibernation file at the time of booting the OS is created, and a transition is made to the operating state S2 (T11).

  The operation state S2 is a state in which the information processing apparatus 5 can be used for work. When the user finishes or interrupts the work, the operation interruption switch 53 is turned on. Thereby, the state of the information processing apparatus 5 transits to the hibernation file creation state S5 (T12).

  The hibernation file creation state (S5) is a state in which the information in the volatile storage device 52 when the operation is interrupted is saved to the nonvolatile storage device 55. If there is any external operation such as a key input during evacuation, the evacuation operation is interrupted and the operation state S2 is changed (T13). When all information in the volatile storage device 52 is saved and the creation of the hibernation file is completed, the hibernation information is stored in the activation flag storage area 551 of the nonvolatile storage device 55, and then the state transits to the nap state S3 (T15). ). If the OS activation hibernation is given priority according to the user's instruction, the save process is not performed and the hibernation information is stored in the activation flag storage area 551, and then the state transitions to the nap state S3.

  The nap state S3 does not stop the power supply to the parts related to the volatile storage device 52, but cuts off the power to the part unrelated to the function of returning to the state at the time of the operation interruption such as the screen display unit 58. State.

  The user treats this state as a normal power-off state. In the volatile storage device 52, the information at the time when the operation interruption switch 533 is turned on is maintained as it is, and if there is an external operation such as keyboard 531 input, power is immediately supplied to the part that was disconnected. Can be resumed, transition to the operation state S2, and work can be resumed (T14).

  When the external power supply to the information processing device 5 is stopped during the nap state S3, the information processing device 5 transitions to the hibernation state S4 (T16). In the hibernation state S4, unlike the stop state S11, the external power supply operation switch 574 remains on, and a hibernation file exists in the nonvolatile storage device 55. Also, the start flag has a value different from that in the stop state.

  When power supply from the outside is resumed during the hibernation state S4, the information processing apparatus 5 immediately starts the activation process and transitions to the nap state S3 (T17). This startup process normally restores the information at the time of the operation interruption in the nonvolatile storage device 55 saved in the hibernation creation state S5 to the volatile storage device 52. If this fails, or when the OS is started In the case where the reproduction is prioritized, the hibernation file created in the transition (T11) from the stop state S11 to the operation state S2 is restored.

  The start-up process for realizing the transitions (T11) and (T17) from the stop state S11 / hibernation state S5 will be described using the flowchart of FIG. It should be noted that a program for performing the activation process exists in the BIOS ROM 512.

  First, the flow of activation from the stop state S11 (transition (T11)) will be described. When the startup process is started, the CPU 511 accesses the address assigned to the BIOS ROM 512, and first recognizes the capacity of the main memory in the information processing apparatus 5 and checks the hard disk in accordance with the program written here. Checking and initialization processing are performed (ST1).

  Next, with reference to the activation flag F recorded in the RTC / CMOS memory 551, it is determined whether the activation is from the stop state S11, the activation from the hibernation state S4, or the reboot (ST2). ). When starting from the stop state S11, the start flag F has an initial value “0”. In the start flag check (ST2), when the start flag F is “0” or “2”, the process proceeds to step ST3. When the activation flag F is other than “0” and “2”, the process branches to step ST5.

  FIG. 10 shows possible values of the activation flag F and their functions. F = 0 is an initial value or a stopped state. F = 1 indicates a normal hibernation state, and indicates a state in which the hibernation file is stored on the hard disk and is normally terminated. F = 2 is OS boot hibernation, and indicates a state in which the OS is booted using the hibernation file at the time of booting the OS. F = 3 indicates a hibernation file creation start state, which is the transition (T12) state in FIG. 8, and is set to F = 1 at the normal end. F = 4 indicates a hibernation file return state, which is the transition (T14) state of FIG.

  In step ST2, when the activation flag F is “0” or “2”, it is determined whether the activation flag F is “0” or “2” (ST3). When the activation flag F is “0” Initialize the hibernation file area at the end of the previous work (ST4), and then initialize the hibernation file area at the time of OS activation (ST10), and then enter the OS activation process (ST11). At the time when the OS is started, the information in the volatile storage device 52 at the time of OS startup is saved to the area initialized in step ST4 in the nonvolatile storage device 55, and a hibernation file at the time of OS startup is created. (ST12). At this time, the process shifts to the OS side when the OS is started. However, if the OS cannot call the system BIOS program at the start point, the process may be shifted to the system BIOS side by a specific hardware interrupt. . After completion of the hibernation file, the error flag is checked (ST13). However, the flag is not set in the processing so far, and the process shifts to the operation state S2 (ST14).

  In step ST3, when the startup flag F is “2”, the hibernation file at the time of OS startup is checked (ST8), and when there is an abnormality in the file, an error flag is set (ST9), and the hibernation at the time of OS startup is performed. The file area is initialized (ST10). Thereafter, the same processing as when the activation flag F is “0” is performed.

  Next, the case of activation from hibernation state S4 (transition (T17)) will be described. After checking each device (ST1), there are two cases: branching to normal hibernation, and performing OS boot hibernation if the user has selected to prioritize the hibernation file at the time of booting the OS. As a result of checking the activation flag F in step ST2, if the activation flag F is other than “0” or “2”, it is checked whether the activation flag F is “1” (ST5). As a result of the check in step ST5, when the activation flag F is other than “1”, an error flag is set (ST6), and the hibernation file area at the end of the previous work is initialized (ST7), and then the above-described step ST8 is performed. Migrate to

  When performing normal hibernation, the activation flag F is “1”, the first activation flag is checked (ST2), the activation flag F branches to other than “0” or “2”, and The save state of the hibernation file is checked by the activation flag check in (ST5). If F = 1, the hibernation file at the end of the previous work has been normally created, so a file check is performed in step ST15. If it is normal, the activation flag F = 4 is set (ST16), and information that the hibernation file is restored is stored. In step ST17, the hibernation file is restored to the volatile storage device 52. After that, since the error flag is not raised, the state transits to the nap state S3 (ST20).

  When it is determined that the file is abnormal in step ST15 for some reason, such as when the file is damaged or the hardware configuration of the information processing apparatus has been changed, such as adding memory, or when the activation flag is checked in step ST5 If a value other than F = 1 is detected, an error flag is set (ST6), and the hibernation file area at the end of the previous work is initialized again (ST7). The error flag takes a value of 0 without error and 1 with error, and is one of the variables of the startup processing program set on the main memory of the volatile memory, not the nonvolatile storage device such as the startup flag storage area. One. Thereafter, a hibernation file check (ST8) at the time of OS startup is performed. If normal, the hibernation file is restored to the volatile storage device, an error message is displayed (ST19), and then the state transitions to the nap state S3.

  If it is determined in step ST8 that it is abnormal, an error flag is set (ST9) (however, since the error flag is already set in step ST6, the value does not actually change) After initializing the hibernation file area at the time of OS startup (ST10), OS startup processing is performed in the same manner as the startup from the stopped state S11 (ST11). When the OS is activated, information in the volatile storage device is saved to an initialized area in the nonvolatile storage device, and a hibernation file at the time of OS activation is created (ST12).

  Here, similarly to the activation from the stop state S11, when the OS cannot call the system BIOS program when the OS is activated, the processing may be shifted to the system BIOS by a specific hardware interrupt. At this time, the process shifts to the OS side when the OS is started. However, if the OS cannot call the system BIOS program at the start point, the process may be shifted to the system BIOS side by a specific hardware interrupt. .

  After that, an error flag check (ST13) is performed, and since an error flag is set in steps ST6 and ST9, an error message is displayed (ST19), and a transition to a nap state is made (ST20).

  If the user gives priority to the hibernation file at the time of OS startup, the process branches to F = 2 in the first startup flag check (ST2), and also branches to F = 2 in the next startup flag check (ST3). As a result, the process related to hibernation at the end of the previous work is skipped, and the process immediately proceeds to the hibernation file check (ST8) when the OS is started. Thereafter, the same processing is performed. When the hibernation file at the time of OS startup is restored to the volatile storage device, the value of the startup flag is not changed.

  Rebooting the information processing apparatus is realized by setting the activation flag F of the nonvolatile storage device to an initial value 0 and reproducing the activation process from the stop state S11.

  The flow in the hibernation file creation state S5 is as shown in FIG. The program that performs this process exists in the BIOS ROM 512, as does the program that performs the startup process. When the operation interruption button 533 is pressed during the operation state S2, this process is started (transition (T12)).

  First, the processing is terminated for all programs that are currently accessing the nonvolatile storage device 55 (ST31). Next, the address in the vector table of the keyboard interrupt and the operation interruption switch interrupt is rewritten to the address where the program for suspending the hibernation file creation and returning to the operation state is arranged (ST32). Next, it is determined whether or not priority is given to the hibernation file at the time of OS startup (ST33). If the activation flag F is “2”, the hibernation file at the time of the current operation interruption is not created, and the state immediately shifts to the nap state S3 (transition (T15)). If it is determined in step ST33 that the activation flag F is other than “2”, the activation flag F = 3 is set (ST34), and information on the start of hibernation file creation is stored in the activation flag area. Thereafter, the current contents of the volatile storage device are saved in the nonvolatile storage device, and a hibernation file at the time of operation interruption is created (ST35).

  When the keyboard interruption and the operation interruption switch interruption do not occur and the creation of the hibernation file is completed, the activation flag F = 1 is set and the information is recorded in the activation flag storage area (ST36), and the process shifts to the nap state S3. (ST37) (Transition (T15)).

  If a keyboard interrupt signal or an interrupt signal from the operation interruption switch is detected during the processing after step ST32, the process branches to step ST38 according to the rewritten vector address. The rewritten vector address is changed to the original address (ST38), the hibernation file creation is interrupted, and the operation state S2 is entered (transition (T13)) (ST39).

  The memory map in this embodiment will be described with reference to FIG. 12 schematically showing the memory map. When the operation interrupt button is pressed, the hibernation file creation state in the ROM area is determined according to the operation interrupt button interrupt address ADDR2 described in the interrupt vector table (the part where each interrupt vector address near the top address of the memory is written). Program processing begins.

  The addresses of the interrupt vector table rewritten in step ST32 are the operation interrupt button interrupt address ADDR2 and the keyboard interrupt address ADDR1. The keyboard interrupt address ADDR1 indicates the head address of the key code acquisition program in the ROM area. Both the addresses ADDR1 and ADDR2 are rewritten to the head address ADDR3 of the hibernation file creation state interruption processing program. As a result, when the keyboard or the operation interruption switch is pressed during the state of creating the hibernation file and an interruption occurs, the process goes to ADDR3. After the interrupt vector address rewritten by the process of step ST38 is returned to the original ADDR1 and ADDR2 in the process from there, the process returns to the previous process at the time when the interruption to the hibernation file creation state program is applied, and the operation state S2 Migrate to

  Processing in the nap state S3 will be described with reference to FIG. A program for performing this process exists in the BIOS ROM 512. After the transition to the nap state S3, the information processing apparatus waits for an operation interruption switch interrupt or a keyboard interrupt (ST41). As long as no interrupt occurs, the process does not proceed from step ST41. When an interrupt occurs, the activation flag F is checked to determine whether or not OS activation hibernation is prioritized (ST42). If the activation flag F is “2”, that is, if the OS activation hibernation, the operation state S2 is immediately shifted to (ST44) (transition T14). If the activation flag F is not “2”, the activation flag F is set to “4”, that is, return to the hibernation file (ST43), and the process proceeds to the operation state S2 (ST44).

  FIG. 14 schematically shows the relationship between the transition of each state and the change of the activation flag F. In the stop state S11, the initial value of the start flag F is set to “0”, and after the start process, the process proceeds to the operation state S2. At this time, the value of the activation flag F remains “0”.

  In the operation state S2, the activation flag F can be rewritten to F = 2 when priority is given to OS activation hibernation, and to F = 0 when it is reactivated (in the case of reactivation, the activation process is performed as it is). ). In the operation state S2, in addition to F = 0 and 2, four values of F = 4 after restoration of the hibernation file and F = 3 when the hibernation file creation is interrupted and the operation state S2 is restored can be taken.

  In the operation state S2, regardless of the state of any activation flag, pressing the operation interruption switch 533 causes the process to proceed to the hibernation file creation state S5.

  When the operation interruption switch 533 is pressed, according to the processing of FIG. 11, if the activation flag F is “2”, it goes to the nap state S3 as it is, otherwise the activation flag F becomes “3” at the start of hibernation file creation first. The hibernation file creation state S5 is set, and after the hibernation file creation is completed, the activation flag F is set to “1”, and the process shifts to the nap state S3.

  In the nap state S3, when the transition to the operation state S2 is performed, if the activation flag F is “1”, the activation flag F is set to “4” and the operation state S2 is restored. When the activation flag F is “2”, the operation state S2 is returned as it is.

  When shifting to the hibernation state S4, the value of the activation flag F of “1” or “2” is carried over as it is. When power supply from the outside is resumed in the hibernation state S4, in the case of normal hibernation where the activation flag F is “1”, activation processing is performed, and the activation flag F after activation processing is set to “4” to make a nap When the OS shifts to the state S3 and the OS startup hibernation with the startup flag F being “2”, the startup process is performed and the transition to the nap state S3 is performed, and the startup flag F remains “2” and the operation state S2 is entered.

  The relationship between the power consumption and the transition of each state of the information processing apparatus will be described with reference to FIG. In this figure, the power consumption is plotted on the vertical axis and the time is plotted on the horizontal axis, and the relationship between the power consumption and each state transition of the information processing apparatus is shown. The power consumption is 0 at the time of the stop state S11. From this point, when the external power supply is started and the external power supply operation switch is turned on to start the startup process, the same power consumption as in the operation state S2 is maximized. The power consumption remains at the maximum even when the operation interruption switch is turned on and in the hibernation file creation state S5. After the hibernation file creation process, the power consumption is reduced by the portion where the power supply is cut off when the nap state S3 is entered. When the supply of external power stops, the power consumption naturally becomes 0, and the information processing apparatus enters the hibernation state S4. When the supply of external power resumes, the information processing apparatus immediately enters the start-up process from hibernation state S4, and power consumption is maximized at this point. Thereafter, since the transition to the nap state S3 is made at the end of the activation process, the power consumption is suppressed, and the state of the information processing apparatus returns to the same state as when the operation is interrupted.

  A third embodiment of the present invention will be described with reference to FIG. In this embodiment, the information processing apparatus is a notebook information processing apparatus 5 '. The notebook information processing apparatus 5 ′ includes a main body unit 50 ′ and a screen display unit 58 ′. In the notebook type information processing apparatus 5 ′, an operation interruption switch 533 ′ is arranged near the base of the movable part connecting the main body 50 ′ and the screen display unit 58 ′. When the screen display unit 58 ′ is closed, the switch is turned on. Pressed. As a result, when the user interrupts or finishes the operation, the user can simplify the procedure by closing the screen display unit 58 ′, and can complete the operation of resuming the operation by opening the screen display unit 58 ′. Can be better.

The functional block diagram which shows the structure of the information processing apparatus (operation state) concerning the 1st Embodiment of this invention. The flowchart explaining the state transition of the information processing apparatus concerning the 1st Embodiment of this invention. The functional block diagram which shows the structure of the information processing apparatus (nap state) concerning the 1st Embodiment of this invention. The functional block diagram which shows the structure of the information processing apparatus (hibernation state) concerning the 1st Embodiment of this invention. The perspective view which showed typically the external appearance of the information processing apparatus of this invention. The functional block diagram which shows the function structure of the principal part of the information processing apparatus concerning the 2nd Embodiment of this invention. The functional block diagram in more detail which shows the function structure of the information processing apparatus concerning the 2nd Embodiment of this invention. The figure explaining the state which the information processing apparatus concerning the 2nd Embodiment of this invention can take, and its transition conditions. The flowchart of the starting process from the stop state / hibernation state in 2nd Embodiment. The figure explaining the value of a starting flag, and its function. The flowchart in the hibernation file creation state in 2nd Embodiment. Explanatory drawing which represents typically the structure of the memory map in 2nd Embodiment. The flowchart in the nap state in 2nd Embodiment. Explanatory drawing which showed typically the relationship between the transition of each state of 2nd Embodiment, and the change of a starting flag. The figure explaining the relationship between power consumption and the transition of each state of information processing apparatus. The external view of the notebook type information processing apparatus concerning the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing apparatus main body electronic circuit 10 Internal storage device data 101 Display memory data 11 LSI internal information 12 Information processing device internal state storage unit 2 External storage device 21 Internal storage device data storage area 211 Display memory data storage area 22 LSI internal information storage area 3 Power supply control unit 31 Power supply circuit 311 External power detection unit 312 Start / stop control unit 313 Start / stop switch 314 Power switching unit 32 Power storage unit 41 Power disconnection signal 42 Power supply line 421 Power supply line 422 Power supply line 43 Power supply circuit state output line 44 Power supply circuit state output line 45 External power supply line 5 Information processing device 50 Division processor main body electronic circuit 51 Storage device control unit 511 CPU
512 BIOS ROM
513 Chipset (memory controller, bus controller)
514 Chipset (Super I / O and others)
515 VGA controller 52 Volatile storage device 521 Main memory 522 Video memory 53 Operation interruption switch / information input means 531 Keyboard 533 Operation interruption switch 55 Non-volatile storage device 551 Startup flag storage area 552 in the non-volatile storage device In the non-volatile storage device The area 5521 for storing information in the volatile storage device in the storage area 5521 in the area for storing information in the volatile storage device in the nonvolatile storage device at the end of the work 5522 Information in the volatile storage device in the nonvolatile storage device Hibernation file creation area 553 at the time of OS startup in the area for storing the hard disk 554 RTC / CMOS memory 57 power supply unit 571 power supply cutoff unit 574 external power supply operation switch 571 power cutoff unit (FET)
572 DC / DC converter 574 External power supply operation switch 573 AC / DC converter S1 initial state S2 operation state S5 hibernation file creation state S3 hibernation state S4 hibernation state S11 stop state T1 transition from operation state to nap state T2 operation state to hibernation Transition from state to state T3 Transition from hibernation state to hibernation state T4 Transition from hibernation state to operation state T5 Transition from hibernation state to nap state T6 Transition from hibernation state to operation state T7 Transition from initial state to operation state T8 Transition from operation state to initial state T9 Transition from nap state to hibernation state T10 Transition from hibernation state / nap state to initial state T11 Transition from stop state to operation state T12 Transition from operation state to hibernation file creation state T13 Operation status from hibernation file creation status Transition to state T14 Transition from nap state to operation state T15 Transition from hibernation file creation state to nap state T16 Transition from nap state to hibernation state T17 Transition from hibernation state to nap state ADDR1 Start address of key code acquisition program ADDR2 Start address of hibernation file creation status program ADDR3 Start address of hibernation file creation status interruption processing program

Claims (3)

  In an information processing apparatus having a volatile storage device and a non-volatile storage device that records information on an internal state during operation, the internal state of the information processing device changes between an operation state, a nap state, and a hibernation due to a change in external conditions. An information processing apparatus characterized by changing to a state or an operating state, a nap state, a hibernation state, and a hibernation file creation state.   The information processing apparatus according to claim 1, wherein the information processing apparatus in the nap state transitions to a hibernation state if the nap state continues even after a predetermined time has elapsed. Information is recorded in the volatile storage device during operation, information during operation stored in the volatile storage device is saved to the nonvolatile storage device when the operation is interrupted, and the saved information is saved in the nonvolatile storage device when the operation is resumed. The information processing apparatus according to claim 1, wherein the information processing apparatus is restored to a volatile storage device.

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