JP2006301786A - Device and program for appropriately confirming layout - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout appropriate confirmation device for detecting circuit configurations in which wiring congestion is likely to occur so that any failure in wiring arrangement can be preliminarily extracted. <P>SOLUTION: This layout appropriate configuration device is provided with a logical stage/cell number investigating part 2 for inputting a network list 1, and for obtaining a relation between the number of cells existing on a path from all input ports to all output ports and a logical stage by using connection information between configuration sections described in the network list and a circuit configuration investigating part 7 for determining the circuit configuration and wiring congestion of the network list 1 from the relation between the number of cells and logical stage obtained by the logical stage/cell number investigating part 2 based on a circuit configuration determination parameter 8 for regulating a typical relation between configuration sections in circuit configurations where wiring congestion occurs, and for outputting the determination result as layout appropriate confirmation information. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a layout appropriateness confirmation device for confirming layout suitability and a program for causing a computer to function as this device.

  For example, Patent Document 1 and Patent Document 2 disclose conventional techniques for efficiently performing automatic placement and routing of LSIs. These use a netlist and a cell library to simulate an environment that is close to the state of being actually placed and routed on a chip.

JP 2002-217299 A JP 9-45776 A

  In order to execute the simulation as in the conventional technique described above, detailed physical parameters are required up to the cell size, chip size, and wiring width. Moreover, a huge amount of simulation time is required for the simulation that handles these detailed data.

  As described above, in the conventional technique, it is not possible to know whether or not the placement and routing is possible unless a simulation of the placement and routing that takes a long time is performed. For this reason, when it is found that the layout cannot be performed after the placement and routing simulation, there is a problem that a large process delay occurs due to rework.

  This invention was made to solve the above problems, and by detecting a circuit structure that is likely to cause wiring congestion by investigating the netlist before actually simulating the placement and routing, It is an object of the present invention to obtain a layout appropriateness confirmation apparatus capable of extracting in advance problems occurring during placement and routing, and a program for causing a computer to function as this apparatus.

  The layout appropriateness confirmation apparatus according to the present invention inputs a netlist and uses a connection information between components described in the netlist to obtain a relationship between components existing on a path from the input to the output. Based on the relationship between the structural elements determined by the netlist structure research unit and the judgment information that defines the relationship between the structural investigation part and the structural elements characteristic of the circuit structure causing wiring congestion, the circuit structure of the netlist and its And a circuit structure investigation unit that determines wiring congestion and outputs a determination result as layout appropriateness confirmation information.

  According to the present invention, a netlist structure investigation unit that inputs a netlist and obtains a relationship between components existing on a path from the input to the output by using connection information between the components described in the netlist; Based on the determination information that defines the relationship between the structural elements characteristic of the circuit structure causing wiring congestion, the netlist circuit structure and its wiring congestion are determined from the relationship between the structural elements obtained by the netlist structure investigation unit. Since it has a circuit structure investigation unit that makes judgments and outputs judgment results as layout appropriateness confirmation information, modules that are likely to cause wiring congestion can be detected before actual layout is performed, and the layout suitability of the modules can be confirmed The layout design work period can be shortened.

Embodiment 1 FIG.
The layout appropriateness confirmation apparatus according to the first embodiment executes the following processing.
(1) Using the module netlist as an input, the relationship between the logic stage and the number of cells is investigated for all paths from the input to the output of the module, and the relationship between the logic stage and the number of cells is output.
(2) Based on the relationship between the logic stage and the number of cells obtained as a result of the investigation, the circuit structure is investigated using the circuit structure determination parameter.
(3) As a result of investigation of the circuit structure, a determination result as to whether or not the module is highly likely to cause congestion in the placement and routing is output.

  FIG. 1 is a block diagram showing a configuration for obtaining the relationship between the logic stage and the number of cells in the layout appropriateness confirmation apparatus according to Embodiment 1 of the present invention. The logical stage / cell number examining unit (net list structure examining unit) 2 according to the first embodiment includes a netlist arranging unit 4, a netlist circulating unit 5, and 1st to Nth stage cell number counters 6-1 to 6-N. Consists of The netlist alignment unit 4 aligns the cells described in the input module netlist 1 in a pyramid shape. The netlist circulating unit 5 reads information on the arranged module netlists, exhaustively tours the circuit network described in the module netlist 1, and outputs information on the logic stages. The 1st to Nth stage cell number counters 6-1 to 6-N are counters that are provided corresponding to the respective logical stages output from the netlist circulating unit 5 and count the number of cells in each logical stage.

  FIG. 2 is a block diagram showing a configuration for investigating the circuit structure of the layout appropriateness confirmation apparatus according to the first embodiment. The circuit configuration investigation unit 7 according to the first embodiment includes a parameter expansion unit 9 and a parameter match determination unit 10. The parameter expansion unit 9 reads the circuit structure determination parameter (determination information) 8 written in a specific format, and expands (compiles) it into an instruction that can be used by the parameter match determination unit 10. In accordance with the instruction generated by the parameter expansion unit 9, the parameter match determination unit 10 determines whether or not the investigation result 3 on the relationship between the logical stage and the number of cells generated by the logical stage / cell number inspection unit 2 matches the input parameter. judge.

  The logic stage / cell number examining unit 2 and the circuit configuration examining unit 7 described above are realized on the computer by causing the computer to read the layout appropriateness confirmation processing program according to the present invention and controlling its operation. be able to. In addition, the functions of the logic stage / cell number examining unit 2 and the circuit configuration examining unit 7 are executed as separate program modules by computers capable of exchanging information with each other, and these computers perform the logic stage / cell number examining unit. 2 and the circuit configuration examining unit 7 may be separately embodied. The module netlist 1, the investigation result 3 on the relationship between the logic stage and the number of cells, and the circuit structure determination parameter 8 are stored in, for example, a storage device equipped in the computer.

  In the following description, the configuration of the computer itself that embodies the layout appropriateness confirmation apparatus of the present invention and the basic functions thereof can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. The detailed description is omitted because it is not directly related to the essence of the present invention.

Next, the operation will be described.
FIG. 3 is a flowchart showing the operation of the layout appropriateness confirmation apparatus according to the first embodiment. The operation will be specifically described with an example in which the module netlist shown in FIG. 4 is input to the apparatus shown in FIG. . First, the module shown in FIG. 4 will be described.

  FIG. 4 shows a netlist of modules whose main functions are selectors of 2to1. Cells 1-1 to 1-8 are cells of the first logic stage, cells 2-1 to 2-5 are cells of the second logic stage, and cells 3-1 to 3-3 are the third stage. This is a cell in the logic stage. Solid lines connecting IN0 to IN12, OUT0 to OUT4, and cells represent wiring.

  Also, as in the cell 2-5, when the number of logic stages is different when counted from one of the two inputs and when counted from the other input, the number of logic stages becomes large, or Sort in advance to be smaller. In FIG. 4, sorting is performed so that the number of logical stages is increased.

  When placing and routing a netlist having a circuit structure as shown in FIG. 4, it is natural to place it in a pyramid shape, but in reality it is a pyramid shape due to chip size constraints, timing constraints, and pin location constraints. Often not placed. For this reason, it is known that the wiring is twisted and detoured, and the wiring is likely to be congested.

Next, the layout appropriateness confirmation process will be described with the module netlist as the module netlist 1.
The logic stage / cell number examining unit 2 of the layout appropriateness confirmation apparatus according to the first embodiment inputs the net list 1 having the above-described circuit structure (step ST1). In the logic stage / cell number examining unit 2, the internal netlist arranging unit 4 arranges cells in a pyramid shape as shown in FIG. 4 from the connection relation of the cells described in the input module netlist 1.

  Subsequently, the logic stage and the number of cells are checked by the net list circulating unit 5 and the cell number counters 6-1 to 6-N of the logic stage / cell number checking unit 2 (step ST2). First, the netlist circulating unit 5 reads information on the module netlist arranged by the netlist arranging unit 4 and comprehensively circulates the circuit network described in the module netlist 1 for each logical stage. Output information about. For example, information about cells included in each logic stage is output.

  The information for each logical stage output from the netlist circulating unit 5 is input to the cell number counters 6-1 to 6-N of the corresponding logical stage, and the number of cells in each logical stage is counted. In the example of FIG. 4, the first-stage cell number counter 6-1 to the third-stage cell number counter 6-3 count the number of cells in each logic stage. In this way, the investigation result 3 of the relationship between the logic stage and the number of cells is obtained (step ST3).

  The results of investigating the relationship between the logic stage and the number of cells in the module shown in FIG. 4 are as follows. This can be represented by a graph indicating that the number of cells in the logical stage of the eye is 3.

  Next, the circuit structure investigation unit 7 inputs the investigation result 3 on the relationship between the logic stage and the number of cells, and executes the circuit structure investigation based on this (step ST4). First, the parameter expansion unit 9 of the circuit structure investigation unit 7 reads the circuit structure determination parameter 8 written in a specific format, and expands (compiles) it into an instruction that can be used by the parameter match determination unit 10. The circuit structure determination parameter 8 is a parameter that defines a characteristic circuit structure in a module that is likely to cause wiring congestion with respect to the number of cells, and serves as a determination reference for a determination command to be executed by the parameter match determination unit 10.

  In accordance with the instruction generated by the parameter expansion unit 9, the parameter match determination unit 10 determines whether the investigation result 3 of the relationship between the logical stage and the number of cells generated by the logical stage / cell number inspection unit 2 matches the circuit structure determination parameter 8. Determine whether or not. In the circuit structure shown in FIG. 4, the circuit structure determination parameter 8 matches, for example, the parameter “ratio of the number of cells in the Nth stage and the (N + 1) th stage is approximately 2: 1”. Determined as a module.

In the case of the example in FIG. 4, assuming that the number of cells in the Nth and N + 1th stages is Sn and Sn + 1, respectively, if there are two or more consecutive Ns satisfying the following formula (1), the circuit structure determination parameter 8 It is determined that it matches the above-mentioned parameter.
(Sn + 1) × 0.75 ≦ Sn / 2 ≦ (Sn + 1) × 1.25 (1)

  In this way, the parameter match determination unit 10 compares the characteristics of the graph shown in FIG. 5 with the circuit structure determination parameters, and may cause wiring congestion when there is a parameter that matches the characteristics of the graph. The determination result of the module having a high value is output as information for checking the proper layout (step ST5).

  As described above, according to the first embodiment, the netlist 1 is input, and on the paths from all the input ports to all the output ports using the connection information between the components described in the netlist 1 Based on the logic stage / cell number investigating unit 2 for obtaining the relationship between the number of existing cells and the logic stage, and the circuit structure determination parameter 8 for defining the relationship between the constituent parts characteristic of the circuit structure causing the wiring congestion, A circuit structure investigation unit 7 that determines the circuit structure of the netlist 1 and its wiring congestion from the relationship between the number of cells obtained by the stage / cell number investigation unit 2 and the logical stage, and outputs a determination result as layout appropriateness confirmation information; Therefore, it is possible to identify a module that is likely to cause wiring congestion before the actual layout is performed. Thereby, the layout suitability of the module can be confirmed in advance, and as a result, the layout design period can be shortened.

  In the first embodiment, an example in which the ratio of the number of cells in the Nth stage and the (N + 1) th stage is about 2: 1 is used to determine a module whose main function is a 2to1 selector as shown in FIG. As described above, the parameters are not limited to those described above as long as a parameter capable of determining a module whose main function is a 2to1 selector can be created.

  In addition to the module whose main function is a 2to1 selector as shown in FIG. 4, if there is a module having a circuit structure that has a high possibility of causing wiring congestion, parameters for determining the circuit structure are set to the logic stage and the number of cells. If the same procedure as the procedure of creating the relationship and determining the circuit of FIG. 4 is executed, it is possible to determine whether or not the module is highly likely to cause wiring congestion.

  Furthermore, various parameters related to the circuit structure that are highly likely to cause wiring congestion are stored in the circuit structure determination parameter 8, and the parameter match determination unit 10 selects modules that are likely to cause wiring congestion for each parameter. Each determination may be executed.

Embodiment 2. FIG.
The layout appropriateness confirmation apparatus according to the second embodiment executes the following processing.
(1) Using the module netlist as an input, the relationship between the logic stage and the number of wires is investigated for all paths from the module input to the output, and the relationship between the logic stage and the number of wires is output.
(2) Based on the relationship between the logic stage and the number of wires obtained as a result of the investigation, the circuit structure is investigated using the circuit structure determination parameter.
(3) As a result of investigation of the circuit structure, a determination result as to whether or not the module is highly likely to cause congestion in the placement and routing is output.

  FIG. 6 is a block diagram showing a configuration for obtaining the relationship between the logic stage and the number of wires in the layout appropriateness confirmation apparatus according to the second embodiment of the present invention. The logical stage / wire number examining unit (net list structure examining unit) 2A according to the second embodiment includes a netlist aligning unit 4, a netlist circulating unit 5a, and 1st to Nth stage wire number counters 11-1 to 11-N. Consists of The netlist aligning unit 4 executes the same processing as that shown in the first embodiment. The net list circulating unit 5a reads information on the arranged module net list, comprehensively circulates the circuit network described in the module net list 1, and outputs information on the logic stage including the wires of each logic stage. . The 1-Nth stage wire number counters 11-1 to 11-N are provided corresponding to the respective logic stages output from the netlist circulating unit 5a, and are counters that count the number of wires of each logic stage.

  FIG. 7 is a block diagram showing a configuration for investigating the circuit structure of the layout appropriateness confirmation apparatus according to the second embodiment. The circuit configuration investigation unit 7A according to the second embodiment includes a parameter expansion unit 9a and a parameter match determination unit 10a. The parameter expansion unit 9a reads the circuit structure determination parameter (determination information) 13 written in a specific format, and expands (compiles) it into an instruction that can be used by the parameter match determination unit 10a. In accordance with the instruction generated by the parameter expansion unit 9a, the parameter match determination unit 10a determines whether or not the investigation result 12 on the relationship between the logical stage and the number of wires generated by the logical stage / wire number inspection unit 2A matches the input parameter. judge.

  The logical stage / wire number examining unit 2A and the circuit configuration examining unit 7A described above are realized on the computer by causing the computer to read the layout appropriateness confirmation processing program according to the present invention and controlling the operation thereof. be able to. Further, the functions of the logic stage / wire number investigation unit 2A and the circuit configuration investigation unit 7A are executed as separate program modules by computers capable of exchanging information with each other. You may embody 2A and the circuit structure investigation part 7A separately. The module netlist 1, the investigation result 12 on the relationship between the logic stage and the number of wires, and the circuit structure determination parameter 13 are stored, for example, in a storage device equipped in the computer.

  In the following description, the configuration of the computer itself that embodies the layout appropriateness confirmation apparatus of the present invention and the basic functions thereof can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. The detailed description is omitted because it is not directly related to the essence of the present invention.

Next, the operation will be described.
FIG. 8 is a flowchart showing the operation of the layout appropriateness confirmation apparatus according to the second embodiment, which will be specifically described by taking an example in which the module netlist shown in FIG. 9 is input to the apparatus shown in FIG. . First, the module shown in FIG. 9 will be described.

  FIG. 9 is a diagram showing a netlist of a module whose main function is a 2to1 selector, similar to the module of FIG. 4 of the first embodiment. Cells 1-1 to 1-8 are cells in the first logic stage, cells 2-1 to 2-4 are cells in the second logic stage, and cells 3-1 and 3-2 are in the third stage. This is a cell in the logic stage. Solid lines connecting IN0 to IN12, OUT0 to OUT4, and cells represent wiring.

  Also, the circuit structure as shown in FIG. 9 has almost the same structure as that in FIG. 4. Therefore, when arranging and wiring a netlist having this connection relationship, chip size restrictions, timing restrictions, pin positions, etc. In many cases, it is not arranged in a pyramid shape due to restrictions. For this reason, twisting and detouring of the wiring occur, and wiring congestion is likely to occur.

Next, the layout appropriateness confirmation process will be described with the module netlist as the module netlist 1.
The logic stage / wire number examining unit 2A of the layout appropriateness confirmation apparatus according to the second embodiment inputs the netlist 1 having the above-described circuit structure (step ST1a). In the logic stage / wire number examining unit 2A, the internal netlist arranging unit 4 arranges cells in a pyramid shape as shown in FIG. 9 from the connection relation of the cells described in the inputted module netlist 1.

  Subsequently, the logic stage and the number of wires are checked by the net list circulating unit 5a of the logic stage / wire number checking unit 2A and the wire number counters 11-1 to 11-N (step ST2a). First, the net list circulating unit 5a reads the information about the module net list arranged by the net list arranging unit 4, and comprehensively circulates the circuit network described in the module net list 1 so that each logic stage has a logical stage. Output information about. For example, information about wires connected to cells included in each logic stage is output.

  Information for each logical stage output from the netlist circulating unit 5a is input to the wire number counters 11-1 to 11-N of the corresponding logical stage, and the number of wires of each logical stage is counted. Here, the value obtained by counting the wires input to the cells of each logic stage is defined as the number of wires. In the example of FIG. 9, the wire indicated by the bold solid line in the figure is counted as the wire for the first logic stage, and the wire indicated by the thick dashed line is counted as the wire for the second logic stage. The wires indicated by the thin two-dot broken lines are counted as wires for the third logic stage. In this way, the investigation result 12 of the relationship between the logic stage and the number of wires is obtained (step ST3a).

  The investigation result of the relationship between the logic stage and the number of wires in the module shown in FIG. 9 is that the number of wires in the first logic stage is 24 as shown in FIG. This can be represented by a graph indicating that the number of wires in the logical stage of the eye is six.

  Next, the circuit structure investigation unit 7A inputs the investigation result 12 on the relationship between the logic stage and the number of wires, and executes the circuit structure investigation based on this (step ST4a). First, the parameter expansion unit 9a of the circuit structure investigation unit 7A reads the circuit structure determination parameter 13 written in a specific format, and expands (compiles) it into an instruction that can be used by the parameter match determination unit 10a. The circuit structure determination parameter 13 is a parameter that defines a characteristic circuit structure in a module that is likely to cause wiring congestion with respect to the number of wires, and serves as a determination reference for a determination command to be executed by the parameter match determination unit 10a.

  In accordance with the instruction generated by the parameter expansion unit 9a, the parameter match determination unit 10a determines whether the investigation result 12 of the relationship between the logical stage and the number of wires generated by the logical stage / wire number inspection unit 2A matches the circuit structure determination parameter 13. Determine whether or not. In the case of the circuit structure as shown in FIG. 9, since it matches the parameter “ratio of the number of wires in the N-th stage and the (N + 1) -th stage is approximately 2: 1”, it is determined that the module is highly likely to cause wiring congestion.

In the case of the example in FIG. 9, assuming that the numbers of wires in the Nth and N + 1th stages are Sn and Sn + 1, respectively, if there are two or more consecutive Ns satisfying the following equation (2), the circuit structure determination parameter 13 It is determined that it matches the above-mentioned parameter.
(Sn + 1) × 0.75 ≦ Sn / 2 ≦ (Sn + 1) × 1.25 (2)

  As described above, the parameter match determination unit 10a compares the characteristics of the graph shown in FIG. 10 with the circuit structure determination parameter 13, and may cause wiring congestion when there is a parameter that matches the characteristics of the graph. The determination result of the module having a high value is output as information for checking the proper layout (step ST5a).

  As described above, according to the second embodiment, the logic stage / wire number examining unit 2A obtains the relationship between the logic stage and the number of wires existing on the path from the input port to the output port of the netlist 1. The logic determined by the logic stage / wire number investigating unit 2A based on the circuit structure determination parameter 13 that defines the relationship between the number of logic stages and the number of wires characteristic of the circuit structure causing wiring congestion. Since the circuit structure of the netlist 1 and its wiring congestion are determined from the relationship between the stage and the number of wires and the determination result is output as layout appropriateness confirmation information, there is a high possibility of causing wiring congestion before the actual layout is performed. Modules can be specified. Thereby, the layout suitability of the module can be confirmed in advance, and as a result, the layout design period can be shortened.

  In the second embodiment, an example in which the ratio of the number of wires in the Nth stage and the (N + 1) th stage is about 2: 1 is used for the determination of a module whose main function is a 2to1 selector as shown in FIG. As described above, the parameters are not limited to those described above as long as a parameter capable of determining a module whose main function is a 2to1 selector can be created.

  In addition to the module whose main function is a 2to1 selector as shown in FIG. 9, if there is a module having a circuit structure that is highly likely to cause wiring congestion, the parameters for determining the circuit structure are set to the logic stage and the number of wires. If the same procedure as the procedure of creating the relationship and determining the circuit of FIG. 9 is executed, it is possible to determine whether or not the module is highly likely to cause wiring congestion.

Embodiment 3 FIG.
The layout appropriateness confirmation apparatus according to the third embodiment executes the following processing.
(1) Using the module net list as an input, the relationship between the number of wires and the logical wire length is investigated for all paths from the input to the output of the module, and the relationship between the number of wires and the logical wire length is output.
(2) Based on the relationship between the number of wires and the logical wire length obtained as a result of the investigation, the circuit structure is investigated using the circuit structure determination parameter.
(3) As a result of investigation of the circuit structure, a determination result as to whether or not the module is highly likely to cause congestion in the placement and routing is output.

  FIG. 11 is a block diagram showing a configuration for obtaining the relationship between the number of wires and the logical wire length of the layout appropriateness confirmation apparatus according to the third embodiment of the present invention. The wire number / logical wire length checking unit (net list structure checking unit) 2B according to the third embodiment includes a net list alignment / labeling unit 14, a net list circulating unit 5b, and a wire number counter having a logical wire length of 1 to N. 15-1 to 15-N. The netlist alignment / labeling unit 14 arranges the cells described in the input module netlist 1 in a pyramid shape, and labels the logical stages to which the cells belong.

  The netlist circulating unit 5b reads information on the arranged module netlists and comprehensively traverses the circuit network described in the module netlist 1, and for example, from the cell A of the label N to the subsequent label (N + M) When moving to cell B, the difference M between the logic levels of the labeled cells is output as the logic wire length. The wire number counters 15-1 to 15-N are counters that respectively count the number of wires corresponding to each logical wire length output from the netlist circulating unit 5b.

  FIG. 12 is a block diagram showing a configuration for investigating the circuit structure of the layout appropriateness confirmation apparatus according to the third embodiment. The circuit configuration investigation unit 7B according to the third embodiment includes a parameter expansion unit 9b and a parameter match determination unit 10b. The parameter expansion unit 9b reads the circuit structure determination parameter (determination information) 17 written in a specific format, and expands (compiles) it into an instruction that can be used by the parameter match determination unit 10b. In accordance with the instruction generated by the parameter expansion unit 9b, the parameter match determination unit 10b determines whether the investigation result 16 of the relationship between the number of wires and the logical wire length generated by the wire number / logical wire length investigation unit 2B matches the input parameter. Determine whether.

  The above-described wire number / logical wire length survey unit 2B and circuit configuration survey unit 7B are realized on the computer by reading the program for checking the appropriateness of the layout according to the present invention and controlling the operation thereof. can do. In addition, the functions of the wire number / logical wire length investigation unit 2B and the circuit configuration investigation unit 7B are executed as separate program modules in computers capable of exchanging information with each other. The investigation unit 2B and the circuit configuration investigation unit 7B may be embodied separately. The module netlist 1, the investigation result 16 of the relationship between the number of wires and the logical wire length, and the circuit structure determination parameter 17 are stored in, for example, a storage device equipped in the computer.

  In the following description, the configuration of the computer itself that embodies the layout appropriateness confirmation apparatus of the present invention and the basic functions thereof can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. The detailed description is omitted because it is not directly related to the essence of the present invention.

Next, the operation will be described.
FIG. 13 is a flowchart showing the operation of the layout appropriateness confirmation apparatus according to the third embodiment. The operation will be specifically described with an example in which the module netlist shown in FIG. 14 is input to the apparatus shown in FIG. . First, the module shown in FIG. 14 will be described.

  FIG. 14 shows a module having a circuit configuration having N logic stages, and a wire 18 indicated by a thick line in the figure is the cells 1-1 to X (1 <X) arranged in the first logic stage. <N) Wire connected to the configuration unit 19 in the logic stage of the first stage, from the cell 1-2 arranged in the logic stage of the first stage to the configuration unit 19 in the logic stage of Y (X <Y <N) stage The wire to connect is shown. Note that the number of wires is the same as that counted in the second embodiment.

  The wires 18 that connect the components of the logic stages that are separated from each other, such as the 1st stage to the X stage and the 1st stage to the Y stage, are often control signals like the select signal of the selector, and the layout is scattered. Wiring also tends to be pulled and scattered. Therefore, as shown in FIG. 14, if there are a large number of wires having a long logical wire length, wiring congestion is likely to occur.

Next, the layout appropriateness confirmation process will be described with the module netlist as the module netlist 1.
The wire number / logical wire length examining unit 2B of the layout appropriateness confirmation apparatus according to the third embodiment inputs the netlist 1 having the above-described circuit structure (step ST1b). In the wire number / logical wire length investigation unit 2B, the internal netlist alignment / labeling unit 14 arranges cells in a pyramid shape as shown in FIG. 14 from the connection relationship of the cells described in the input module netlist 1. Align and label the logical stage to which the cell belongs.

  Subsequently, the number of wires and the logical wire length are investigated by the net list circulating unit 5b of the wire number / logical wire length examining unit 2B and the wire number counters 15-1 to 15-N (step ST2b). First, the net list circulating unit 5b reads the information about the module net list arranged by the net list arranging / labeling unit 14, reads the information about the module net list after the arrangement, and the circuit described in the module net list 1 While exhaustively traversing the network, the difference between the logic levels of the labeled cells is output as the logic wire length.

  In the example of FIG. 14, when the netlist circulating unit 5b moves the search from the cell 1-1 of the label 1 to the cell of the subsequent label X + 1, the logical stage difference (X) of the labeled cell is logically calculated. Output as wire length. Further, when the search is moved from the cell 1-2 of the label 1 to the cell of the label X + Y + 1 at the subsequent stage, the difference (X + Y) of the logic stage of the cell is output as the logic wire length.

  Information for each logical wire length output from the netlist circulating unit 5b is input to the corresponding wire count counters 15-1 to 15-N of the logical wire length, and the number of wires of each logical wire length is counted. In the case of handling the example of FIG. 14, the wire number counter 15-1 having a logical wire length of 1 to the wire number counter 15-3 having a logical wire length of 3 counts the number of wires in each logical wire length. In this way, the investigation result 16 of the relationship between the number of wires and the logical wire length is obtained (step ST3b).

  As shown in FIG. 15, the investigation result of the relationship between the number of wires of the module and the logical wire length shown in FIG. Can be represented by a graph indicating that the number of wires of X is 1 and the number of wires of logical wire length (X + Y) is 1.

  Next, the circuit structure investigation part 7B inputs the investigation result 16 of the relationship between the number of wires and the logical wire length, and executes the circuit structure investigation based on this (step ST4b). First, the parameter expansion unit 9b of the circuit structure examining unit 7B reads the circuit structure determination parameter 17 written in a specific format, and expands (compiles) it into an instruction that can be used by the parameter match determination unit 10b. The circuit structure determination parameter 17 is a parameter that defines a characteristic circuit structure in a module that is highly likely to cause wiring congestion with respect to the number of wires of the logical wire length, and is a determination criterion for a determination instruction to be executed by the parameter match determination unit 10b. It becomes.

  In accordance with the instruction generated by the parameter expansion unit 9b, the parameter match determination unit 10b matches the circuit number determination parameter 17 with the result 16 of the relationship between the number of wires / logical wire length generated by the wire number / logical wire length checking unit 2B. It is determined whether or not to do. In the circuit structure shown in FIG. 14, if a parameter “N (N> 1) or more where the logical wire length exceeds X (X> 1)” is set in the circuit structure determination parameter 17, It is determined as a module that matches the parameters and has a high possibility of causing wiring congestion.

  As described above, the parameter match determination unit 10b performs comparison between the characteristics of the graph shown in FIG. 15 and the circuit structure determination parameter 17, and may cause wiring congestion when there is a parameter that matches the characteristics of the graph. The determination result of the module having a high value is output as information for checking the proper layout (step ST5b).

  As described above, according to the third embodiment, the number-of-wires / logical-wire-length examining unit 2B has a relationship between the number of wires existing on the path from the input port to the output port of the netlist 1 and the logical wire length. Based on the circuit structure determination parameter 17 that defines the relationship between the number of wires characteristic of the circuit structure causing wiring congestion and the logical wire length, the circuit structure investigation unit 7B determines the number of wires / logical wire length investigation unit 2B. The circuit structure of the netlist 1 and its wiring congestion are determined from the relationship between the number of wires obtained and the logical wire length, and the determination result is output as layout appropriateness confirmation information. Therefore, the wiring congestion before the actual layout is performed. Modules that are likely to wake up can be identified. Thereby, the layout suitability of the module can be confirmed in advance, and as a result, the layout design period can be shortened.

  In the third embodiment, an example in which “there are more than N (N> 1) logical wire lengths exceeding X (X> 1)” is shown for module determination as shown in FIG. However, the present invention is not limited to the parameters described above as long as a parameter capable of determining a module as shown in FIG. 14 can be created.

Embodiment 4 FIG.
The layout appropriateness confirmation apparatus according to the fourth embodiment executes the following processing.
(1) Using a module netlist as an input, for all paths from module input to output, the relationship between the logic stage and the number of cells, the relationship between the logic stage and the number of wires, and the number of wires and the logic wire length Investigate relationships and output the results of these investigations.
(2) Based on each relation obtained as a result of the investigation, the circuit structure is investigated using the circuit structure determination parameter.
(3) Based on the investigation result of each circuit structure, a determination result obtained by further comprehensively determining a determination result as to whether or not the module is highly likely to cause congestion in the placement and routing is output.

  The layout appropriateness confirmation apparatus according to the fourth embodiment of the present invention includes a logic stage / cell number examining unit 2 shown in the first embodiment, a logic stage / wire number examining unit 2A shown in the second embodiment, and wires. It has a survey unit (net list structure survey unit) composed of a number / logical wire length survey unit 2B. These investigation units 2, 2A, 2B perform the same investigation process as that in the first to third embodiments on the module net list input to the layout appropriateness confirmation apparatus according to the fourth embodiment, respectively, to determine the logic stage and the number of cells. Investigation result 3 of the relationship, investigation result 12 of the relationship between the logical stage and the number of wires, and investigation result 16 of the relationship between the number of wires and the logical wire length.

  FIG. 16 is a block diagram showing a configuration for investigating the circuit structure of the layout appropriateness confirmation apparatus according to the fourth embodiment of the present invention. The circuit configuration investigation unit 7C according to the fourth embodiment includes the circuit investigation unit 7 shown in the first embodiment, the circuit investigation unit 7A shown in the second embodiment, and the circuit investigation unit shown in the third embodiment. 7B and the parameter match comprehensive determination unit 20. The parameter match comprehensive determination unit 20 weights which determination results are important with respect to the determination results output by the circuit structure examining units 7, 7A, and 7B, and outputs the determination results.

  The above-described investigation unit including the investigation units 2, 2A and 2B and the circuit configuration investigation unit 7C allow the computer to read the layout appropriateness confirmation processing program according to the present invention and control the operation thereof. Can be realized. Further, the functions of the survey units 2, 2A, 2B and the circuit configuration survey unit 7C are executed as separate program modules on computers capable of exchanging information with each other, and the survey units 2, 2A, 2B and The circuit configuration examining unit 7C may be separately embodied. The module net list 1, investigation results 3, 12, and 16, and circuit structure determination parameters 8, 13, and 17 are stored in, for example, a storage device equipped in the computer.

  In the following description, the configuration of the computer itself that embodies the layout appropriateness confirmation apparatus of the present invention and the basic functions thereof can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. The detailed description is omitted because it is not directly related to the essence of the present invention.

Next, the operation will be described.
FIG. 17 is a flowchart showing the operation of the layout appropriateness confirmation apparatus according to the fourth embodiment. The operation will be described with reference to this figure.
When the logic stage / cell number examining unit 2, the logic stage / wire number examining unit 2A, and the wire number / logic wire length examining unit 2B of the layout appropriateness confirmation apparatus according to the fourth embodiment input the module net list 1 (steps). ST1c) In the same manner as in the first to third embodiments, the relationship between the logic stage and the number of cells, the number of wires and the logic wire length are investigated (step ST2c-1, step ST2c-2, step ST2c-3). The respective survey results 3, 12, and 16 are obtained (step ST3c-1, step ST3c-2, step ST3c-3).

  Next, the circuit structure investigation part 7C inputs each investigation result 3, 12, and 16 and performs a circuit structure investigation based on these (step ST4c). The circuit structure investigation unit 7, 7A, 7B in the circuit structure investigation unit 7C matches each investigation result 3, 12, 16 with the circuit structure determination parameters 8, 13, 17 in the same manner as in the first to third embodiments. It is determined whether or not to do. In this way, the parameter match determination units 10, 10 a, and 10 b perform comparison between the characteristics of the circuit structure specified by the respective investigation results 3, 12, and 16 and the circuit structure determination parameters 8, 13, and 17. When there is a parameter that matches the characteristics of the graph, the determination results of the modules that are likely to cause wiring congestion are output.

  Determination results from the parameter match determination units 10, 10 a, and 10 b are input to the parameter match comprehensive determination unit 20. In the parameter match comprehensive determination unit 20, a final determination for checking the appropriateness of the layout is performed by adding weights to which determination results are regarded as important with respect to the determination results output by the respective circuit structure inspection units 7, 7A, 7B. The result is output (step ST5c).

  As described above, according to the fourth embodiment, the processing of the first to third embodiments is executed by outputting the determination results obtained by combining the processes described in the first to third embodiments. Compared with the circuit structure, it is possible to detect a circuit structure that is likely to cause wiring congestion more accurately.

  In the fourth embodiment, the example in which the determination results obtained by the processing described in the first to third embodiments are combined is shown. However, other components in the circuit structure that may cause wiring congestion It is also possible to set a circuit structure determination parameter that defines the relationship between them and obtain a relationship other than those in the first to third embodiments to create layout appropriateness confirmation information.

  The cells in the first to fourth embodiments include those that are instantiated on the layout.

It is a block diagram which shows the structure which calculates | requires the relationship between the logic stage of the layout appropriateness confirmation apparatus by Embodiment 1 of this invention, and the number of cells. It is a block diagram which shows the structure which investigates the circuit structure of the layout appropriateness confirmation apparatus by Embodiment 1. FIG. 4 is a flowchart showing an operation by the layout appropriateness confirmation apparatus according to the first embodiment. It is a figure which shows an example of the circuit structure specified by a module net list. It is a graph of the investigation result of the relationship between a logic stage and the number of cells. It is a block diagram which shows the structure which calculates | requires the relationship between the logic stage of the layout appropriateness confirmation apparatus by Embodiment 2 of this invention, and the number of wires. It is a block diagram which shows the structure which investigates the circuit structure of the layout appropriateness confirmation apparatus by Embodiment 2. FIG. 10 is a flowchart illustrating an operation performed by the layout appropriateness confirmation apparatus according to the second embodiment. It is a figure which shows an example of the circuit structure specified by a module net list. It is a graph of the investigation result of the relationship between a logic stage and the number of wires. It is a block diagram which shows the structure which calculates | requires the relationship between the number of wires of the layout appropriateness confirmation apparatus by Embodiment 3 of this invention, and a logical wire length. It is a block diagram which shows the structure which investigates the circuit structure of the layout appropriateness confirmation apparatus by Embodiment 3. FIG. 10 is a flowchart illustrating an operation performed by the layout appropriateness confirmation apparatus according to the third embodiment. It is a figure which shows an example of the circuit structure specified by a module net list. It is a graph of the investigation result of the relationship between the number of wires and the logical wire length. It is a block diagram which shows the structure which investigates the circuit structure of the layout appropriateness confirmation apparatus by Embodiment 4 of this invention. 14 is a flowchart illustrating an operation performed by the layout appropriateness confirmation apparatus according to the fourth embodiment.

Explanation of symbols

1 module net list, 1-1 to 1-8, 2-1 to 2-5, 3-1 to 3-3 cells, 2 logic stages / cell number investigation section (net list structure investigation section), 2A logic stages, Wire number investigation part (net list structure investigation part), 2B Wire number / logical wire length investigation part (net list structure investigation part), 3 Logical stage and cell number investigation results, 4 Net list alignment part, 5, 5a, 5b Netlist traveling unit, 6-1 to 6-N cell counter, 7, 7A, 7B, 7C circuit structure examining unit, 8, 13, 17 circuit structure determining parameter (determination information), 9, 9a, 9b parameter expanding unit 10, 10a, 10b Parameter match determination unit, 11-1 to 11-N Wire number counter, 12 Investigation result of relationship between logical stage and wire number, 14 Netlist alignment / labeling unit, 15-1 to 15-N Number of wires Counter, 16 a wire number and findings of the logical wire length relationship, 18 wire, 19 components, 20 parameters match the overall judgment section.

Claims (7)

A netlist structure investigation unit that inputs a netlist and obtains a relationship between components existing on a path from the input to the output using connection information between the components described in the netlist;
Based on the determination information that defines the relationship between the components characteristic of the circuit structure causing the wiring congestion, the netlist circuit structure and the wiring congestion thereof are determined from the relationship between the components obtained by the netlist structure investigation unit. A layout appropriateness confirmation apparatus comprising: a circuit structure investigation unit that determines and outputs the determination result as layout appropriateness confirmation information. The netlist structure investigation unit obtains the relationship between the number of cells and the logical stage existing on the path from the input to the output as the relationship between the components of the netlist,
The circuit structure investigation unit determines the relationship between the logic stage and the number of cells obtained by the netlist structure investigation unit based on the determination information that defines the relationship between the logic stage and the number of cells characteristic of the circuit structure causing wiring congestion. 2. The layout appropriateness confirmation apparatus according to claim 1, wherein a circuit structure of the net list and wiring congestion thereof are determined. The netlist structure research unit obtains the relationship between the number of wires and the logical stage existing on the path from the input to the output as the relationship between the components of the netlist,
The circuit structure investigation unit determines the relationship between the logic stage and the number of wires obtained by the net list structure investigation unit based on the determination information that defines the relationship between the number of logic stages and the number of wires characteristic of the circuit structure causing wiring congestion. 2. The layout appropriateness confirmation apparatus according to claim 1, wherein a circuit structure of the net list and wiring congestion thereof are determined. The netlist structure investigation unit obtains the relationship between the number of wires existing on the path from the input to the output and the logical wire length as the relationship between the components of the netlist,
The circuit structure investigation unit determines the number of wires and the logical wire length obtained by the netlist structure investigation unit based on the determination information that defines the relationship between the number of wires characteristic of the circuit structure causing wiring congestion and the logical wire length. 2. The layout appropriateness confirmation apparatus according to claim 1, wherein the circuit structure of the net list and the wiring congestion thereof are determined from the relationship. The netlist structure investigation unit obtains the relationship between a plurality of components existing on the path from the input to the output as the relationship between the components of the netlist,
The circuit structure investigation unit determines whether the netlist structure investigation unit obtains the relationship between the plurality of components based on the determination information that defines the relationship between the plurality of components characteristic of the circuit structure causing the wiring congestion. 2. The layout appropriateness confirmation apparatus according to claim 1, wherein the circuit structure of the netlist and its wiring congestion are respectively determined, and the result of comprehensively determining these determination results is output as layout appropriateness confirmation information. The netlist structure investigation unit obtains the relationship between the number of cells or instances and the logical stage, the relationship between the number of wires and the logical stage, and the relation between the number of wires and the logical wire length as the relationship between a plurality of components.
The circuit structure investigation unit determines the relationship between the logical stage and the number of cells, the relationship between the logical stage and the number of wires, and the relationship between the number of wires and the logical wire length, which are characteristic of the circuit structure that causes wiring congestion. Based on the information, the network structure of the netlist and its wiring congestion are respectively determined from the relationship between the plurality of components obtained by the netlist structure investigation unit, and the weighting corresponding to the importance is given to these determination results The layout appropriateness confirmation apparatus according to claim 5, wherein a result of comprehensive determination is output by assigning a value. A program that causes a computer to function as the net list structure examining unit according to any one of claims 1 to 6 and the circuit structure examining unit according to any one of claims 1 to 6.

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