JP2006301748A - Information recording reproduction system, information recording reproduction device, and information recording reproduction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manage a signal processing system for recording and reproducing asynchronous SDI data by a Ref synchronous signal system independently from a frame synchronizer as in a conventional system, and to record and reproduce SDI data asynchronous to Ref synchronous signal. <P>SOLUTION: The data recording reproduction device 101 comprises an ENC substrate 31, a main CPU 23 managing recording and reproduction of information based on the Ref synchronous signal; an ENC sub-CPU 38 controlling the ENC substrate 31 to record and reproduce SDI data asynchronous to the Ref synchronous signal; and dual port RAMs 59 and 69 writing control information Dc from the main CPU 23 to the ENC sub-CPU 38 based on the Ref synchronous signal, reading it synchronously with Input synchronous signal, writing communication information Cd from the ENC sub-CPU 38 to the main CPU 23 synchronously with the Input synchronous signal, and reading it based on the Ref synchronous signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention records an audio / video data encoded and compressed stream data in a predetermined data format in a large-capacity storage device, or reproduces the data stream data from the storage device and decodes / decompresses the AV server The present invention relates to an information recording / reproducing system, an information recording / reproducing apparatus, and an information recording / reproducing method suitable for application to a system.

  Specifically, communication information from a first control system that manages recording and reproduction of information based on a reference synchronization signal to a second control system that records and reproduces information of an asynchronous input signal source is based on the reference synchronization signal. For communication for reading and writing in synchronization with the input signal source, and for writing communication information from the second control system to the first control system in synchronization with the input signal source and reading based on the reference synchronization signal And a second control system for recording / reproducing control of information of an asynchronous input signal source can be managed from the first control system based on the reference synchronization signal, and is asynchronous with respect to the reference synchronization signal. It was made possible to record / reproduce information of various input signal sources.

  In recent years, a synchronous recording / reproducing AV server is often used when editing video and audio information in broadcasting stations and video and audio information distribution systems. The AV server has a data recording / reproducing device, a data storage device (RAID), and the like. In a data recording / reproducing apparatus, at the time of data recording, video and audio information is encoded and compressed by a data compression standard such as MPEG (encoding process). Header information such as a frame index is added to the encoded and compressed video and audio data to form stream data of a predetermined data format, which is stored in a data recording device. According to this type of synchronous recording / reproducing AV server system, stream data is recorded in a data storage device in a unique data format.

  At the time of data reproduction, stream data is read from the data storage device to the data recording / reproducing device, and the stream data is decoded and expanded (decoding process). The video and audio data after decoding / decompression is converted into video and audio information. The video and audio information is output to a video display device and an audio output device. In such an AV server, data is recorded and reproduced in a time slot managed in synchronization with the AV input signal.

  In relation to this type of AV server, Patent Document 1 discloses a data recording / reproducing apparatus and a method of using time slots. According to this data recording / reproducing apparatus, when data is recorded and / or reproduced using a non-linear accessible RAID (recording medium), data input / output and recording / reproducing means that do not require real-time characteristics are used. Asynchronous transfer means for executing data transfer is provided, and this asynchronous transfer means does not transfer data between the recording / reproducing means and any one of the input unit and the output unit for executing input / output of data requiring real-time characteristics. In the time slot determined to be, data transfer is performed with the recording / reproducing means.

  When the data recording / reproducing apparatus is configured in this way, even when all the input / output ports of the AV server are operating, it is possible to connect each port and the RAID without preparing a time slot other than the time slot assigned to each port. The processing that could not be executed simultaneously with the data transfer can be performed.

  On the other hand, Patent Document 2 discloses an asynchronous input type recording / reproducing apparatus and a signal input method. According to this recording / reproducing apparatus, in the AV data input unit, the operation of the circuit preceding the storage means (bank memory) used as the frame synchronizer and the write operation to the storage means are synchronized with the input signal from the outside. The data is read from the storage means and transferred to the recording / reproducing means in synchronization with the reference synchronization signal. When the recording / reproducing apparatus is configured in this way, an AV signal asynchronous with the reference video signal can be directly recorded on the AV server.

Japanese Unexamined Patent Publication No. 2000-299835 (FIG. 1 on page 6) Japanese Unexamined Patent Publication No. 2000-307986 (pages 4 to 5)

  Incidentally, the AV server according to the conventional example has the following problems.

  i. Since a synchronous recording / reproducing AV server such as that disclosed in Patent Document 1 requires a reference synchronous input as an input signal source, in order to be able to handle an asynchronous input AV signal, either externally or internally. A frame synchronizer for absorbing phase jitter between the AV input signal and the reference synchronization signal (reference) must be provided.

  ii. According to the asynchronous input type recording / reproducing apparatus as shown in Patent Document 2, a bank memory for absorbing input phase jitter is arranged for each input / output port, and a CPU is arranged in each bank memory to manage jitter. Must. For this reason, when an AV server having a plurality of input / output ports is to be configured, a structure for negotiating between the bank memory management CPUs and writing AV data to the RAID is required, which complicates the server structure itself.

  iii. Even when an AV server combining Patent Document 1 and Patent Document 2 is to be configured, control from the reference synchronous signal system to the asynchronous input signal system is possible if the bank memory address is communicated for each frame. When transferring information, there is a risk of data corruption.

  iv. As a solution described above, a method of absorbing jitter by using a FIFO memory for passing control information between the reference synchronous signal system and the asynchronous input signal system is conceivable. However, since a certain amount of data must be stored in the FIFO memory and then extracted, it may take time to transmit control information to the information output system.

  iv. In addition, since the allowable amount of jitter absorption is determined by the amount of information stored there with respect to the total memory capacity (stored information amount) of the FIFO, the phase gradually increases over a long time in an asynchronous input signal system. When the flowing phase shift is tens of frames or hundreds of frames, it cannot be handled.

  v. Therefore, if the asynchronous input signal fluctuates with respect to the reference synchronization signal, control information may not be transmitted or received, or a large amount of control information may be transferred and the control information may be lost. Such a problem may occur when the control information is notified from the reference synchronization signal system to the asynchronous input signal system and when the control information is notified from the asynchronous input signal system to the reference synchronization signal system.

  Therefore, the present invention solves such a conventional problem, and a signal processing system for recording / reproducing information of an asynchronous input signal source without depending on a frame synchronizer as in the conventional system is used as a reference synchronization signal. An information recording / reproducing system, an information recording / reproducing apparatus, and an information recording / reproducing method capable of recording and reproducing information of an input signal source asynchronous with respect to a reference synchronizing signal system And

  The above-described problem includes an information recording / reproducing apparatus including a data storage device that stores stream data in a predetermined data format, and an information recording / reproducing device that is connected to the data storage device and records and / or reproduces stream data. The information recording / reproducing unit, the first control unit for managing the recording / reproducing of information based on the reference synchronization signal, and the information recording / reproducing so as to record / reproduce information of the input signal source asynchronous to the reference synchronizing signal A second control unit for controlling the unit, and communication information from the first control unit to the second control unit is written based on the reference synchronization signal, read in synchronization with the input signal source, and second control Information recording / reproducing system comprising: a communication memory for writing communication information from the communication unit to the first control unit in synchronization with an input signal source and reading out based on a reference synchronization signal It is solved by.

  According to the information recording / reproducing system of the present invention, in the recording / reproducing apparatus connected to the data storage device, for example, when recording stream data of a predetermined data format in the data storage device, the communication memory is the reference Write and input communication information based on a reference synchronization signal from a first control unit that manages recording and reproduction of information based on a synchronization signal to a second control unit that controls recording and reproduction of information of an asynchronous input signal source Read in synchronization with the signal source. In addition, the memory writes communication information from the second control unit to the first control unit in synchronization with the input signal source and reads out based on the reference synchronization signal.

  Therefore, the second control unit for recording / reproducing control of the information of the asynchronous input signal source can be managed by the first control unit based on the reference synchronization signal. Thereby, the information recording / reproducing apparatus can record / reproduce information of the input signal source asynchronous to the reference synchronizing signal.

  An information recording / reproducing apparatus according to the present invention includes a first control unit that manages recording / reproduction of information based on a reference synchronization signal, and a second controller that controls recording / reproduction of information of an input signal source that is asynchronous with respect to the reference synchronization signal. The communication information from the control unit and the first control unit to the second control unit is written based on the reference synchronization signal, read out in synchronization with the input signal source, and the first control from the second control unit And a communication memory for writing communication information to the unit in synchronization with an input signal source and reading out based on a reference synchronization signal.

  According to the information recording / reproducing apparatus of the present invention, when recording stream data of a predetermined data format in the data storage system, the communication memory manages the information recording / reproduction based on the reference synchronization signal. The communication information from the control unit to the second control unit for recording / reproducing control of the asynchronous input signal source information is written based on the reference synchronization signal and read out in synchronization with the input signal source. In addition, the memory writes communication information from the second control unit to the first control unit in synchronization with the input signal source and reads out based on the reference synchronization signal.

  Therefore, the second control unit for recording / reproducing control of the information of the asynchronous input signal source can be managed by the first control unit based on the reference synchronization signal. Thereby, the information recording / reproducing apparatus can record / reproduce information of the input signal source asynchronous to the reference synchronizing signal.

  In the information recording / reproducing method according to the present invention, information recording / reproducing is managed based on the reference synchronization signal in the first control system, and information of the input signal source asynchronous to the reference synchronization signal is managed in the second control system. Recording / reproducing, writing communication information from the first control system to the second control system in the memory based on the reference synchronization signal, reading out from the memory in synchronization with the input signal source, and from the second control system to the first The communication information to the control system is written in the memory in synchronization with the input signal source and is read out from the memory based on the reference synchronization signal.

  According to the information recording / reproducing method of the present invention, when the stream data of a predetermined data format is recorded in the data storage system, the second control system for recording / reproducing information of the asynchronous input signal source is used as the reference synchronization signal. Can be managed from the first control system. Therefore, in the information recording / reproducing system, it is possible to record / reproduce information of the input signal source asynchronous to the reference synchronizing signal.

  According to the information recording / reproducing system of the present invention, from the first control unit that manages the recording / reproducing of information based on the reference synchronization signal to the second control unit that controls recording / reproducing information of the asynchronous input signal source. The communication information is written on the basis of the reference synchronization signal and is read in synchronization with the input signal source. In addition, communication information from the second control unit to the first control unit is written in synchronization with the input signal source and read out based on the reference synchronization signal.

  With this configuration, the second control unit that controls recording / reproduction of the information of the asynchronous input signal source can be managed by the first control unit based on the reference synchronization signal. Therefore, it is possible to record / reproduce information of an input signal source that is asynchronous with respect to the reference synchronization signal. In addition, it is not necessary to prepare a frame synchronizer as in the conventional method. As a result, the information recording / reproducing system can be sufficiently applied to the AV server system.

  According to the information recording / reproducing apparatus and the information recording / reproducing method of the present invention, the first control unit that manages the recording / reproducing of information based on the reference synchronization signal performs the recording / reproducing control of the information of the asynchronous input signal source. Communication information to the control unit 2 is written based on the reference synchronization signal and read in synchronization with the input signal source. Further, a memory for writing communication information from the second control unit to the first control unit in synchronization with the input signal source and reading out based on the reference synchronization signal is provided.

  With this configuration, the second control unit that controls recording / reproduction of the information of the asynchronous input signal source can be managed by the first control unit based on the reference synchronization signal. Therefore, it is possible to record / reproduce information of an input signal source asynchronous with respect to the reference synchronization signal. In addition, it is not necessary to prepare a frame synchronizer as in the conventional method. As a result, the information recording / reproducing apparatus and the information recording / reproducing method can be sufficiently applied to the AV server system.

  Next, an embodiment of the information recording / reproducing system, information recording / reproducing apparatus and information recording / reproducing method according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of an AV server system 100 as an embodiment according to the present invention.
The AV server system 1 shown in FIG. 1 constitutes an example of an information recording / playback system, and audio / video stream data (AV stream data) is transmitted at a broadcasting station or video / sound (including audio and music) information distribution station. It is written and recorded in a storage device, and / or AV stream data is read from the data storage device and reproduced.

  The AV server system 1 includes a video recording / reproducing apparatus (hereinafter referred to as “AV server 100”) and a control terminal apparatus 200. The AV server 100 receives recording control of the control terminal device 200 at the time of data recording, and inputs video and sound material information (AV input) from a data supply system such as a broadcasting device and a video and sound information distribution device and performs an encoding process. To do. Additional data is added to the encoded data to form stream data of a predetermined data format. This stream data is recorded and held.

  In addition, the AV server 100 receives the reproduction control of the control terminal device 200 at the time of data reproduction, and reads the stream data of a predetermined data format previously recorded and held. The stream data of the predetermined data format read here is decoded. The decoded data is output (AV output) to a data demand system such as a broadcasting device or video and sound information distribution device. The AV server 100 is connected to the network 500 via the HUB 400, and is configured to input / output AV stream data of a predetermined data format from the network 500. This is because the AVS server 10 can record and manage the file format data such as the MXF (Material Exchange Format) file format and the AVI format as much as possible, giving priority to the accessibility from the network 500.

  FIG. 2 is a block diagram illustrating an internal configuration example of the AV server 100. The AV server 100 shown in FIG. 2 includes, for example, one personal computer for file system (file manager) (hereinafter referred to as FM personal computer 80), a personal computer for network interface (hereinafter referred to as NetIF personal computer 90), and four data sets. The recording / reproducing apparatuses 101 to 104, four data storage devices (hereinafter referred to as RAID) 301 to 304, and one fiber channel switch 602 are configured.

  The FM personal computer 80 is connected to the NetIF personal computer 90 and the four data recording / reproducing apparatuses 101 to 104 through a LAN (Local Area Network) such as Ethernet (registered trademark) 19, for example. The FM personal computer 80 manages additional information (files) of AV data handled by the AV server 100. For example, the FM personal computer 80 holds information arranged in a file header part, a file footer part, etc. added to AV data via the data recording / reproducing apparatus 101 or the like.

  The NetIF personal computer 90 is connected to the network 500, for example, inputs stream data in a general format from a data supply system, and separates and manages additional information from the stream data. The stream data in the general format is composed of AV data composed of audio data and video data and its additional information. The additional information includes a file header part, a file footer part, and the like. For example, when performing data transmission / reception via the network, the NetIF personal computer 90 executes addition / deletion of a file header portion, a file footer portion, and the like based on information of the FM personal computer 80. This additional deletion is to enable the AV server 100 to record and manage the stream data in the general-purpose format from the network 500 smoothly and appropriately.

  Each of the data recording / reproducing apparatuses 101 to 104 is connected to a fiber channel switch 602 through an optical communication line (fiber channel), and the data writing / reading operation is speeded up. Four RAIDs 301 to 304 are connected to the fiber channel switch 602. For RAID 301 to 304, a recording medium such as a magnetic disk or a magneto-optical disk is used.

  The data recording / reproducing apparatus 101 receives recording control of the control terminal apparatus 200 at the time of data recording, inputs video and sound material information (SDI data; AV input), and performs SDI data in accordance with a predetermined compression standard (such as MPEG). Is encoded and compressed (encoded). The SDI data is NTSC or PAL video and sound material information created or edited by a data supply system 600 such as a broadcasting station or video and audio information distribution station. Additional information is added to the AV data after the SDI data is compressed to form AV stream data in a predetermined data format. AV stream data is recorded in RAID 301, 302, 303 or 304 via the fiber channel switch 602.

  Further, the data recording / reproducing apparatus 101 reads AV stream data of a predetermined data format based on the additional information from the RAID 301, 302, 303, or 304 under the reproduction control of the control terminal apparatus 200 during data reproduction. For example, AV stream data of a predetermined data format read from the RAID 301 is decoded and decompressed (decoded). The SDI data (AV output) after the AV data is decoded is output to, for example, a video display device or an audio output device.

  FIG. 3 is a block diagram showing an example of the internal configuration of the data recording / reproducing apparatus 101. 3 includes one fiber channel input / output substrate (hereinafter referred to as FC input / output substrate 11), three encoder substrates (hereinafter referred to as ENC substrates) 31 to 33, and three decoder substrates (hereinafter referred to as “FC substrate”). (Referred to as a DEC substrate) 41 to 43 and one recording / reproduction control substrate 12.

  The recording / reproducing control board 12 includes a CPU interface (hereinafter referred to as a CPU I / F circuit 21) and a CPU block 22. The CPU block 22 has a main CPU (first control system) 23 that constitutes a first control unit. The CPU 23 controls a circuit and a memory mounted on the FC input / output board 11. For example, when the CPU 23 acquires the write area on the RAID 301 from the FM personal computer 80 and the AV stream data is filled in the address area reserved in advance on the bank memory 14 mounted on the FC input / output board 11, The AV stream data is recorded on the RAID 301. An AV serial backplane 53 is connected to an I / O port (not shown) of the recording / reproduction control board 12. The FC input / output board 11 is connected to the AV serial backplane 53.

  The FC input / output board 11 constitutes a recording / reproducing unit, and includes a fiber channel interface circuit (hereinafter referred to as FC block 13), a bank memory 14, an encoder / decoder interface circuit (hereinafter referred to as backplane block 15), and a second control unit. The FC sub CPU 16 is configured. The FC block 13 is composed of a field programmable gate array (FPGA) and has an optical signal processing function. For example, a fiber channel is connected to the FC block 13. Further, the FC block 13 is provided with an optical signal processing unit (not shown), and performs optical signal processing such as optical modulation based on the stream data. A bank memory 14 is connected to the FC block 13, and AV stream data is stored in units of one frame. For example, AV stream data is written in the input address area of the bank memory 14. The address area information is added (superimposed) to the AV stream data.

  The AV stream data is transferred to the address area indicated by this information. Thus, the AV memory data can be buffered in the bank memory 14. A hard disk or the like is used for the bank memory 14. A backplane block 15 is connected to the bank memory 14. An AV serial backplane 53 is connected to the backplane block 15, and AV stream data transmission / reception processing with I / O ports such as the ENC boards 31 to 33 and the DEC boards 41 to 45 is executed.

  On the FC input / output board 11, an auxiliary CPU (Nios; hereinafter referred to as FC sub-CPU 16), which is locally composed of an FPGA, is constructed, and a plurality of ENC boards 31 to 33 are recorded at the time of data recording. Arbitrates the transfer destination of the AV stream data transmitted from. The FC sub CPU 16 controls reading / writing of stream data to / from the bank memory 14 based on a control command from the main CPU 23, and executes access control to the RAID 301 and the like through a fiber channel. For example, in the RAID 301, the FC sub CPU 16 receives information related to an area where AV stream data is written from the main CPU 23, and controls the FC block 13 based on this information to write the AV stream data on the bank memory 14 into the RAID 301. It is made like.

  ENC boards 31 to 33 and DEC boards 41 to 45 are connected to the AV serial backplane 53. One ENC board 31 includes an SDIIN block 34, an MPEG encoder 35, an audio block 36, an ENC sub CPU (second control system) 38, a mini bank memory 39, and a pack block 70.

  The ENC board 31 inputs an NTSC or PAL audio / video signal SDI during data recording, and encodes and compresses (encodes) the SDI input based on a signal compression standard such as MPEG. The audio / video data after compression is added with additional information to become AV stream data. Each time one frame of AV stream data is stored in the bank memory 14, the ENC board 31 transmits AV stream data to the FC input / output board 11 as needed under the control of the main CPU 23. At this time, a control signal from the control terminal device 200 is input. Communication cables based on the RS-422A communication protocol are used for the control terminal device 200 and the ENC board 31 and the like.

  In this example, the position on the bank memory 14 to which the AV stream data is transferred is added (superimposed) to the AV stream data. AV stream data is written to the input address area of the bank memory 14. Similarly, the other ENC boards 32 to 33 receive the audio / video signal SDI and output the AV stream data. The other ENC substrates 32 to 33 have the same configuration and function, but the description thereof is omitted.

  One DEC board 41 includes a depacking block 44, an MPEG decoder 45, an audio block 46, a jog memory 47, an SDIout block 48, and a DEC sub CPU 49.

  The DEC board 41 inputs AV stream data from the bank memory 14 to the depacking block 44 during data reproduction. In the depack block 44, the additional information is separated from the AV stream data. The MPEG stream data from which the additional information is separated is output to the MPEG decoder 45 and the audio block 46, respectively. In the MPEG decoder 45, the MPEG stream data is decoded and decompressed (decoded) based on a predetermined MPEG standard, and video data is output. The audio block 46 decodes the MPEG stream data and outputs audio data. The jog memory 47 stores the audio / video data after the depacking / decoding process. The audio / video data after the decoding process becomes SDI data. The SDI data is output from the jog memory 47 through the SDIout block 48 to, for example, a video display device or an audio output device.

  A control signal from the control terminal device 200 is input to the DEC board 41. A communication cable based on the RS-422A communication protocol is used between the control terminal device 200 and the DEC board 41 and the like. The other DEC boards 42 and 43 are similarly processed to input AV stream data and output an audio / video signal SDI. The other DEC substrates 42 and 43 have the same configuration and function, but the description thereof is omitted.

  A CPU bus 29 is provided in the AV serial backplane 53 described above. The CPU bus 29 is connected to the FC sub CPU 16, the main CPU 23, this embodiment of each of the boards 31 to 33, the DEC sub CPU 49 of each of the boards 41 to 43, and the REF input board 50. The REF input board 50 includes a TG block 51 and an LTS sub CPU 52. A REF signal (frame synchronization signal) is input to the TG block 51, and the REF signal is supplied to each of the boards 11, 12, 31 to 33, 41 to 43, etc. under the control of the LTS sub CPU 52. . The LTS sub CPU 52 is connected to the FM personal computer 80, the NetIF personal computer 90, and the CPU bus 29 through the Ethernet (registered trademark) 19, and communicates with the personal computers 80, 90, the main CPU 23, and the like. The other data recording / reproducing devices 102 to 104 have the same configuration, but the description thereof is omitted.

  FIG. 4 is a format showing an example data structure of an MXF file. The data structure of the MXF file shown in FIG. 4 is suitable for the AV multiplex data format and is an example applied in the AV server system 1 according to the present invention. According to the data structure example of the MXF file, the AV stream data includes a file header part, a file body part, and a file footer part, and has a hierarchical structure.

  In the file body portion, video data and audio data, which are AV data, are multiplexed and arranged in units of 60 frames (in the case of NTSC), for example. Furthermore, the MXF file does not depend on the platform, supports various recording formats, and corresponds to QT (Quick Time) (registered trademark), which is scalable software.

  In the file header part, information necessary for reproducing and editing video data and audio data arranged in a body part conforming to the MXF standard by QT is arranged. In the file header portion, an MXF header (MXF Header) including a run-in, a header partition pack, and header metadata is sequentially arranged from the head.

  Run-in is an option for interpreting the start of the MXF header if the 11-byte pattern matches. The run-in can be secured up to 64 kilobytes, but is 8 bytes, for example. Anything other than the 11 byte pattern of the MXF header may be placed in the run-in.

  In the header partition pack, an 11-byte pattern for specifying the file header part, the data format arranged in the file body part, information representing the file format, and the like are arranged. In the header metadata, information necessary for reading AV data arranged in the file body portion is arranged.

  The file body part is composed of a generic container (GC) or an essence container, and the GC container includes a partition pack (PP), an index table (Index Table), an edit unit (Edit Unite), and the like. Be placed. In the editing unit, the first to tenth frames are arranged in units of frames. A footer portion pack and a random index pack are arranged in the file footer portion.

  In one frame of the edit unit, AV data is multiplexed and arranged in units of 60 frames (in the case of NTSC), for example. In this hierarchy, a system item, a picture item, a sound item, and other items (Auxiliary) are arranged. In the system item, a local time code (LTC), a UMID, and an essence mark (Essence Mark) are described.

  For example, four blocks are arranged as the sound item. In the picture item, K, L, and IorPorB picture (MPEG ES) are arranged in the lower layer. A key (K), a data length (L), and a filler (Filler) are arranged at the subsequent stage. In the sound item, K, L, 1ch AES3 elements are arranged in the lower hierarchy. K, L, and a filler are arrange | positioned in the subsequent stage.

  The file footer part is composed of a footer partition pack, and data for specifying the file footer part is arranged in the footer partition pack. When the MXF file configured as described above is given, the data recording / reproducing apparatus 100 compliant with the MXF standard first obtains the MXF header by reading the 11-byte pattern of the header partition pack. Then, the AV data arranged in the GC container can be read based on the header metadata of the MXF header.

FIG. 5 is a block diagram showing a configuration example of the ENC board 31 and its peripheral board in the data recording / reproducing apparatus 101.
In this embodiment, assuming that AV data included in the SDI input (SDI IN), which is an asynchronous input signal, is recorded on the RAID 301, the main CPU 23 operates with a reference synchronization signal (reference synchronization signal). Communication with the substrate 31 is performed in synchronization with a reference synchronization signal (hereinafter referred to as a Ref synchronization signal). The devices in the ENC board 31 are controlled by a non-reference synchronization signal (hereinafter referred to as “Input synchronization signal”) synchronized with the SDI input, but operate in synchronization with the Input synchronization signal except for communication with the main CPU 23.

  The AV data converted from the SDI data into the AV stream data by the ENC board 31 is output to the bank memory 14 based on the Input synchronization signal. In this example, since data communication between the main CPU 23 and the ENC board 31 is performed in synchronization with the Ref synchronization signal, transfer of the control information Dc such as the REC status and the write area of the bank memory 14 is executed. As an example, AV stream data transferred to the bank memory 14 is transferred by embedding a write destination address, data size information, and the like in a header portion, asynchronously transferring data to the bank memory 14 and writing the data.

  A data recording / reproducing apparatus 101 shown in FIG. 5 includes an FC input / output board 11, a recording / reproduction control board 12, and an ENC board 31, and is connected to a RAID 301 connected through the FC channel switch 602 shown in FIG. Thus, stream data of a predetermined data format is stored or reproduced.

  The recording / reproducing control board 12 includes a CPU interface unit (hereinafter referred to as a CPU I / F unit 21) composed of an FPGA and a CPU block 22. The CPU block 22 is provided with a main CPU 23 constituting a first control system, and the main CPU 23 controls recording and reproduction of information such as AV stream data based on the Ref synchronization signal. For example, during the data recording control described above, the main CPU 23 notifies the ENC software of control information Dc for starting and stopping recording of AV stream data, information on the writing area of the bank memory 14, and the like. These pieces of information are executed via a dual port RAM provided in the FC input / output board 11 and the ENC board 31.

  In this example, the main CPU 23 compares the data amount stored in the bank memory 14 provided in the FC input / output board 11 with a preset control reference amount, and the data amount has reached the control reference amount. In this case, the AV stream data is recorded (stored) from the bank memory 14 to the RAID 301 based on the Ref synchronization signal.

  For example, the main CPU 23 determines that AV data is accumulated in the bank memory 14 based on the write information from the ENC sub CPU 38 to the FC sub CPU 16 constituting the second control unit, and the AV of the bank memory 14 is determined. Data is recorded in the RAID 301.

  The ENC board 31 includes an SDI block 34, a pack processor 37 constituted by an FPGA, an ENC sub CPU 38, a video / audio processor 60, an AV data P / S processing unit 68, and a dual port RAM 69.

  The SDI block 34 is a block for inputting SDI data (Data) from a broadcasting device or a video and music distribution device based on the input synchronization signal (SDIin). The SDI data is an example of information of an asynchronous input signal source, and is an audio / video signal with 30 images per second in the NTSC format and 25 images per second in the PAL format. A video / audio processor 60 is connected to the SDI block 34. The video / audio processor 60 is provided with an MPEG encoder 35 and an audio block 36 as shown in FIG. A pack processor 37 is connected to the video / audio processor 60, and the header information and AV stream data are combined and packed based on the input synchronization signal.

  An AV data P / S processing unit 68 is connected to the pack processor 37, and at the time of data recording, parallel AV data is input from the pack processor 37 based on the Input synchronization signal and converted into serial AV data. The AV data after being converted into serial is transferred to the FC input / output board 11. The AV data P / S processing unit 68 designates the area to be written in the bank memory 14 and the size of the transfer data (Input synchronization).

  The ENC sub CPU 38 also constitutes a second control system, and controls the ENC board 31 so as to record / reproduce SDI data asynchronous to the Ref synchronization signal. For example, the ENC sub CPU 38 controls the ENC board 31 so as to convert SDI data into AV stream data of a predetermined data format, and the converted AV stream data is synchronized with the input synchronization signal in accordance with an instruction from the main CPU 23. The data is transferred to the bank memory 14 and the main CPU 23 is notified of the amount of AV stream data transferred to the bank memory 14.

  For example, the ENC sub CPU 38 controls the AV data P / S processing unit 68 and the like so that the write destination address and the data size information are embedded in the header portion of the AV stream data and transferred to the bank memory 14. With this configuration, AV stream data can be transferred to the bank memory 14 asynchronously.

  The ENC sub CPU 38 is connected to a dual port RAM 69 that constitutes an example of a memory for communication. The communication information Cd from the main CPU 23 to the ENC sub CPU 38 is written based on the Ref synchronization signal, and read in synchronization with the Input synchronization signal. In addition, the communication information Cd from the ENC sub CPU 38 to the main CPU 23 is written in synchronization with the Input synchronization signal, and is read based on the Ref synchronization signal. The dual port RAM 69 is connected to the CPU bus 29 and is connected to the CPU I / F unit 21 of the recording / reproducing control board 12. The communication information Cd includes control information Dc for the main CPU 23 to control the ENC sub CPU 38 and reply notification information indicating the result of the control.

  In this example, communication between the main CPU 23 and the ENC sub CPU 38 is performed via the CPU I / F unit 21, the CPU bus 29, and the dual port RAM 69. For example, one frame of the Ref synchronization signal is divided into four. It is performed in a time-sharing manner in each control period (time slot). If comprised in this way, the conventional communication system is employ | adopted and the influence on main CPU23 can be suppressed to the minimum. For example, the ENC sub CPU 38 reads the writing area of the bank memory 14 based on the control information Dc obtained via the dual port RAM 69 and performs recording start / stop control for each device (Ref synchronization).

  In this example, the FC input / output board 11 is connected to the ENC board 31 through the data bus 27 and the CPU bus 29. The ENC board 31 includes a bank memory 14, an FC sub CPU 16, a bank memory controller 17, an AV data S / P processing unit 58, and a dual port RAM 59.

  The AV data S / P processing unit 58 is connected to the above-described AV data P / S processing unit 68 through the data bus 29. The AV data S / P processing unit 58 receives serial AV data from the ENC board 31 based on an input synchronization signal (hereinafter referred to as an input synchronization signal) and converts it into parallel AV data during data recording. The AV data converted into parallel is transferred to the bank memory controller 17 (Input synchronization).

  A bank memory controller 17 is connected to the AV data S / P processing unit 58, and under the control of the FC sub CPU 16, data write / read control of the bank memory 14 is executed based on the input synchronization signal. For example, the bank memory controller 17 refers to (extracts) the address and data size from the header information of the AV stream data based on the Input synchronization signal, and controls to write the AV data to the bank memory 14 (Input synchronization). The bank memory 14 temporarily stores AV stream data.

  The FC sub CPU 16 notifies the main CPU 23 of frame information such as the data size and time code Tc written in the bank memory 14 based on the Ref synchronization signal (Ref synchronization). The FC sub CPU 16 is connected to a dual port RAM 59 as an example of a memory for communication, and writes control information Dc (Data 1, Data 2, etc.) from the main CPU 23 to the FC sub CPU 16 based on the Ref synchronization signal and the Input synchronization signal. The information is read synchronously, and the communication information Cd from the FC sub CPU 16 to the main CPU 23 is written synchronously with the input synchronous signal and read based on the Ref synchronous signal. In this way, the main CPU 23 can manage the bank memory 14 via the FC sub CPU 16.

  In the method of the present invention, since the synchronization signal system is replaced with Ref synchronization signal → Input synchronization signal or Input synchronization signal → Ref synchronization signal, in order to prevent data depletion and overflow at the time of information notification, the communication amount is set to Ref. Quantification is not performed on the basis of the synchronization signal, in other words, the traffic is not quantified on the basis of the Ref synchronization signal. That is, a method is adopted in which information communication in frame units is reduced as much as possible, and communication information Cd is aggregated and the amount of the chunk is communicated together.

  For example, regarding the communication information Cd exchanged between the main CPU 23 and the FC sub CPU 16, the ENC sub CPU 38, etc., data is grouped according to the use and frequency of occurrence, and the number of data chunks grouped here is determined. It is made to be included in the notification item. In addition, in order to handle the data as a lump, a dual port RAM 69 having a FIFO memory is installed between the Ref sync signal and the Input sync signal, and when extracting data from this FIFO, the data amount in the FIFO is checked It has a loose interface structure that communicates together and does not send it together or send it. When the content of the communication information Cd is limited and dealt with in this way, data that can be notified collectively can be notified collectively, and communication failure can be prevented.

  Specifically, in the communication between the main CPU 23 and the ENC board 31, when the writing area in the bank memory 14 is notified, the bank memory 14 can be written for several frames without notifying the address every time one frame is written. Communicates the write area (start address, size). The ENC board 31 receives writable bank information based on the Ref synchronization signal of a certain frame, and the ENC board 31 increments the address based on the information. Communication failure can be prevented by collectively reporting such information.

  In this example, as a communication item between the ENC board 31 and the main CPU 23, the size of data to be written to the bank memory 14 which has become indefinite in the MPEG long GOP is notified, and the recorded time code Tc is notified. . By handling these data as one information block in one frame and notifying information for 0 to 2 frames at the timing of the Input sync signal and the Ref sync signal, it is possible to prevent data transfer failure.

  Table 1 shows communication contents in units of frames by the dual port RAM 69 for asynchronous recording. In this example, communication processing is performed between the main CPU 23 and the ENC sub CPU 38 of the ENC board 31 via the dual port RAM 69.

  The communication contents are a picture item size, a recording time code, and the like. In this example, the item name data valid (Data Valid) is a flag indicating the validity of the data. The flag byte is 1 byte (Byte), 4 bits (Bit), or 1 Bit. The flag “1” indicates valid (Valid), and the flag “0” indicates invalid (Invalid).

  The data size (Data Size) indicates an effective data size, and is 0 to 2 frames in this example. The size byte is 1 byte or 4 bits. Data 1 (Data 1) is the data content of the first frame of communication in units of frames (DPS communication) by the dual port RAM 69, and its byte is arbitrary. This is because the number of bytes varies depending on each communication content. Data 2 is the data content of the second frame of the DPS communication, and the byte is arbitrary. This is also because the number of bytes varies depending on each communication content.

  Further, according to communication between the other main CPU 23 and the ENC board 31 via the dual port RAM 69, the status is notified from the main CPU 23 to the ENC board 31. In this case, the status is notified for each frame. However, when the communication information Cd is lost on the ENC board 31 side, the previous state is maintained, and when it is transferred to one side for two frames, a new status is displayed. By adopting it, it will be made to cope with information depletion.

6A to 6K are operation time charts in the data recording / reproducing apparatus 101, and show communication time charts between the main CPU 23 and the ENC board 31.
In this embodiment, when communication is performed between the main CPU 23 and the FC sub CPU 16 via the dual-port RAM 59, one frame of the Ref sync signal is divided into four times in each control period. With this configuration, the influence on the main CPU 23 can be minimized as compared with the case where a conventional communication method is adopted. Incidentally, when the conventional HV time division communication system is adopted, data synchronized with input signals such as the data size, time code Tc, and metadata written in the bank memory 14 and control information such as memory area information of the bank memory 14 In the delivery of Dc, the communication between the main CPU 23 and the FC sub CPU 16 breaks down.

  In the system of the present invention, these can be prevented. As a preventive measure, the delay amount when converting the SDI data in the ENC board 31 into AV stream data is simply set to one frame. Further, a case where the block area notification from the main CPU 23 to the bank memory 14 is executed in the control period HV1 of the HV_CNT signal of the Ref synchronization signal is taken as an example.

In this example, the counter for time axis HV that is cleared by hardware is HV. Create a CNT signal, this HV The CNT signal can be read from the main CPU 23. In addition, after switching of time axis HV, HV The interrupt request is activated by the INT signal. Main CPU 23 is an interrupt handler and counter HV of time axis HV The value of CNT is read and the current time axis HV value is recognized.

The Ref synchronization signal shown in FIG. 6A is a reference frame of a signal for operating the main CPU 23 of the data recording / reproducing apparatus 101. HV shown in FIG. 6B The INT signal is an interrupt pulse signal, and is a signal that divides one cycle of the Ref synchronization signal into four at equal intervals. This HV Based on the INT signal, four interrupts can be generated to the main CPU 23.

The HV_CNT signal shown in FIG. 6C is a control period (control information: time slot) obtained by the counters 0 to 3 on the time axis HV synchronized with the Ref synchronization signal of the main CPU 23. HV is a time axis obtained by time-dividing one frame into four, and each is indicated by control periods HV0, HV1, HV2, and HV3. The control periods HV0 and HV1 are periods in which even fields are controlled by the video scanning method. HV2 and HV3 are periods for controlling odd fields. In this example, HV In the control period HV1 of the CNT signal, the main CPU 23 writes a writable bank area (address size) for several frames in the dual port RAM 69 (Ref synchronization). Further, the ENC software reads the bank information from the dual port RAM 69 during the control period HV2 (Ref synchronization).

  The input synchronization signal shown in FIG. 6D is an input frame synchronized with the SDI data of the ENC board 31 and is an input frame of a signal for operating the ENC sub CPU 38. IN_HV_CNT shown in FIG. 6E is a control period (information) obtained by the counters 0 to 3 on the time axis HV in synchronization with the input synchronization signal of the SDI data of the ENC board 31. The SDI data shown in FIG. 6F is data input to the SDI block. The SDI data indicates the Nth data, the N−1th data before it, the N + 1th data, the N + 2th data, etc. after that, based on the input synchronization signal.

  AV data shown in FIG. 6G is data separated from SDI data. In this example, the delay amount when converting the SDI data in the ENC board 31 into AV stream data is one frame. Therefore, the AV data is delayed by one frame from the SDI data with reference to the input synchronization signal. In the figure, the Nth AV data, the N−1th and N−2th AV data before it, and the subsequent N + 1 The AV data are shown.

  Control information Dc such as REC start, address, and data size is transferred from the main CPU 23 shown in FIG. 6H to the dual port RAM 69 shown in FIG. 6I at the timing I of the control period HV1. Similarly, control information Dc such as REC start, address, and data size is transferred at timing II of the control period HV2. Further, the above-described three control information Dc and the like are transferred from the dual port RAM 69 shown in FIG. 6I to the ENC software shown in FIG. 6J. In this example, the start flag and address of the (N-1) th AV data are set at the timing III of the control period HV2.

  The address acquired from the ENC software shown in FIG. 6J via the dual port RAM 69 is set in the AV data P / S processing unit 68 shown in FIG. 6K in the control period HV2 (Input synchronization). That is, the timing of setting the address of the bank memory 14 in the AV data P / S processing unit 68 that outputs AV stream data and setting the transfer start flag is the control period of the IN_HV_CNT signal of the input of the previous frame of the AV stream to be output It is set based on HV2.

  In this example, the ENC software increments the address until the writable area (block) acquired in the bank memory 14 is used up. The start flag and address of the Nth AV data are set at the timing IV of the control period HV2. At the timing V of the control period HV2, the start flag and address of the (N + 1) th AV data are set. This eliminates data depletion.

  Next, an information recording / reproducing method according to the present invention will be described. 7 to 12 are flowcharts showing an operation example in the data recording / reproducing apparatus 101. FIG. 7 is a flowchart showing a control example at the time of REC start in the main CPU 23.

  In this embodiment, the main CPU (first control system) 23 manages information recording / reproduction based on the Ref synchronization signal, and the second control system such as the FC sub CPU 16 and the ENC sub CPU 38 responds to the Ref synchronization signal. Asynchronous SDI data is recorded and reproduced, and control information Dc from the main CPU 23 to the FC sub CPU 16 and the ENC sub CPU 38 is written to the dual port RAM 59 or 69 based on the Ref synchronization signal. Read in sync with.

  On the contrary, the communication information Cd from the FC sub CPU 16 or the ENC sub CPU 38 to the main CPU 23 is written in the dual port RAM 59 or 69 in synchronization with the input synchronization signal and is read out from the RAM 59 or 69 based on the Ref synchronization signal. The

  In addition, regarding communication information Cd exchanged between the main CPU 23 and the FC sub CPU 16 or the ENC sub CPU 38, data is grouped according to the use and frequency of occurrence, and the number of data chunks grouped here is notified. To be included in the item. Further, the write destination address and the data size information are embedded in the header portion of the AV stream data and transferred to the bank memory 14.

  Under these operating conditions, the main CPU 23 receives the main REC start (signal) in step A1 of the flowchart shown in FIG. At this time, the main CPU 23 receives a REC start command from the host control terminal device 200 via the RS-422 based on the Ref synchronization signal. During the data recording control described above, the main CPU 23 notifies the ENC software of control information Dc for starting and stopping recording of AV stream data, information on the writing area of the bank memory 14, and the like.

  Next, in step A2, the main CPU 23 controls the FC sub CPU 16 so as to secure two frames of free space in the bank memory 14 of the FC input / output board 11. For example, the main CPU 23 writes an instruction for “reserving an empty area” in the dual port RAM 59 of the FC input / output board 11. The FC sub CPU 16 receives the notification from the main CPU 23 via the dual port RAM 59 in the control period HV0 based on the Ref synchronization signal, and stores about 8.5 MB × 2 blocks in the bank memory 14 based on this notification. Is secured (Ref synchronization). One block corresponds to about 1 second when the transfer rate is about 50 MbPS.

  In step A3, the main CPU 23 writes the REC start to the ENC sub CPU 38 and notifies the bank area that one block of free space has been secured (Ref synchronization; control period HV0). At this time, the main CPU 23 writes a REC start instruction in the dual port RAM 69 of the ENC board 31. At the same time, the main CPU 23 notifies the address and size of the writable bank area at the same timing as the REC start. The second block is notified after the next frame.

  Thereafter, in step A4, the ENC sub CPU 38 receives the REC start in the control period HV1 based on the Ref synchronization signal. At this time, the ENC sub CPU 38 reads the dual port RAM 69 and reads the REC start instruction.

  Next, in step A5, the ENC sub CPU 38 writes the REC start in the FIFO for Ref → input conversion in the ENC software in the control period HV1 based on the Ref synchronization signal. At this time, the ENC sub CPU 38 writes the address and size of the writable bank area in the FIFO at the same timing as the REC start. Thereafter, the process proceeds to the Ref → Input conversion process.

FIG. 8 is a flowchart showing a control example at the time of REC start in the ENC sub CPU 38.
In this embodiment, according to the control example at the time of REC start in the ENC sub CPU 38, in the flowchart shown in FIG. 8, first, in step B1, the ENC sub CPU 38 in the ENC software in the control period HV2 based on the input synchronization signal. Reads the amount of FIFO data for Ref → Input conversion.

  Thereafter, in step B2, the ENC sub CPU 38 detects whether or not the data amount is “0”. If the data amount is “0”, the process proceeds to step B3 to maintain the ENC software status in the previous state (Input synchronization; HV2). At this time, if the RAID 301 is being recorded (REC), it remains in REC. If it is stopped (IDLE), it remains in REC. If the previous status is REC start, the status is changed to REC. If the previous one is a REC stop, the status is changed to IDLE.

  If the data amount is not “0”, the process proceeds to step B4, and the control branches based on whether the data amount is “1”. When the data amount is “1”, the process proceeds to step B5, and the ENC sub CPU 38 reads one FIFO data for command in the ENC software in the control period HV2 based on the Input signal, The status of the ENC software is set (Input synchronization; HV2). At this time, since the address and size of the bank area in which writing is possible are written in the FIFO at the same timing as the REC start, the ENC sub CPU 38 acquires the address and size of the bank area. In this example, since the REC start is read from the FIFO in the ENC software, the status is REC start.

  If the data amount is “2” in step B6, the process proceeds to step B7, and the ENC sub CPU 38 reads two FIFO data for ENC software commands in the control period HV2 based on the input synchronization signal. Then, the control change point command is selected (Input synchronization; HV2). At this time, if the RAID 301 is in status = REC start or REC, REC start is selected.

  If the RAID 301 is status = REC in progress or REC stop, REC stop is selected. If the RAID 301 is status = REC start or REC stop, one frame REC is selected. In this example, when the REC start is designated immediately after the REC stop, it is excluded from the control target.

  If the data amount is not “2” in step B6 described above, the process proceeds to step B8 to execute an abnormality process. The abnormality process is for coping with input synchronization disturbance and Ref synchronization disturbance. If an abnormality is detected, the main CPU 23 notifies an error. If the status is REC, the main CPU 23 changes the status to the IDLE state. Thereafter, the process proceeds to REC start (Input synchronization).

FIG. 9 is a flowchart showing an example of encoding control by the ENC sub CPU 38 in the ENC board 31.
In this embodiment, the ENC sub CPU 38 controls the ENC board 31 so as to record / reproduce SDI data asynchronous to the Ref synchronization signal. For example, the ENC sub CPU 38 controls the ENC board 31 so as to convert SDI data into AV stream data of a predetermined data format, and the converted AV stream data is synchronized with the input synchronization signal in accordance with an instruction from the main CPU 23. The data is transferred to the bank memory 14 and the main CPU 23 is notified of the amount of AV stream data transferred to the bank memory 14.

  With this as an encoding processing condition, in the flowchart of FIG. 9, first, in step C1, the ENC sub CPU 38 detects the status of the ENC software and obtains a REC start. Next, in step C2, the ENC sub CPU 38 outputs a start instruction to the MPEG encoder 35 or the like in the ENC board 31 in the control period HV1 based on the input synchronization signal (Input synchronization; HV1). The ENC board 31 that has received this start instruction inputs SDI data based on the input synchronization signal from the broadcast device or video / music distribution device. The SDI data is an example of information of an asynchronous input signal source, and is an audio / video signal with 30 images per second in the NTSC format and 25 images per second in the PAL format.

  In the video / audio processor 60, the SDI data is compression-encoded by the MPEG compression standard, for example. The AV data after the compression encoding process is packed by the pack processor 37. In this packing process, header information and AV stream data are combined based on the input synchronization signal.

  Thereafter, in step C3, the ENC sub CPU 38 notifies the main CPU 23 of the result of compressing the baseband video signal from the MPEG encode 35 through an interrupt. For example, the notification content includes the data size of the AV data after MPEG compression, the picture type (I picture, B picture, P picture), and the like. In the dual port RAM 69, the data size from the ENC sub CPU 38 to the main CPU 23 and communication information Cd such as picture type are written in synchronization with the input synchronization signal and read out based on the Ref synchronization signal.

  In step C4, the ENC sub CPU 38 executes other processing, for example, pack processing such as recording format conversion, based on the input synchronization signal. At this time, the ENC sub CPU 38 controls the pack block 70 so as to embed the write destination address and data size information in the header portion of the AV stream data and transfer it to the bank memory 14.

  Thereafter, in step C5, the ENC sub CPU 38 writes a bank memory area for transferring data to the AV stream transmission (P / S conversion block) in the ENC board 31 (Input synchronization; HV3). At this time, the ENC sub CPU 38 sets the address and data size received from the main CPU 23 in the AV data P / S processing unit 68. Upon receiving this setting, the AV data P / S processing unit 68 designates the area to be written in the bank memory 14 and the size of the transfer data (Input synchronization). Further, the AV data P / S processing unit 68 inputs parallel AV data from the pack processor 37 based on the Input synchronization signal, and converts it into serial AV data. The AV data after being converted into serial is transferred to the FC input / output board 11. With this configuration, AV stream data can be transferred to the bank memory 14 asynchronously.

  In step C6, the ENC sub CPU 38 writes frame information such as the data size and picture type transferred to the bank memory 14 in the FIFO for Input → Ref conversion in the control period HV1 based on the Input synchronization signal (Input synchronization; HV1 ). In the dual port RAM 69, communication information Cd such as frame information from the ENC sub CPU 38 to the main CPU 23 is written in synchronism with the input sync signal and read out based on the Ref sync signal. Thereafter, the control proceeds to the control example at the time of REC start in the ENC sub CPU 38.

FIG. 10 is a flowchart showing a control example at the time of REC start in the ENC sub CPU 38.
In the flowchart of FIG. 10, in step E1, the ENC sub CPU 38 reads the FIFO data amount for Ref synchronous input conversion in the ENC software (Input synchronization; HV2). Next, in step E2, the ENC sub CPU 38 detects whether or not the data amount is “0”, and branches control based on the detection. When the data amount is “0”, the process proceeds to step E3, and the ENC sub CPU 38 notifies the main CPU 23 that there is no data because there is no frame information such as the data size and picture type. At this time, the ENC sub CPU 38 notifies the main CPU 23 via the dual port RAM 69 (Ref synchronization; HV1).

  When the data amount is not “0”, the process proceeds to step E4, and the ENC sub CPU 38 branches the control based on whether the data amount is “1”. If the data amount is “1”, the process proceeds to step E5, and the ENC sub CPU 38 notifies the main CPU 23 that there is data because frame information such as the data size and picture type exists. At this time, the ENC sub CPU 38 notifies the main CPU 23 of the frame information and the number of valid data via the dual port RAM 69 (Ref synchronization; HV1).

  If the data amount is not “1” in step E4, the process proceeds to step E6 to detect whether the data amount is “2”. When the data amount is “2”, the process proceeds to step E7, and the ENC sub CPU 38 notifies the main CPU 23 of the frame information and the number of valid data Y because there are two data sizes and picture types. . At this time, the main CPU 23 is notified via the dual port RAM 69 (Ref synchronization; HV1).

  If the data amount is not “2”, the process proceeds to step E8 to execute an abnormality process. The abnormality process is for coping with input synchronization disturbance and Ref synchronization disturbance. The ENC sub CPU 38 notifies the main CPU 23 of the error. If the status is REC, the main CPU 23 sets the status to the IDLE state. Thereafter, the process shifts to the Ref synchronization process of the main CPU 23.

  FIG. 11 is a flowchart illustrating a communication example of the control information Dc in the main CPU 23. In step F1 of the flowchart shown in FIG. 11, the main CPU 23 receives frame information such as the data size and the valid data amount (0 to 2 frames) via the dual port RAM 69 (Ref synchronization).

  In step F2, the main CPU 23 recognizes that the AV data has been written to the bank memory 14 of the FC input / output board 11 that has previously given the write instruction. At this time, the main CPU 23 determines that AV data has been stored in the bank memory 14 based on the write information from the ENC sub CPU 38 to the FC sub CPU 16, and records the AV data in the bank memory 14 in the RAID 301. To be made. Thereby, the REC start process in the main CPU 23 is ended.

  FIG. 12 is a flowchart showing an example of recording in the bank memory 14. In this embodiment, the processing in the ENC software is almost the same as that at the start of REC, and data is transferred to the bank memory 14 while incrementing the address every frame. The transferred data size is notified to the main CPU 23 as frame information. When this process is repeated, the memory block (8.5 Mbytes) secured in the bank memory 14 of the FC input / output board 11 by the main CPU 23 becomes full.

  Under these data recording conditions, first, at step G1 of the flowchart shown in FIG. 12, the main CPU 23 sends frame information such as data size and picture from the ENC sub CPU 38 via the dual port RAM 69 and an effective data amount (2 frames). Minutes) (Ref synchronization).

  Next, in step G2, the main CPU 23 recognizes that data has been written to the bank memory 14 of the FC input / output board 11 that has previously given the write instruction. In step G3, the main CPU 23 detects that the block of the bank memory 14 notified to the ENC sub CPU 38 is full. At this time, in the dual port RAM 59, the communication information Cd indicating “block full” from the FC sub CPU 16 to the main CPU 23 is written in synchronization with the Input synchronization signal and read out based on the Ref synchronization signal.

  Thereafter, in step G4, the main CPU 23 notifies the FC sub CPU 16 of the FC input / output board 11 to record the data of the block of the bank memory 14 which has become full in the RAID 301. The main CPU 23 transmits the frame information such as the data size and the picture and the effective data amount (for two frames) to the FC sub CPU 16 via the dual port RAM 59 (Ref synchronization).

  In parallel with this, in step G5, the main CPU 23 notifies the FC input / output CPU 16, the ENC sub CPU 38, etc. so as to secure an empty block in the bank memory 14. In the dual port RAM 59, 69, etc., the control information Dc for “reserving an empty block” from the main CPU 23 to the FC sub CPU 16 is written based on the Ref synchronization signal and read in synchronization with the Input synchronization signal.

  In step G6, the main CPU 23 detects the block of the bank memory 14 in which the AV data is full, and writes the AV data from the block of the bank memory 14 to the RAID 301 (Ref synchronization). For example, in the FC input / output board 11, the AV data S / P processing unit 58 receives serial AV data from the ENC board 31 and converts it into parallel AV data during the control period based on the input synchronization signal. The AV data converted into parallel is transferred to the bank memory controller 17 (Input synchronization).

  Under the control of the FC sub CPU 16, the bank memory controller 17 executes data write / read control of the bank memory 14 based on the Input synchronization signal. For example, the bank memory controller 17 refers to (extracts) the address and data size from the header information of the AV stream data based on the Input synchronization signal, and controls to write the AV data to the bank memory 14 (Input synchronization). The bank memory 14 temporarily stores AV stream data.

  The FC sub CPU 16 notifies the main CPU 23 of frame information such as the data size and time code Tc written in the bank memory 14 based on the Ref synchronization signal (Ref synchronization). AV data is written from the block of the bank memory 14 to the RAID 301 based on the Ref synchronization signal (Ref synchronization). Under such control, the main CPU 23 can manage the bank memory 14 via the FC sub CPU 16 and the ENC sub CPU 38.

  As described above, according to the information recording / reproducing system and the information recording / reproducing method as the embodiment, the digital recording / reproducing apparatus 101 connected to the RAID 301 has dual when recording AV stream data of a predetermined data format on the RAID 301. The port RAMs 59 and 69 use the control information Dc from the main CPU 23 that manages the recording and reproduction of information based on the Ref synchronization signal to the FC sub CPU 16 and the ENC sub CPU 38 that control recording and reproduction of asynchronous SDI data as the Ref synchronization signal. Based on this, writing is performed in synchronization with the input synchronization signal. The dual port RAMs 59 and 69 write communication information Cd from the FC sub CPU 16 and the ENC sub CPU 38 to the main CPU 23 in synchronization with the input synchronization signal and read out based on the Ref synchronization signal.

  Therefore, the FC sub CPU 16 and the ENC sub CPU 38 that control recording / reproduction of asynchronous SDI data can be managed by the main CPU 23 based on the Ref synchronization signal. As a result, the data recording / reproducing apparatus 101 can record / reproduce the SDI data asynchronous with the Ref synchronization signal with the RAID 301. In addition, it is not necessary to prepare a frame synchronizer as in the conventional method. Also, it becomes possible to provide an AV server system 1 to which the information recording / reproducing system is applied.

  An AV server for recording stream data in a predetermined data format obtained by encoding and compressing audio and video data in a large-capacity storage device, or reproducing and decoding the data stream data from the storage device It is extremely suitable when applied to a system.

1 is a block diagram showing a configuration example of an AV server system 1 as an embodiment according to the present invention. 2 is a block diagram illustrating an example of an internal configuration of an AV server 100. FIG. 3 is a block diagram showing an example of the internal configuration of a data recording / reproducing apparatus 101. FIG. It is a format which shows the data structure example of a MXF file. 3 is a block diagram showing a configuration example of an ENC board 31 and its peripheral board in the data recording / reproducing apparatus 101. FIG. (A) to (K) are time charts showing an operation example in the data recording / reproducing apparatus 101. It is a flowchart which shows the example of control at the time of REC start in a main CPU. 7 is a flowchart showing a control example (No. 1) at the time of REC start in the ENC sub CPU. It is a flowchart which shows the example of encoding control by ENC sub CPU in an ENC board | substrate. It is a flowchart which shows the control example (the 2) at the time of REC start in an ENC sub CPU. It is a flowchart which shows the example of communication of the control information in main CPU. It is a flowchart which shows the example of recording from a bank memory to RAID.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... FC input / output board, 12 ... Recording / reproduction control board, 13 ... FC block, 14 ... Bank memory (data storage part), 16 ... FC sub CPU (2nd control part) ), 19... Ethernet (registered trademark), 23... Main CPU (first control unit), 31 to 33... ENC board, 38... ENC sub CPU (second control unit), 39 ... Mini bank memory, 47 ... Jog memory (data storage unit), 49 ... DEC sub CPU (second control unit), 59, 69 ... Dual port RAM (memory for communication) , 60: Video / audio processor, 70: Pack block, 80 ... FM personal computer, 90 ... NetIF personal computer, 100 ... AV server (video recording / reproducing apparatus), 200 ... Control terminal apparatus 101 to 104 ... the data recording and reproducing apparatus (information recording and reproducing apparatus), 301~304 ··· RAID (data recording device)

Claims (15)

A data storage device for storing stream data in a predetermined data format;
An information recording / reproducing device connected to the data storage device for recording and / or reproducing the stream data;
The information recording / reproducing apparatus comprises:
An information recording / reproducing unit;
A first control unit that manages recording and reproduction of information based on a reference synchronization signal;
A second control unit that controls the information recording / reproducing unit to record / reproduce information of an input signal source that is asynchronous with respect to the reference synchronization signal;
Communication information from the first control unit to the second control unit is written based on the reference synchronization signal and read out in synchronization with the input signal source, and the second control unit to the first control unit The information recording / reproducing system includes: a communication memory for writing communication information to the input signal source in synchronization with the input signal source and reading out based on the reference synchronization signal. The second controller is
Controlling the information recording / reproducing unit to convert the information of the input signal source into stream data of a predetermined data format;
The converted stream data is transferred to a bank memory in synchronization with the input signal source in accordance with an instruction from the first control unit,
The information recording / reproducing system according to claim 1, wherein the first control unit is notified of the amount of stream data transferred to the bank memory. The first controller is
Compare the amount of data stored in the bank memory and the control reference amount,
The information recording / reproducing system according to claim 2, wherein when the data amount reaches a control reference amount, stream data is recorded from the bank memory to the data storage device based on the reference synchronization signal. The communication memory is
It consists of dual port RAM,
Communication between the first control unit and the second control unit is performed in a time-sharing manner in each control period obtained by dividing one frame of the reference synchronization signal into four through the dual port RAM. The information recording / reproducing system according to claim 1. Regarding communication information exchanged between the first control unit and the second control unit, data is grouped according to usage and frequency of occurrence,
The information recording / reproducing system according to claim 1, wherein the number of the grouped data chunks is included in a notification item. The second controller is
3. The information recording / reproducing system according to claim 2, wherein the information recording / reproducing unit is controlled to embed a write destination address and data size information in a header of the stream data and transfer the embedded data to the bank memory. A first control unit that manages recording and reproduction of information based on a reference synchronization signal;
A second control unit for recording and reproducing information of an input signal source asynchronous with respect to the reference synchronization signal;
Communication information from the first control unit to the second control unit is written based on the reference synchronization signal and read out in synchronization with the input signal source, and the second control unit to the first control unit And a communication memory that reads out the communication information in synchronization with the input signal source and reads out the communication information based on the reference synchronization signal. The second controller is
Controlling the information recording / reproducing unit to convert the information of the input signal source into stream data of a predetermined data format;
The converted stream data is transferred to a bank memory in synchronization with the input signal source in accordance with an instruction from the first control unit,
8. The information recording / reproducing apparatus according to claim 7, wherein the first control unit is notified of the amount of stream data transferred to the bank memory. The first controller is
Compare the amount of data stored in the bank memory and the control reference amount,
9. The information recording / reproducing apparatus according to claim 8, wherein when the data amount reaches a control reference amount, stream data is recorded from the bank memory to the data storage device based on the reference synchronization signal. The communication memory is
It consists of dual port RAM,
The communication between the first control unit and the second control unit is performed in a time-sharing manner in each control period obtained by dividing one frame of the reference synchronization signal into four through the dual port RAM. The information recording / reproducing apparatus according to claim 7. Regarding communication information exchanged between the first control unit and the second control unit, data is grouped according to usage and frequency of occurrence,
8. The information recording / reproducing apparatus according to claim 7, wherein the number of the grouped data chunks is included in a notification item. The second controller is
9. The information recording / reproducing apparatus according to claim 8, wherein the information recording / reproducing unit is controlled so that a write destination address and data size information are embedded in a header of the stream data and transferred to the bank memory. Managing the recording and reproduction of information based on the reference synchronization signal in the first control system;
Recording and reproducing information of an input signal source asynchronous to the reference synchronization signal in the second control system;
The communication information from the first control system to the second control system is written to the memory based on the reference synchronization signal and read from the memory in synchronization with the input signal source,
Communication information from the second control system to the first control system is written in a memory in synchronization with the input signal source, and is read from the memory based on the reference synchronization signal. Regarding communication information exchanged between the first control system and the second control system, data is grouped according to usage and frequency of occurrence,
14. The information recording / reproducing method according to claim 13, wherein the number of data chunks grouped is included in a notification item. 14. The information recording / reproducing method according to claim 13, wherein a write destination address and data size information are embedded in a header of the stream data and transferred to the bank memory.

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