JP2006300832A - Film thickness measuring method, film thickness measuring program, and manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a film thickness measuring method measuring precisely and nondestructively a film thickness of a semiconductor integrated circuit pattern transferred and formed on a semiconductor substrate. <P>SOLUTION: This film thickness measuring method has steps of: acquiring a product secondary electronic signal waveform of a product pattern; extracting a plurality of product feature amounts from the product secondary electronic signal waveform; and measuring the film thickness of the product pattern, using a plurality of model functions calculated preliminarily, setting:, as unknowns, the plurality of product feature amounts in a test pattern having a dimension specification same that of the product pattern; and a plurality of exposure conditions therefor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a film thickness measurement method, a film thickness measurement program, and a semiconductor device manufacturing method, and more particularly to a resist pattern film thickness measurement technique.

As miniaturization of semiconductor devices progresses, a resist pattern dimension measurement technique in a lithography process has become important. Conventionally, a two-dimensional shape measuring apparatus such as a scanning electron microscope (SEM) has been used for dimension measurement of a resist pattern (see, for example, Non-Patent Document 1). However, although the two-dimensional shape measuring apparatus is effective for measuring the line width of a resist pattern, it is not suitable for measuring a film thickness. Therefore, there is a method (cross section SEM) in which a resist pattern is cut and a cross section is observed with an SEM in order to measure the film thickness with the SEM. However, cross-sectional SEM is a destructive inspection and cannot be used for product inspection. Devices that can measure the three-dimensional shape of a resist pattern include a light wave scattering measurement device, a focused ion beam processing observation device (FIB), a transmission electron microscope (TEM), an atomic force microscope (AFM), and the like. In the light wave scattering measuring apparatus, the resist pattern to be measured is a dense pattern such as a line and space pattern and has an area of about 50 μm ² , and there are many restrictions for use in product inspection. FIB and TEM can measure film thickness with high precision, but cannot be used for product inspection because of destructive inspection. On the other hand, AFM can measure film thickness with high accuracy by nondestructive inspection. However, since the AFM scans the resist surface with a probe, it is necessary to verify whether the resist pattern observed by the AFM can be used for subsequent processing, and there is still a problem in using it for product inspection.
Koji Hashimoto, “Model-based PPC Verification Methodology with Two-dimensional Pattern Feature Extraction” (USA), SPIE Optical Microlithography 16 XVI), 2003

  The present invention provides a film thickness measurement method, a film thickness measurement program, and a method for manufacturing a semiconductor device that enable high-precision film thickness measurement of a semiconductor integrated circuit pattern transferred and formed on a semiconductor substrate by nondestructive inspection.

  In order to achieve the above object, the first feature of the present invention includes (a) a step of obtaining a product secondary electronic signal waveform of a product pattern, and (b) a plurality of product feature quantities from the product secondary electronic signal waveform. (C) a product pattern film using a plurality of pre-calculated model functions in which each of a plurality of model feature quantities and a plurality of exposure conditions of a test pattern having the same product pattern and dimension standard is an unknown The gist of the present invention is a film thickness measuring method including a step of measuring a thickness.

  The second feature of the present invention is that the central processing unit of the film thickness measurement system has (b) a procedure for acquiring a product secondary electronic signal waveform of a product pattern, and (C) Using a plurality of pre-calculated model functions, each of which is an unknown number of a plurality of model feature quantities and a plurality of exposure conditions of a test pattern having the same dimensional standard as the product pattern, The gist of the present invention is a film thickness measurement program for executing a procedure for measuring a film thickness of a product pattern.

According to the present invention, there is provided a film thickness measuring method, a film thickness measuring program, and a semiconductor device manufacturing method capable of performing highly accurate film thickness measurement of a semiconductor integrated circuit pattern transferred and formed on a semiconductor substrate by nondestructive inspection. Can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The embodiments shown below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention specifies the arrangement of components and the like as follows. Not what you want. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
The film thickness measurement system shown in FIG. 1 according to the first embodiment of the present invention transfers a product mask pattern onto a product resist, and forms an exposure apparatus 3 that forms a product resist pattern, which is a product pattern. An electron microscope apparatus 332 that acquires a product secondary electron signal waveform and a central processing unit (CPU) 300 are included. The exposure apparatus 3 further forms a plurality of test resist patterns (test patterns) having the same dimensional standard as the product resist pattern on the test mask pattern under a plurality of exposure conditions. The CPU 300 includes a product feature amount extraction unit 345, an exposure function calculation unit 347, and a film thickness calculation unit 346. The product feature quantity extraction unit 345 extracts a plurality of product feature quantities from the product secondary electron signal waveform. The exposure function calculation unit 347 acquires a plurality of model features extracted from each model secondary electron signal waveform of each of the plurality of test resist patterns and a plurality of model functions with each of the plurality of exposure conditions as unknowns. To do. Further, the exposure function calculation unit 347 obtains a film thickness function in which the model film thickness of the plurality of test resist patterns and the plurality of exposure conditions are unknowns. The “product feature value”, “model feature value”, and “model film thickness” will be described later with reference to FIGS. Further, the exposure function calculation unit 347 shown in FIG. 1 substitutes a plurality of product feature amounts for each of the plurality of model functions, and derives simultaneous equations composed of a group of exposure functions. The film thickness calculator 346 solves the simultaneous equations and calculates the calculated exposure conditions. Further, the film thickness calculation unit 346 substitutes the calculated exposure condition into the film thickness function to calculate the film thickness of the product resist pattern.

  As shown in FIG. 2, the exposure apparatus 3 includes an illumination light source 41, an aperture stop holder 58 disposed below the illumination light source 41, a polarizer 59 that polarizes light emitted from the illumination light source 41, and a collection of illumination light. Light collecting optical system 43, slit holder 54 disposed below the condensing optical system 43, reticle stage 15 disposed below the slit holder 54, projection optical system 42 disposed below the reticle stage 15, A wafer stage 32 is provided below the projection optical system.

  On the reticle stage 15, a product mask provided with a product mask pattern such as a circuit pattern and a test mask provided with a test mask pattern such as a plurality of rectangular patterns are arranged. Reticle stage 15 is for reticle XY stage 81, reticle movable shafts 83a and 83b arranged on the top of reticle XY stage 81, and reticle movable shafts 83a and 83b, respectively. A Z-tilt stage 82 is provided. A reticle stage drive unit 97 is connected to the reticle stage 15. The reticle stage drive unit 97 scans the reticle XY stage 81 in the horizontal direction. Each of the reticle movable shafts 83a and 83b is driven in the vertical direction. Therefore, the reticle Z tilt stage 82 is positioned in the horizontal direction by the reticle XY stage 81, and can be disposed so as to be inclined with respect to the horizontal plane by the reticle movable shafts 83a and 83b. A reticle moving mirror 98 is arranged at the end of the reticle Z tilt stage 82. The arrangement position of the reticle Z tilt stage 82 is measured by a reticle laser interferometer 99 arranged to face the reticle moving mirror 98.

  On the wafer stage 32, a product wafer coated with a product resist to which a product mask pattern image is transferred and a test wafer coated with a test resist to which a test mask pattern image is transferred are arranged. The wafer stage 32 is for wafers connected to the wafer XY stage 91 by the wafer XY stage 91, the wafer movable shafts 93a and 93b disposed on the wafer XY stage 91, and the wafer movable shafts 93a and 93b, respectively. A Z-tilt stage 92 is provided. A wafer stage drive unit 94 is connected to the wafer stage 32. The wafer stage drive unit 94 scans the wafer XY stage 91 in the horizontal direction. Each of the wafer movable shafts 93a and 93b is driven in the vertical direction. Therefore, the wafer Z tilting stage 92 can be positioned in the horizontal direction by the wafer XY stage 91 and can be disposed with an inclination with respect to the horizontal plane by the wafer movable shafts 93a and 93b. A wafer moving mirror 96 is disposed at the end of the wafer Z tilt stage 92. The arrangement position of the wafer Z tilt stage 92 is measured by a wafer laser interferometer 95 arranged to face the wafer moving mirror 96.

  An SEM or the like can be used as the electron microscope apparatus 332 shown in FIG. The electron microscope apparatus 332 irradiates the product resist pattern formed on the developed product resist with an electron beam after the exposure apparatus 3 projects the product mask pattern. Furthermore, the electron microscope apparatus 332 detects secondary electrons generated from the product resist pattern irradiated with the electron beam, and acquires a “product secondary electron signal waveform”. The electron microscope apparatus 332 irradiates the test resist pattern formed on the developed test resist with an electron beam after the test mask pattern is projected by the exposure apparatus 3. Further, the electron microscope apparatus 332 detects secondary electrons generated from the test resist pattern irradiated with the electron beam, and acquires a “model secondary electron signal waveform”. The electron microscope apparatus 332 acquires the line width CD of the test resist pattern and the product resist pattern. FIG. 3 is a schematic diagram of an SEM image of the test resist pattern 5 observed from the upper surface by the electron microscope apparatus 332, and FIG. 4 is a cross-sectional view of the test resist pattern 5 viewed from the AA direction in FIG. The cross-sectional shape of the test resist pattern 5 arranged on the test wafer 50 is a trapezoid, and has a line width CD of the lower base and a “model film thickness h” corresponding to a vertical distance between the upper base and the lower base. The signal intensity of secondary electrons detected from the test resist pattern 5 by the electron microscope apparatus 332 appears as white bands 7a and 7b in the schematic diagram of the SEM image shown in FIG. 3 because the edge is stronger than the flat part. Therefore, the signal intensity peaks corresponding to the white bands 7a and 7b also appear in the “model secondary electron signal waveform” shown in FIG. 5 acquired by the electron microscope apparatus 332. A film thickness measuring device 333 is further connected to the CPU 300. As the film thickness measuring device 333, SEM, FIB, TEM, AFM, or the like can be used. The film thickness measuring device 333 measures the “model film thickness h” of the test resist pattern 5 shown in FIG. When SEM is used, the film thickness measuring device 333 shown in FIG. 1 observes the cross section of the test resist pattern 5 in order to improve accuracy.

  The CPU 300 further includes an exposure apparatus control unit 326, a dimensional standard verification unit 360, a model feature amount extraction unit 341, a model function calculation unit 342, a film thickness function calculation unit 343, and an exposure function calculation unit 347. The exposure apparatus control unit 326 sets an exposure environment that matches the exposure conditions in the exposure apparatus 3. For example, the reticle stage driving unit 97 and the wafer stage driving unit 94 shown in FIG. 2 are driven to move the reticle stage 15 and the wafer stage 32, and the arrangement position, the scanning direction, the scanning speed, and the like of the reticle laser interferometer 99 are set. The exposure environment is set by monitoring with the wafer laser interferometer 95.

  The dimensional standard verification unit 360 shown in FIG. 1 verifies whether or not the line width CD of the lower base of the test resist pattern 5 shown in FIG. 4 satisfies the dimensional standard, and if it does not satisfy the dimensional standard, extracts the model feature amount The test resist pattern 5 is excluded from the processing target of the part 341. Here, the “dimension standard” is given by the range of length allowed by the line width CD of the test resist pattern 5 or the like.

  The model feature quantity extraction unit 341 shown in FIG. 1 extracts “model feature quantity” from the model secondary electron signal waveform shown in FIG. The “model feature amount” is a quantification of features appearing in the model secondary electron signal waveform. In the example shown in FIG. 6, the model feature amount extraction unit 341 has a lower base line width f1 corresponding to the lower base line width CD of the test resist pattern 5 shown in FIG. 3, an upper base line width f2 corresponding to the upper base line width, Each of the peak intervals f3 which are the peak intervals of the white bands 7a and 7b is extracted from the model secondary electron signal waveform as model feature amounts f1 to f3. Further, the model feature amount extraction unit 341 shown in FIG. 1 includes a first white band width f4 that is the width of the white band 7a shown in FIG. 6 and secondary electron signals from the peak of the white band 7a to the coordinates corresponding to the edge of the upper base. 1st roundness f5 which is the integrated area of the waveform, 1st upper part which is the area where the secondary electron signal waveform is integrated from the peak of the white band 7a to the coordinates where the intensity between the peak intensity and the intensity at the upper base is obtained Model features of area f6 and first lower area f7, which is the area obtained by subtracting the first upper area f6 from the area obtained by integrating the secondary electron signal waveform from the peak of the white band 7a to the coordinates corresponding to the edge of the lower base The quantities f4 to f7 are extracted from the model secondary electron signal waveform. Also, the model feature quantity extraction unit 341 shown in FIG. 1 has a second white band width f8 which is the width of the white band 7b shown in FIG. 6, and the secondary electron signal waveform from the peak of the white band 7b to the coordinates corresponding to the edge of the upper base. The second rounding amount f9, which is the integrated area, and the second upper area, which is the integrated area of the secondary electron signal waveform from the peak of the white band 7b to the coordinates at which the intensity at the peak and the intensity at the upper base are intermediate Each model feature amount of f10 and the second lower area f11, which is the area obtained by subtracting the second upper area f10 from the area obtained by integrating the secondary electron signal waveform from the peak of the white band 7b to the coordinates corresponding to the edge of the lower base f8 to f11 are extracted from the model secondary electron signal waveform. The model feature quantity extraction unit 341 shown in FIG. 1 creates a data set including the model feature quantity, the exposure conditions used when creating the test resist pattern, and the dimensional standard of the test resist pattern.

The model function calculation unit 342 shown in FIG. 1 calculates the bottom base line width f1 shown in FIG. 6 for each of a plurality of test resist patterns produced by projecting the same test mask pattern under a plurality of focus conditions and exposure amounts. Collect the dataset that contains it. Further, the model function calculation unit 342 shown in FIG. 1 approximates the correlation between the collected plurality of bottom base line widths f1 and the corresponding focus conditions and exposure amounts, and as shown in FIG. 7, the bottom base line width f1 and the focus conditions And a model function with the exposure amount as an unknown. Similarly, the model function calculation unit 342 shown in FIG. 1 includes an upper base line width f2, a peak interval f3, a first white band width f4, a first rounding amount f5, a first upper area f6, and a first lower area shown in FIG. For each of f7, second white band width f8, second roundness f9, second upper area f10, and second lower area f11, a model function that approximates the correlation with the focus condition and the exposure amount is calculated. Examples of a plurality of model functions are shown in the following equations (1) to (3). In the equations (1) to (3), Fc is a focus condition, D is an exposure amount, and A _{1 to} A ₁₂ are constants.

f1 = A ₁ × Fc × D + A ₂ … (1)
f2 = A ₃ × Fc ² + A ₄ × Fc + A ₅ × D ² + A ₆ × D + A ₇ … (2)
f3 = A ₈ × Fc ² + A ₉ × Fc -A ₁₀ × D ² + A ₁₁ × D + A ₁₂ … (3)
The film thickness function calculation unit 343 shown in FIG. 1 is a model film thickness h shown in FIG. 4 for each of a plurality of test resist patterns produced by projecting the same test mask pattern under a plurality of focus conditions and exposure amounts. To collect. Further, the film thickness function calculation unit 343 approximates the correlation between the collected model film thicknesses h and the corresponding focus condition and exposure amount, and as shown in FIG. 8, the film thickness, focus condition, and exposure amount are calculated. Calculate the film thickness function as an unknown number. An example of the film thickness function is shown in the following formula (4). In the formula (4), B _{1 to} B ₇ are constants.

h = B ₁ × Fc ³ + B ₂ × Fc ² + B ₃ × Fc + B ₄ × D ³ + B ₅ × D ² + B ₆ × D + B ₇ … (4)
The product feature quantity extraction unit 345 shown in FIG. 1 calculates the bottom base line width f1, the top base line width f2, the peak interval f3, the first white band width f4, the first roundness f5, and the first top from the product secondary electron signal waveform. The product feature quantities of the area f6, the first lower area f7, the second white band width f8, the second roundness f9, the second upper area f10, and the second lower area f11 are extracted. Each definition of the product feature value is the same as the model feature value shown in FIG.

The exposure function calculation unit 347 substitutes the value of the lower base line width f1 extracted from the product secondary electron signal waveform into the model function with the lower base line width f1, the focus condition, and the exposure amount as unknowns, and the focus condition and exposure An exposure function with the amount unknown is calculated. Similarly, the top bottom line width f2, the peak interval f3, the first white band width f4, the first rounding amount f5, the first upper area f6, the first lower area f7, the second white band width f8, the second rounding amount f9, Each of the second upper area f10 and the second lower area f11 is also substituted into the corresponding model function, and simultaneous equations composed of a group of exposure functions are derived. Examples of a group of exposure functions are shown in the following equations (5) to (7). In the equations (5) to (7), C _{1 to} C ₉ are constants.

Fc = C ₁ × D + C ₂ (5)
D = C ₃ × Fc ² + C ₄ × Fc + C ₅ … (6)
D =-C ₇ × Fc ² + C ₈ × Fc + C ₉ … (7)
As shown in FIG. 9, the film thickness calculation unit 346 calculates a calculated exposure condition defined by a calculated focus condition and a calculated exposure amount that are solutions of the calculated simultaneous equations. Further, the film thickness calculation unit 346 substitutes the values of the calculated focus condition and the calculated exposure dose into the film thickness function shown in FIG. 8 where the film thickness, the focus condition, and the exposure dose are unknowns, and the film of the product resist pattern Calculate the thickness. Specifically, the calculated focus condition Fc and the calculated exposure dose D, which are solutions of the simultaneous equations of the above formulas (5) to (7), are substituted into the formula (4), and the film thickness h of the product resist pattern is calculated. .

A data storage device 200 is further connected to the CPU 300. The data storage device 200 includes a lithography condition storage unit 201, a dimension standard storage unit 203, a model function storage unit 305, and a film thickness function storage unit 306. The lithography condition storage unit 201 stores a database of exposure conditions of the exposure apparatus 3. FIG. 10 is an example of a database of exposure conditions, and n (n is a natural number) focus conditions F ₁ and F when a test mask pattern or a product mask pattern is step-and-scan projected by the exposure apparatus 3 shown in FIG. _2, F _{3, ·····,} the exposure amount D ₁ of the street F _i and _{n, D 2, D 3,} ·····, respectively which is a combination exposure conditions 6AA of D _j, 6AB, 6AC, ..., 6AN, 6BA, 6BB, 6BC, ..., 6BN, 6CA, 6CB, 6CC, ..., 6BN, ..., 6NA, 6NB, 6NC, ... ..., 6NN is stored. Here, the focal condition refers to a focal direction distance of a focal position of the projection optical system 42 with respect to a resist surface applied to a wafer arranged on the wafer stage 32 of the exposure apparatus shown in FIG. The lithography condition storage unit 201 also stores exposure conditions such as the numerical aperture (NA) of the projection optical system 42 of the exposure apparatus 3, the coherence factor σ, and the annular shielding rate of the illumination light source 41. A dimension standard storage unit 203 shown in FIG. 1 stores a plurality of dimension standards used when the dimension standard verification unit 360 verifies the line width CD of the test resist pattern 5. The model function storage unit 305 stores the model function calculated by the model function calculation unit 342. The film thickness function storage unit 306 stores the film thickness function calculated by the film thickness function calculation unit 343.

  An input device 312, an output device 313, a program storage device 330, and a temporary storage device 331 are further connected to the CPU 300. As the input device 312, for example, a keyboard and a pointing device such as a mouse can be used. As the output device 313, an image display device such as a liquid crystal display and a monitor, a printer, and the like can be used. The program storage device 330 stores an operating system that controls the CPU 300 and the like. The temporary storage device 331 sequentially stores the calculation results by the CPU 300. As the program storage device 330 and the temporary storage device 331, for example, a recording medium for recording a program such as a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, or a magnetic tape can be used.

  Next, the calculation method of the model function and the film thickness function according to the first embodiment will be described using the flowchart shown in FIG.

  (a) In step S100, the exposure apparatus control unit 326 shown in FIG. 1 reads the exposure conditions 6AA to 6NN shown in FIG. A mask having a test mask pattern is placed on reticle stage 15 shown in FIG. 2, and a wafer coated with a test resist is placed on wafer stage 32. The exposure apparatus control unit 326 shown in FIG. 1 sets the exposure environment of the exposure apparatus 3, and projects a test mask pattern image on the test resist in a matrix form as shown in FIG. 10 under each of the exposure conditions 6AA to 6NN. Thereafter, the test resist is subjected to post-exposure baking (PEB) and development processing. As a result, a wafer having test resist patterns arranged in a matrix according to a plurality of exposure conditions 6AA to 6NN is obtained.

  (b) In step S101, the actual measurement value of the line width CD shown in FIG. 4 of each of the plurality of test resist patterns is measured by the electron microscope apparatus 332 shown in FIG. The dimension standard verification unit 360 reads the dimension standard stored in the dimension standard storage unit 203, and verifies whether or not the actually measured dimension value of the line width CD of each of the plurality of test resist patterns satisfies the dimension standard. The dimension standard verification unit 360 determines to exclude those that do not satisfy the dimension standard from the following steps.

  (c) In step S102, each of the plurality of test resist patterns satisfying the dimension standard is observed with the electron microscope apparatus 332 shown in FIG. 1, and a plurality of model secondary electron signal waveforms are obtained. In step S103, the model feature amount extraction unit 341 generates a lower base line width f1, an upper base line width f2, a peak interval f3, a first white band width f4, a first rounding amount f5, a first round amount f5, and the like shown in FIG. The model feature amounts of the first upper area f6, the first lower area f7, the second white band width f8, the second roundness f9, the second upper area f10, and the second lower area f11 are extracted. Next, the model feature quantity extraction unit 341 shown in FIG. 1 reads out the exposure conditions 6AA to 6NN shown in FIG. 10 used at the time of producing each of the plurality of test resist patterns from the lithography condition storage unit 201. Also, the model feature quantity extraction unit 341 shown in FIG. 1 reads out the dimensional standard verified when a plurality of test resist patterns are satisfied from the dimensional standard storage unit 203. The model feature quantity extraction unit 341 creates a data set including the model feature quantity of each of the plurality of test resist patterns, the exposure conditions 6AA to 6NN used at the time of fabrication, and the dimension standard, and the data set is shown in FIG. To the model function calculation unit 342 shown.

  (d) In step S104, the model function calculation unit 342 calculates the correlation between the bottom base line width f1 shown in FIG. 6 of the test resist pattern and the focus condition and the exposure amount set in the exposure conditions 6AA to 6NN shown in FIG. The model function shown in FIG. 7 is calculated by approximating the lower base line width f1, the focus condition, and the exposure amount as unknowns. Similarly, the model function calculation unit 342 includes an upper base line width f2, a peak interval f3, a first white band width f4, a first rounding amount f5, a first upper area f6, a first lower area f7, a second white band width f8, For each of the second roundness f9, the second upper area f10, and the second lower area f11, a model function that approximates the correlation with the focus condition and the exposure amount is calculated. The model function calculation unit 342 stores the calculated plurality of model functions in the model function storage unit 305 together with the dimension standard.

  (e) In step S105, the model film thickness h shown in FIG. 4 for each of the plurality of test resist patterns is measured by the film thickness measuring device 333 shown in FIG. Next, the film thickness measuring device 333 sends the model film thickness h of each of the plurality of test resist patterns to the film thickness function calculating unit 343. In step S106, the film thickness function calculation unit 343 reads from the lithography condition storage unit 201 the exposure conditions 6AA to 6NN shown in FIG. 10 used when each of the plurality of test resist patterns is formed. Further, the film thickness function calculation unit 343 shown in FIG. 1 reads out the dimensional standard verified when a plurality of test resist patterns satisfy the dimensional standard storage unit 203. Next, the film thickness function calculation unit 343 approximates the correlation between the model film thickness h of the test resist pattern, the focus condition set in the exposure conditions 6AA to 6NN used when the test resist pattern was created, and the exposure amount, A film thickness function shown in FIG. 8 is calculated with the model film thickness h, the focus condition, and the exposure amount as unknowns. The film thickness function calculation unit 343 stores the calculated film thickness function in the film thickness function storage unit 306 together with the dimension standard. The film thickness function calculated here corresponds to the dimensional standard.

  As described above, according to the calculation method of the model function and the film thickness function shown in FIG. 11, the model function and the film thickness function can be calculated based on the test resist pattern verified as satisfying the size standard in step S101. In addition, by repeatedly performing the calculation method of the model function and the film thickness function shown in FIG. 11 while changing the dimension standard used in step S101, a plurality of model functions and film thickness functions corresponding to each of the plurality of dimension standards are performed. Can be calculated and stored in the model function storage unit 305 and the film thickness function storage unit 306, respectively.

  Next, a film thickness measuring method according to the first embodiment will be described using the flowchart shown in FIG.

  (a) In step S200, a mask having a product mask pattern is placed on reticle stage 15 shown in FIG. 2, and a wafer coated with product resist is placed on wafer stage 32. The exposure apparatus control unit 326 shown in FIG. 1 sets the exposure environment of the exposure apparatus 3 and projects a product mask pattern on the product resist. After exposure, the product resist is subjected to post-exposure baking (PEB) and development treatment to obtain a product resist pattern.

  (b) In step S201, the product resist pattern is observed with the electron microscope apparatus 332, and the actual measurement value of the line width CD of the product resist pattern is measured. In step S202, the product secondary electron signal waveform of the product resist pattern is acquired by the electron microscope apparatus 332. In step S203, the product feature quantity extraction unit 345 calculates the lower base line width f1, the upper base line width f2, the peak interval f3, the first white band width f4, the first rounding amount f5, the first upper area from the product secondary electron signal waveform. Product feature values of f6, first lower area f7, second white band width f8, second roundness f9, second upper area f10, and second lower area f11 are extracted. Next, the product feature amount extraction unit 345 sends the product feature amount to the exposure function calculation unit 347.

  (g) In step S204, the exposure function calculation unit 347 reads from the model function storage unit 305 a plurality of model functions created in accordance with the dimensional standard corresponding to the actual measurement value of the line width CD of the product resist pattern. In step S205, the exposure function calculation unit 347 reads from the film thickness function storage unit 306 a film thickness function created according to the dimensional standard corresponding to the line width CD of the product resist pattern. In step S206, the exposure function calculation unit 347 substitutes the value of the lower base line width f1 extracted from the product secondary electron signal waveform into the model function with the lower base line width f1, the focus condition, and the exposure amount as unknowns, An exposure function with unknown conditions and exposure amount is calculated. Similarly, the top bottom line width f2, the peak interval f3, the first white band width f4, the first rounding amount f5, the first upper area f6, the first lower area f7, the second white band width f8, the second rounding amount f9, Each of the second upper area f10 and the second lower area f11 is also substituted into the corresponding model function, and simultaneous equations composed of a group of exposure functions are derived.

  (h) In step S207, the film thickness calculation unit 346 calculates a calculated exposure deviation and a calculated exposure amount, which are solutions of the derived simultaneous equations, as shown in FIG. In step S208, the film thickness calculation unit 346 substitutes the values of the calculated exposure deviation and the calculated exposure amount into the film thickness function shown in FIG. 8 where the film thickness, the focus condition, and the exposure amount are unknown, The film thickness of the product resist pattern after the lithography process such as development processing is calculated as the film thickness of the “product pattern”.

  As described above, if the film thickness measurement system and the film thickness measurement method according to the first embodiment shown in FIGS. 1 and 12 are used, the film thickness of the product resist pattern based on the secondary electron signal waveform of the electron microscope apparatus 332 Can be measured with high accuracy by non-destructive inspection. Conventionally, the electron microscope apparatus 332 is useful for two-dimensional shape observation, but the accuracy of three-dimensional shape measurement such as height measurement of a three-dimensional pattern has been considered to be low when the three-dimensional pattern is observed from the upper surface. On the other hand, according to the film thickness measurement method shown in FIG. 12, the film thickness function acquired in step S205 is the model film thickness measured with high accuracy by the film thickness measuring device 333 in step S105 in FIG. It is calculated based on. Further, in step S205 to S208 in FIG. 12, the product function amount extracted from the product secondary electron signal waveform of the product resist pattern, the model function and the film thickness created by the dimensional standard corresponding to the line width CD of the product resist pattern Substitute into the function to calculate the film thickness of the product resist pattern. Therefore, since the film thickness of the product resist pattern is calculated based on the model film thickness of the test resist pattern measured with high accuracy by the destructive inspection, the reliability is very high. Since the electron microscope apparatus 332 can use a CD-SEM that has been used for line width CD measurement of a resist pattern in the past, no new capital investment is required. Furthermore, since the electron microscope apparatus 332 has a shorter measurement time than the AFM, the manufacturing time of the semiconductor device can be shortened.

(Second embodiment)
In the film thickness measurement system according to the second embodiment of the present invention, as shown in FIG. 13, a simulator 325, a mask manufacturing apparatus 30, and an etching apparatus 31 are further connected to the CPU 300. The simulator 325 includes a Fourier transform program that calculates the light intensity of the projected image when the product mask pattern is projected onto the resist surface by the exposure apparatus 3, and a lithography simulation program such as a string model that calculates the surface shape of the resist after development. Execute and calculate a predicted resist pattern. The mask manufacturing apparatus 30 is an apparatus that manufactures a mask having a product mask pattern arranged on the reticle stage 15 shown in FIG. As the mask manufacturing apparatus 30 shown in FIG. 13, an electron beam (EB) drawing apparatus or a laser drawing apparatus that reads mask data and draws a product mask pattern on a mask substrate can be used. The etching apparatus 31 selectively removes the conductive film such as aluminum (Al) deposited on the wafer by anisotropic etching.

  The CPU 300 of the film thickness measurement system according to the second embodiment further includes an optical proximity effect correction unit 348, a dangerous part extraction unit 349, an inspection unit 350, and an error determination unit 351. The optical proximity effect correction unit 348 performs layer processing and boolean processing on the design data of the integrated circuit pattern, and further performs optical proximity effect correction (OPC) processing. The optical proximity effect correction unit 348 converts the data format of the design data into a format that can be read by the mask manufacturing apparatus 30, and generates mask data. The dangerous part extraction unit 349 inspects the line width CD of the predicted resist pattern predicted by the simulator 325, and extracts a part having a line width CD close to the manufacturing limit as a “dangerous part”. In the example shown in FIG. 14, from the predicted resist pattern, dangerous portions 61a and 61b with a line width CD of 100 nm to 110 nm, dangerous portions 62a, 62b, 62c, 62d, 62e with a line width CD of 110 nm to 120 nm, and a line width CD Extracts each of the dangerous parts 63a, 63b, 63c, 63d, 63e, 63f from 120 nm to 130 nm.

  The inspection unit 350 inspects whether the line width CD and the film thickness of the product resist pattern that are predicted to be dangerous are equal to or greater than the manufacturing limit threshold, and proceeds to the etching process of the conductive film masked with the product resist pattern. Determine whether or not. Further, the inspection unit 350 analyzes the SEM image of the integrated circuit pattern formed by selectively removing the conductive film masked with the product resist pattern, and inspects whether there is a disconnection defect in the integrated circuit pattern. The error determination unit 351 determines whether or not the part where the line width CD and the film thickness of the product resist pattern are equal to or less than the threshold can be dealt with by redoing the OPC process. For example, it is determined whether or not the line width CD and the film thickness of the product resist pattern can be maintained at a threshold value or more by adding the assist pattern. When it is determined that the re-execution of the OPC process cannot cope, the error determination unit 351 determines that the design data needs to be redesigned.

  Furthermore, the data storage device 200 of the film thickness measurement system according to the second embodiment includes a circuit pattern storage unit 202, a mask data storage unit 204, a predicted pattern storage unit 205, a dangerous part storage unit 206, and a threshold storage unit 207. Have. The circuit pattern storage unit 202 stores design data of the integrated circuit pattern of the semiconductor device as CAD data or the like. The mask data storage unit 204 stores the mask data subjected to the OPC process by the optical proximity effect correction unit 348. The predicted pattern storage unit 205 stores the predicted resist pattern predicted by the simulator 325. The dangerous part storage unit 206 stores the coordinates of the dangerous part extracted by the dangerous part extraction unit 349 on the wafer. The threshold value storage unit 207 stores a manufacturing resist pattern line width CD and a film thickness manufacturing limit threshold value that the inspection unit 350 refers to.

  Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to the flowchart shown in FIG.

  (a) In step S301, the optical proximity effect correction unit 348 shown in FIG. 13 reads the design data of the integrated circuit pattern of the semiconductor device stored in the circuit pattern storage unit 202. In step S302, the optical proximity effect correction unit 348 performs OPC processing on the integrated circuit pattern to generate mask data. The optical proximity effect correction unit 348 stores the generated mask data in the mask data storage unit 204.

  (b) In step S303, the simulator 325 reads the mask data stored in the mask data storage unit 204. Next, the simulator 325 projects the product mask pattern included in the mask data with the exposure apparatus 3 onto the product resist applied on the product wafer, and predicts the shape of the predicted resist pattern formed by developing the product resist. . The simulator 325 stores the predicted resist pattern in the predicted pattern storage unit 205. In step S304, the dangerous part extraction unit 349 reads the predicted resist pattern stored in the predicted pattern storage unit 205. Next, the dangerous part extraction unit 349 measures the line width CD of the predicted resist pattern, and extracts a part having a line width CD close to the manufacturing limit as a dangerous part. The dangerous part extraction unit 349 stores the extracted coordinates of the dangerous part on the product wafer in the dangerous part storage unit 206.

  (c) In step S305, the mask manufacturing apparatus 30 manufactures a product mask having a product mask pattern based on the mask data stored in the mask data storage unit 204. In step S306, a product wafer is used as a substrate to be processed, and a conductor such as aluminum (Al) or an aluminum alloy (Al-Si, Al-Cu-Si, etc.) is deposited on the substrate to be processed by sputtering or vapor deposition. Then, a conductive layer is formed to constitute a new substrate to be processed. That is, the “substrate to be processed” is changed to a “new substrate to be processed” as the manufacturing process proceeds, and is defined as a substrate on which a current processing process is performed. In step S307, a product resist is spin-coated on the substrate to be processed using a spin coater or the like. In step S308, the product mask having the product mask pattern is placed on the reticle stage 15 shown in FIG. 2, and the substrate to be processed is placed on the wafer stage 32. The exposure apparatus control unit 326 shown in FIG. 1 sets the exposure environment of the exposure apparatus 3 and projects a product mask pattern on the substrate to be processed. After the exposure, the product resist of the substrate to be processed is subjected to post-exposure baking (PEB) and development processing to obtain a product resist pattern corresponding to each wiring pattern included in the integrated circuit pattern.

  (d) In step S309, the product resist pattern existing at the coordinates predicted as the dangerous part is observed with the electron microscope apparatus 332, and the line width CD and the product secondary electron signal waveform are obtained. In step S310, the product feature amount extraction unit 345 extracts a plurality of product feature amounts in the same manner as in step S205 in FIG. Next, the product feature amount extraction unit 345 sends a data set of the line width CD and the product feature amount of each of the plurality of product resist patterns existing at the coordinates predicted as the dangerous portion to the exposure function calculation unit 347. In step S311, the exposure function calculation unit 347 reads from the model function storage unit 305 a plurality of model functions created with a dimensional standard that matches the line width CD of the product resist pattern. Next, the exposure function calculation unit 347 substitutes the values of the plurality of product feature amounts into the plurality of model functions that have been read, and calculates a plurality of exposure functions.

  (e) In step S312, as shown in FIG. 9, the film thickness calculation unit 346 calculates the calculated exposure deviation and the calculated exposure amount, which are solutions of the calculated simultaneous equations of the plurality of exposure functions, for each dangerous part. . In step S313, the film thickness calculation unit 346 reads from the film thickness function storage unit 306 a film thickness function shown in FIG. 8 created with a dimensional standard that matches the line width CD of the dangerous part. Next, the film thickness calculation unit 346 substitutes the values of the calculated exposure deviation and the calculated exposure dose into the read film thickness function, and calculates the film thickness of the product resist pattern for each dangerous part. In step S314, the inspection unit 350 compares the film thickness of the product resist pattern calculated for each dangerous part with the threshold value stored in the threshold value storage unit 207, and the product resist pattern has a film thickness equal to or greater than the threshold value. Check if it is.

  (f) In step S315, the inspection unit 350 determines whether to proceed to the etching process based on the comparison between the film thickness of the product resist pattern and the threshold value. If it is determined to proceed to the etching process, the process proceeds to step S316. If it is determined not to proceed to the etching process, the process proceeds to step S320. In step S320, the error determination unit 351 determines whether the dangerous part can be dealt with by redoing the OPC process or whether the design change of the integrated circuit pattern is required. If it is possible to cope with the redoing of the OPC process, the process returns to step S302, and the optical proximity effect correcting unit 348 changes the parameter of the OPC process and redoes the OPC process. If it is necessary to change the design of the integrated circuit pattern, the process returns to step S301, and the optical proximity effect correction unit 348 reads out the design data of the redesigned integrated circuit pattern from the circuit pattern storage unit 202.

  (g) In step S316, the etching apparatus 31 selectively removes the conductive film using the product resist pattern as a mask to form an integrated circuit pattern on the substrate to be processed. In step S317, the integrated circuit pattern formed by the electron microscope apparatus 332 is observed to obtain an SEM image of the integrated circuit pattern. The inspection unit 350 analyzes the SEM image of the integrated circuit pattern and inspects whether there is a disconnection defect or the like in the integrated circuit pattern. In step S318, the inspection unit 350 determines whether to proceed to the next process based on the inspection result. If it is determined to proceed to the next process, the process proceeds to step S319. If it is determined not to proceed to the next process, the process proceeds to step S320. In step S319, the formation of the insulating film and the circuit pattern is repeated to complete the semiconductor device.

As described above, according to the film thickness measurement system and the semiconductor device manufacturing method according to the second embodiment shown in FIGS. 13 and 15, the line width CD of the part of the product resist pattern predicted as a dangerous part by the simulator 325. Not only measurement but also highly accurate film thickness measurement is possible by nondestructive inspection. In the past, the product resist pattern part that was predicted to be a dangerous part in the simulation was determined only by measuring the line width CD using a two-dimensional shape measuring device such as SEM and proceeding to the next process. . In the example shown in FIG. 16, the line width CD of the dangerous portion 151 of the resist pattern 51 indicated by the thick line and the line width CD of the design data indicated by the thin line are compared and verified. As shown in FIG. 20, the design line width CD of the dangerous portion 151 is 112 nm, the actually measured line width CD is 119.6 nm, and the error is 6.8%. When the error threshold is 7%, it is determined that the dangerous portion 151 can proceed to the next process. In the example shown in FIG. 17, the line width CD of the dangerous portion 152 indicated by the thick line of the resist pattern 52 is compared with the line width CD of the design data indicated by the thin line. As shown in FIG. 20, the design line width CD of the critical portion 152 is 112 nm, the actually measured line width CD is 117.6 nm, and the error is 5.0%. When the error threshold is 7%, it is determined that the dangerous portion 152 can proceed to the next process. In the example shown in FIG. 18, the line width CD of the dangerous portion 153 of the resist pattern 53 indicated by the bold line is compared with the line width CD of the design data indicated by the thin line. As shown in FIG. 20, the design line width CD of the critical portion 153 is 186 nm, the actually measured line width CD is 190.9 nm, and the error is 2.6%. When the error threshold is 7%, it is determined that the dangerous portion 153 can proceed to the next process. In the example shown in FIG. 19, the line width CD of the dangerous portion 155 of the resist pattern 55 indicated by the bold line is compared with the line width CD of the design data indicated by the thin line. As shown in FIG. 20, the design line width CD of the critical portion 155 is 184 nm, the actually measured line width CD is 195.4 nm, and the error is 6.2%. When the error threshold is 7%, it is determined that the dangerous portion 155 can proceed to the next process. However, in the exposure step, the k ₁ factor is represented by equation (8) as it decreases year by year, the only verification of the line width CD proceeding to the next step, a disconnection failure in a wiring pattern formed came out a situation arising .

k ₁ = HP × NA / λ (8)
Here, HP represents a half pitch of the semiconductor device, and λ represents an exposure wavelength. Figure 21 shows the relationship between the half pitch of the memory device and the exposure wavelength, NA, and k ₁ factor, and Figure 22 shows the relationship between the half pitch of the logic device, the exposure wavelength, NA, and k ₁ factor. Show. Since mass production technology for next-generation lithography technology has not been established, it is believed that the life of lithography technology using ArF lasers will extend to the 45 nm generation for memory devices and the 32 nm generation for logic devices. For this reason, the k ₁ factor given by equation (8) decreases year by year, and is approaching the resolution limit of lithography (about k ₁ = 0.25). Therefore, it is important for lithography technology using an ArF laser to take measures against a low k ₁ factor more than ever.

As countermeasures against the decrease of k ₁ factor, in order to improve the process margin, introduction of super-resolution exposure technology using phase shift mask and modified illumination, etc., high resolution using thin film resist and multilayer resist process etc. The introduction of a resist process and the like, and the introduction of techniques for controlling error factors of the lithography process such as mask error, lens aberration error, illumination shape error, exposure amount error, and focus error with high accuracy are being studied. Further, as a countermeasure against a decrease in the k ₁ factor, a transition from rule-based OPC to model-based OPC is performed in order to increase the transfer fidelity of the design pattern in the exposure process. Approaches the resolution limit of the future k ₁ factor lithography, it is necessary to introduce a stronger super resolution exposure technology and multiple exposure such as custom illumination. In order to further increase the transfer fidelity of the design pattern in the exposure process, the line width CD and film thickness management of the part judged as a dangerous part in the simulation are more important from the design stage to the completion of the semiconductor device. come.

The resist pattern k ₁ factor is formed when the projection of the mask pattern which has been OPC process shown in FIG. 23 (a) in the case of 0.40 shown in FIG. 23 (b). The resist pattern k ₁ factor is formed when the projection of the mask pattern which has been OPC process shown in FIG. 24 (a) in the case of 0.35 shown in FIG. 24 (b). In this case, two dangerous parts 121a and 121b are confirmed in the resist pattern. The resist pattern k ₁ factor is formed when the projection of the mask pattern which has been OPC process shown in FIG. 25 (a) in the case of 0.30 shown in FIG. 25 (b). In this case, each of the seven dangerous parts 122a, 122b, 122c, 122d, 122e, 122f, 122g is confirmed in the resist pattern. FIG. 23 (b), the FIG. 24 (b), the and as shown in FIG. 25 (b), as the k ₁ factor is if reduced, transcription fidelity increases the number of dangerous parts decreases.

  However, it is not sufficient to redo the OPC process by focusing only on the line width CD of the dangerous part. In the example shown in FIG. 26, a schematic diagram of a plurality of SEM images of a wiring pattern of a 130 nm NAND flash formed using a resist pattern determined to have no problem in line width CD measurement as a mask is shown. Each of the plurality of SEM images is arranged in a matrix with the horizontal axis representing the focus condition when forming the resist pattern and the vertical axis representing the exposure amount when forming the resist pattern. Here, no disconnection failure is confirmed in the wiring pattern formed using the resist pattern formed under the focus condition 0 and the exposure amount 190 as a mask. However, in the wiring pattern formed using the resist pattern formed under the focus condition + 1 and the exposure amount 190 as a mask, a disconnection failure occurs. This is because the resist pattern formed under the focus condition shifted to the plus side caused film slip even if there was no problem with the line width CD, and a sufficient film thickness was not secured for the conductive layer etching process. It is done. Therefore, not only the line width CD management of the dangerous part of the resist pattern but also the film thickness management is important in the manufacturing process of the semiconductor device. On the other hand, according to the film thickness measurement system and the semiconductor device manufacturing method according to the second embodiment shown in FIGS. 13 and 15, the accuracy of the part of the product resist pattern predicted as a dangerous part by the simulator 325 High film thickness measurement is possible by non-destructive inspection, which leads to an improvement in yield and a reduction in manufacturing time in the semiconductor device manufacturing process. The dangerous part can also be used as a pattern to be noted in determining the conditions at the time of manufacturing, or as a dimension monitor part in the manufacturing line.

(Other embodiments)
Although the embodiments of the present invention have been described as described above, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in step S101 of FIG. 11 of the first embodiment, the dimension standard verification unit 360 verifies whether or not the actual measured value of the line width CD of each of the plurality of test resist patterns satisfies the “dimensional standard”. did. On the other hand, the dimension standard verification unit 360 may verify whether or not the dimension design value of each line width CD of the plurality of test resist patterns satisfies the “dimension standard”. In this case, in step S206 of FIG. 12, the exposure function calculation unit 347 can read out a plurality of model functions created by the dimensional standard corresponding to the dimensional design value of the line width CD of the product resist pattern from the model function storage unit 305. That's fine.

  Alternatively, in step S101 in FIG. 11, the dimension standard verification unit 360 may verify whether or not each of the plurality of test resist patterns satisfies the “dimension standard” determined based on the distance from the adjacent pattern. In this case, in step S206 of FIG. 12, the exposure function calculation unit 347 only needs to read a plurality of model functions created by the dimensional standard corresponding to the distance from the adjacent pattern of the product resist pattern from the model function storage unit 305. .

  Furthermore, in step S101 in FIG. 11, the dimension standard verification unit 360 may verify whether or not the “dimension standard” defined based on the pattern density of each of the plurality of test resist patterns is satisfied. In this case, in step S206 of FIG. 12, the exposure function calculation unit 347 may read a plurality of model functions created by the dimensional standard corresponding to the pattern density of the product resist pattern from the model function storage unit 305.

  If it is determined in step S318 in FIG. 15 that the process does not proceed to the next process, the cross-sectional shape of the dangerous part may be measured by a destructive inspection method using the film thickness measuring device 333 shown in FIG. At that time, the film thickness of the dangerous portion, the angle of the side surface, the radius of curvature of the portion where the upper base and the side surface are in contact, and the radius of curvature of the portion where the side surface and the substrate to be processed are in contact may be measured.

  Further, in the embodiment, the method for measuring the film thickness of the product resist pattern after the lithography process has been described. However, in step S316, the conductive film is selectively removed using the product resist pattern as a mask, and then the conductive film is formed on the substrate to be processed. The film thickness measurement method according to the embodiment can be applied to the measurement of the film thickness of the integrated circuit pattern to be formed. Specifically, after step S101, a test circuit pattern made of a conductor or the like is formed using each of the plurality of test resist patterns. Thereafter, the film thickness function is calculated for the test circuit pattern in the same manner as in steps S102 to S105. Further, the secondary electron signal waveform of the integrated circuit pattern is acquired by the electron microscope apparatus 332, and the film thickness of the integrated circuit pattern formed on the substrate to be processed is set to “product pattern” by the same method as in steps S203 to S207. It can be calculated as the film thickness.

  The film thickness measurement method described above can be expressed as a series of processes or operations connected in time series. Therefore, in order to execute the film thickness measurement method by the computer system, the film thickness measurement method shown in FIG. 12 can be realized by a computer program product that specifies a plurality of functions performed by a processor or the like in the computer system. Here, the computer program product refers to a recording medium, a recording device, or the like that can be input and output to a computer system. The recording medium includes a memory device, a magnetic disk device, an optical disk device, and other devices capable of recording other programs. As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is a block diagram which shows the film thickness measurement system which concerns on the 1st Embodiment of this invention. 1 is a schematic diagram showing a reduced projection exposure apparatus according to a first embodiment of the present invention. It is the microscope image which observed the test resist pattern which concerns on the 1st Embodiment of this invention from the upper surface. It is sectional drawing of the test resist pattern which concerns on the 1st Embodiment of this invention. It is a graph (the 1) which shows the model secondary electron signal waveform of the test resist pattern which concerns on the 1st Embodiment of this invention. It is a graph (the 2) which shows the model secondary electron signal waveform of the test resist pattern which concerns on the 1st Embodiment of this invention. It is a graph which shows the model function which concerns on the 1st Embodiment of this invention. It is a graph which shows the film thickness function which concerns on the 1st Embodiment of this invention. It is a graph which shows the exposure function which concerns on the 1st Embodiment of this invention. It is a schematic diagram which shows the exposure conditions of the exposure apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart figure which shows the calculation method of the model function and film thickness function which concern on the 1st Embodiment of this invention. It is a flowchart figure which shows the film thickness measuring method which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the film thickness measurement system which concerns on the 2nd Embodiment of this invention. It is a schematic diagram which shows the prediction resist pattern which concerns on the 2nd Embodiment of this invention. It is a flowchart figure which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a schematic diagram of the 1st scanning electron microscope image of the resist pattern which concerns on the 2nd Embodiment of this invention. It is a schematic diagram of the 2nd scanning electron microscope image of the resist pattern which concerns on the 2nd Embodiment of this invention. It is a schematic diagram of the 3rd scanning electron microscope image of the resist pattern which concerns on the 2nd Embodiment of this invention. It is a schematic diagram of the 4th scanning electron microscope image of the resist pattern which concerns on the 2nd Embodiment of this invention. It is a table | surface which shows the relationship between the design line width which concerns on the 2nd Embodiment of this invention, and measured line width. And half pitch of the memory system devices according to a second embodiment of the present invention, the exposure wavelength, which is a table showing the relationship between the NA, and k _t factor. And half pitch of the logic system device according to a second embodiment of the present invention, the exposure wavelength, which is a table showing the relationship between the NA, and k _t factor. It is a 1st schematic diagram of the resist pattern formed by projecting the mask pattern by which the optical proximity effect correction | amendment which concerns on the 2nd Embodiment of this invention, and a mask pattern is projected. It is the 2nd schematic diagram of the resist pattern formed by projecting the mask pattern by which the optical proximity effect correction | amendment which concerns on the 2nd Embodiment of this invention, and a mask pattern is projected. It is the 3rd schematic diagram of the resist pattern formed by projecting the mask pattern by which the optical proximity effect correction | amendment which concerns on the 2nd Embodiment of this invention was corrected, and a mask pattern. It is a schematic diagram of the scanning electron microscope image of a wiring pattern arrange | positioned in the matrix form of the focus conditions and exposure amount which concern on the 2nd Embodiment of this invention.

Explanation of symbols

5 ... Test resist pattern
6AA, 6AB, 6AC, ..., 6AN, 6BA, 6BB, 6BC, ..., 6BN, 6CA, 6CB, 6CC, ..., 6BN, ..., 6NA, 6NB, 6NC, ..., 6NN ... exposure conditions
203 ... Dimensional standard storage
325 ... Simulator
332 ... Electron microscope device
333 ... Film thickness measuring device
341 ... Model feature extraction unit
342 ... Model function calculator
343 ... Film thickness function calculator
345… Product feature extraction unit
346 ... Thickness calculator
347 ... Exposure function calculator

Claims (5)

Obtaining a product secondary electron signal waveform of a product pattern;
Extracting a plurality of product feature quantities from the product secondary electron signal waveform;
Measuring the film thickness of the product pattern using a plurality of pre-calculated model functions, wherein each of the plurality of model feature quantities and the plurality of exposure conditions of the test pattern having the same dimensional standard as the product pattern is an unknown number; A film thickness measuring method characterized by comprising:   2. The film thickness measuring method according to claim 1, wherein each of the plurality of exposure conditions is at least one of a focus condition and an exposure amount.   The dimensional standard is based on one of an actual measurement value of the product pattern, a dimensional design value of the product pattern, a distance from an adjacent pattern of the product pattern, and a pattern density of the product pattern. 3. The method for measuring a film thickness according to 1 or 2.   4. The film thickness of the product pattern is any one of a film thickness of a product resist pattern after a lithography process and a film thickness of an integrated circuit pattern after an etching process. The film thickness measuring method described in 1. In the central processing unit of the film thickness measurement system,
A procedure for obtaining a product secondary electron signal waveform of a product pattern;
Extracting a plurality of product feature quantities from the product secondary electron signal waveform;
A procedure for measuring the film thickness of the product pattern using a plurality of pre-calculated model functions, wherein each of a plurality of model feature quantities and a plurality of exposure conditions of the test pattern having the same dimensional standard as the product pattern is an unknown. Film thickness measurement program to execute.