JP2006294127A - Voltage step-down circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage step-down circuit which can supply a sufficient operation current without reducing operation response even when a load circuit is operated with lower power source voltage than a step-down level. <P>SOLUTION: The step-down circuit 3 which generates internal power source voltage Vint supplied from external power source voltage VDD to the load circuit is provided with a voltage step-down part 7 generating internal power source voltage Vint by stepping-down the external power source voltage VDD and supplying the internal power source voltage Vint to the load circuit, a switch element 4 supplying directly the external power source voltage VDD to the load circuit, and switch control circuits (5. 6) outputting a drive signal DRV controlling on/off of the switch element 4 in accordance with a level of the external power source voltage VDD. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a step-down circuit, and more particularly to a step-down circuit that generates a power supply voltage (internal power supply voltage) for an internal circuit from an external power supply voltage.

  In recent years, semiconductor devices such as SOC (System On a Chip) have been increasingly required to have high integration, low power consumption, and high speed. In such a semiconductor device, in order to reduce power consumption or protect elements constituting the internal circuit, an operation is performed to step down a power supply voltage (external power supply voltage) supplied from the outside and supply it to the internal circuit. A step-down circuit that generates a voltage (internal power supply voltage) is used. Examples of prior art relating to such a step-down circuit include Patent Documents 1 to 3 and the like.

FIG. 8 is a block diagram showing a semiconductor device including a conventional step-down circuit. As shown in the figure, the step-down circuit 30 is provided in the semiconductor device 31, generates an internal power supply voltage Vint by stepping down the external power supply voltage VDD to a predetermined level, and uses the internal power supply voltage Vint inside the semiconductor device 31. This is supplied to a load circuit 32 which is a circuit (for example, SRAM). Thereby, the load circuit 32 operates using the internal power supply voltage Vint supplied from the external power supply voltage VDD via the step-down circuit 30 as an operation power supply.
Japanese Patent No. 2778199 Japanese Patent No. 2785732 US Pat. No. 5,347,170

  By the way, as shown in FIG. 9, the load circuit (internal circuit) 32 normally operates at the internal power supply voltage Vint generated by the step-down circuit 30 based on the external power supply voltage VDD in the recommended operating power supply voltage range. However, in some cases, in order to suppress the current consumption as much as possible, the operation may be performed with a lower power supply voltage. That is, the load circuit 32 may be operated at an external power supply voltage VDD lower than the step-down level at which the step-down circuit 30 steps down the external power supply voltage VDD based on the external power supply voltage VDD in the recommended operating power supply voltage range.

  However, when the load circuit 32 is operated using the external power supply voltage VDD lower than the step-down level in this way, for example, when the load circuit 32 is in an active state, the current consumed by the load circuit 32 (load current) ) When IL is large, the level of the internal power supply voltage Vint supplied to the load circuit 32 is lowered, and a sufficient operating current originally required may not be supplied. As a result, there is a problem that the operation response of the load circuit 32 is lowered, and there is still room for improvement in this respect.

  The present invention has been made in view of such a conventional situation, and the object thereof is sufficient for a load circuit even when the load circuit is operated with a power supply voltage lower than a step-down level for stepping down an external power supply voltage. An object of the present invention is to provide a step-down circuit capable of supplying an operating current.

  In the following, means for achieving the above object and its operation will be described.

The invention according to claim 1 is a step-down circuit that generates an internal power supply voltage to be supplied to a load circuit from an external power supply voltage, and generates the internal power supply voltage by stepping down the external power supply voltage. A step-down unit that supplies the load circuit to the load circuit, a switch element that directly supplies the external power supply voltage to the load circuit, and a drive signal that controls on / off of the switch element in accordance with the level of the external power supply voltage. And a switch control circuit.

  According to this configuration, the external power supply voltage can be directly supplied to the load circuit through the switch element by performing on / off control of the switch element in accordance with the level of the external power supply voltage. Thus, for example, when operating the load circuit with a power supply voltage lower than the step-down level for stepping down the external power supply voltage, if the external power supply voltage is directly supplied to the load circuit through the switch element, the load circuit A reduction in the level of the internal power supply voltage supplied to the circuit can be suppressed, and a sufficient operating current that is originally required can be supplied to the load circuit.

  According to a second aspect of the present invention, in the step-down circuit according to the first aspect, the switch control circuit is a drive that performs on / off control of the switch element while the step-down unit maintains generation of the internal power supply voltage. The gist is to output a signal.

  According to this configuration, when the external power supply voltage is at a level that turns on the switch element, the internal power supply voltage is supplied to the load circuit from both the step-down unit and the switch element. Thereby, the current supply capability of the step-down circuit can be ensured while preventing an increase in the element size of the switch element.

  According to a third aspect of the present invention, in the step-down circuit according to the first or second aspect, when the external power supply voltage is lower than a predetermined voltage, the switch control circuit outputs a drive signal for turning on the switch element. The gist is to output.

  According to this configuration, the switch control circuit turns on the switch element that directly supplies the external power supply voltage to the load circuit when an external power supply voltage lower than the step-down level is supplied.

  As described above, according to the present invention, even when the load circuit is operated with a power supply voltage lower than the step-down level at which the external power supply voltage is stepped down by the step-down circuit, a sufficient operating current is supplied to the load circuit to load the load circuit. It is possible to suppress a decrease in the operation response of the circuit, and to suppress the addition of a complicated control circuit and an increase in the size of the switch element.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a schematic configuration of a semiconductor device including the step-down circuit according to the present embodiment. The semiconductor device 1 includes a load circuit 2 that is an internal circuit of the semiconductor device 1 and a step-down circuit 3 that generates an internal power supply voltage Vint supplied to the load circuit 2 based on an external power supply voltage VDD.

  The step-down circuit 3 includes a switch element 4. By turning on / off the switch element 4, the internal power supply voltage Vint obtained by stepping down the external power supply voltage VDD to a predetermined step-down level or the external power supply voltage VDD directly The power supply voltage Vint is supplied to the load circuit 2. In the present embodiment, the load circuit 2 is configured by, for example, an SRAM (Static-RAM).

  FIG. 2 is a circuit block diagram showing the configuration of the step-down circuit 3. In addition, the same code | symbol is attached | subjected to the same component as FIG.

The step-down circuit 3 includes a switch element 4, a voltage monitor circuit 5, a switch drive circuit 6, and a step-down unit 7. In the present embodiment, the voltage monitor circuit 5 and the switch drive circuit 6 constitute a switch control circuit.

  The voltage monitor circuit 5 monitors the external power supply voltage VDD, compares the external power supply voltage VDD with the reference voltage Vref output from the step-down unit 7, and generates an activation signal SLEEP that activates the switch drive circuit 6. The switch drive circuit 6 generates a drive signal DRV for turning on / off the switch element 4 based on the activation signal SLEEP output from the voltage monitor circuit 5.

  The switch element 4 is configured by a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) in the present embodiment, an external power supply voltage VDD is applied to the source, and the load circuit (internal circuit) 2 is connected to the drain. A power supply terminal (a supply terminal for the internal power supply voltage Vint) is connected, and a drive signal DRV from the switch drive circuit 6 is supplied to the gate thereof.

  The step-down unit 7 generates an internal power supply voltage Vint obtained by stepping down the external power supply voltage VDD. The step-down unit 7 is a constant voltage circuit having a voltage input voltage output type negative feedback circuit as a basic circuit, and reduces the external power supply voltage VDD by a predetermined step-down based on a reference voltage Vref generated by a reference voltage generation circuit (not shown). An internal power supply voltage Vint lowered to a level is generated. The step-down unit 7 outputs the generated reference voltage Vref to the voltage monitor circuit 5. Since the step-down unit 7 is not a main part of the present invention, a diagram showing a specific configuration is omitted in the present embodiment.

  In the step-down circuit 3 configured as described above, when the switch drive circuit 6 is activated by the activation signal SLEEP from the voltage monitor circuit 5, the switch element 4 (PMOS transistor) is activated by the drive signal DRV from the switch drive circuit 6. The internal power supply voltage Vint is supplied from the step-down unit 7, and the external power supply voltage VDD is directly supplied to the load circuit 2 as the internal power supply voltage Vint through the switched switch element 4. Conversely, when the switch drive circuit 6 is deactivated by the activation signal SLEEP from the voltage monitor circuit 5, the switch element 4 is turned off by the drive signal DRV from the switch drive circuit 6, and the step-down unit 7 outputs the external power supply voltage VDD. Is supplied to the load circuit 2 by the internal power supply voltage Vint that has been stepped down to the step-down level set by the reference voltage Vref.

  Next, the configuration of the voltage monitor circuit 5 will be described.

  As shown in FIG. 3, the voltage monitor circuit 5 includes a differential amplifier 11, an inverter circuit 12, a NOR gate 13, and current sources 14 and 15. The current sources 14 and 15 are circuits for supplying a bias current to the differential amplifier 11 and the inverter circuit 12, respectively.

  The differential amplifier 11 includes a pair of PMOS transistors TP1 and TP2 constituting a current mirror as a load, and N channel type MOS transistors (hereinafter referred to as NMOS transistors) TN1 and TN2 constituting a differential pair transistor. Yes. Specifically, the external power supply voltage VDD is applied to the sources of the PMOS transistors TP1 and TP2 forming a current mirror, and their gates are connected to each other and to the drain of the PMOS transistor TP2. The drains of the PMOS transistors TP1 and TP2 are respectively connected to the drains of the NMOS transistors TN1 and TN2 forming a differential pair transistor, and the sources of the NMOS transistors TN1 and TN2 are grounded via the current source 14. Connected to potential.

The external power supply voltage VDD is input to the gate of the NMOS transistor TN1, the reference voltage Vref is input to the gate of the NMOS transistor TN2, and the external power supply voltage V
A differential amplification voltage Vout obtained by amplifying a voltage difference between DD and the reference voltage Vref is output from a connection point between the NMOS transistor TN1 and the PMOS transistor TP1. The reference voltage Vref is a voltage that sets the step-down level of the external power supply voltage VDD as described above.

  In the differential amplifier 11, the NMOS transistor TN2 on the input side in the differential pair transistor is set to have a higher driving capability than the NMOS transistor TN1 on the output side. Thereby, the differential amplifier 11 outputs the output of the inverter circuit 12 when the external power supply voltage VDD is higher than the reference voltage Vref, that is, when the external power supply voltage VDD is higher than the step-down level set by the reference voltage Vref. Outputs a differential amplification voltage Vout such that becomes H level. Further, when the external power supply voltage VDD coincides with the reference voltage Vref or when the external power supply voltage VDD is lower than the reference voltage Vref, the differential amplification voltage Vout is outputted so that the output of the inverter circuit 12 becomes L level.

  The NOR gate 13 is a two-input NOR gate. The output of the differential amplifier 11 is inverted by the inverter circuit 12 and input to one input terminal, and the ground potential GND is input to the other input terminal. Entered. Therefore, the NOR gate 13 outputs an activation signal SLEEP having a level corresponding to the output of the differential amplifier 11.

  As shown in FIG. 5, voltage monitor circuit 5 configured in this way outputs L level activation signal SLEEP when external power supply voltage VDD is higher than the step-down level. Further, when the external power supply voltage VDD is the same voltage as the step-down level, or when the external power supply voltage VDD is a voltage lower than the step-down level, the activation signal SLEEP is output at a level corresponding to the external power supply voltage VDD.

  Next, the configuration of the switch drive circuit 6 will be described.

  As shown in FIG. 4, the switch drive circuit 6 includes a NAND gate 21 and inverter circuits 22 and 23, and drives the signal obtained by amplifying the activation signal SLEEP from the voltage monitor circuit 5 by the NAND gate 21 through the inverter circuits 22 and 23. Output as signal DRV. The inverter circuit 23 is connected to the switch element 4 (PMOS transistor), and the switch element 4 is gated by the drive signal DRV.

  The NAND gate 21 is a two-input NAND gate. The activation signal SLEEP from the voltage monitor circuit 5 is input to one input terminal, and the external power supply voltage VDD is input to the other input terminal. . Therefore, NAND gate 21 outputs a signal obtained by inverting activation signal SLEEP. That is, the switch drive circuit 6 outputs a signal obtained by inverting the activation signal SLEEP. Specifically, as shown in FIG. 6, when the external power supply voltage VDD is higher than the step-down level, the switch element 4 is turned off based on the L level activation signal SLEEP (FIG. 5). A drive signal DRV (strictly, a drive signal DRV having a level corresponding to the external power supply voltage VDD) is output. Further, when the external power supply voltage VDD is the same voltage as the step-down level or a voltage lower than that, an L level drive that turns on the switch element 4 based on an H level activation signal SLEEP (FIG. 5). The signal DRV is output.

  Next, the operation of the step-down circuit 3 configured as described above will be described.

  As shown in FIG. 7, when the load circuit 2 is operated with the external power supply voltage VDD in the recommended operation power supply voltage range larger than the step-down level, the load circuit 2 operates with the internal power supply voltage Vint supplied through the step-down unit 7. .

  On the other hand, when the load circuit 2 is operated with the external power supply voltage VDD equal to or lower than the step-down level, the voltage monitor circuit 5 outputs an activation signal SLEEP that activates the switch drive circuit 6. That is, at this time, the switch element 4 is turned on by the drive signal DRV from the switch drive circuit 6 while maintaining the supply of the internal power supply voltage Vint from the step-down unit 7, and the external power supply voltage VDD is supplied through the turned on switch element 4. It is directly supplied to the load circuit 2 as it is.

  Thereby, not only when the consumption current (load current) IL of the load circuit 2 is small (for example, when the load circuit 2 is in a standby state), but also when the load current IL is large (for example, when the load circuit 2 is in an active state). Thus, it is possible to suppress the level of the internal power supply voltage Vint from being significantly lowered as in the conventional case (FIG. 9) and being unable to supply the originally required operating current.

  As described above, the following effects can be achieved in the present embodiment.

  (1) The switch element 4 that monitors the external power supply voltage VDD and supplies the external power supply voltage VDD directly to the load circuit 2 when the external power supply voltage VDD is equal to or lower than the step-down level set by the reference voltage Vref is provided. . As a result, when the load circuit 2 is operated at an external power supply voltage VDD lower than the step-down level, the internal power supply voltage Vint decreases due to a large load current IL, for example, the load circuit 2 is in an active state. This can be suitably suppressed.

  (2) The voltage monitor circuit 5 compares the external power supply voltage VDD with the reference voltage Vref, and activates the switch drive circuit 6 when the external power supply voltage VDD is equal to or lower than the step-down level set by the reference voltage Vref. 4 was turned on. With this configuration, the internal power supply voltage Vint supplied to the load circuit 2 can be optimized according to the level of the external power supply voltage VDD.

  (3) When the external power supply voltage VDD is equal to or lower than the step-down level set by the reference voltage Vref, the supply of the internal power supply voltage Vint from the step-down unit 7 is maintained and the drive signal DRV from the switch drive circuit 6 is maintained. The switch element 4 is turned on. As a result, when the external power supply voltage VDD that is lower than the step-down level is supplied, the internal power supply voltage Vint is supplied from both the step-down unit 7 and the switch element 4, which increases the element size of the switch element 4. The current supply capability of the step-down circuit 3 can be ensured while preventing.

  In addition, you may implement the said embodiment, changing into the following aspects (modifications).

  (Modification 1) The NOR gate 13 included in the voltage monitor circuit 5 and the NAND gate 21 included in the switch drive circuit 6 are connected to the ground potential GND and the external power supply voltage VDD, respectively. A control signal may be input.

  (Modification 2) The switch element 4 is not limited to a PMOS transistor, and may be composed of other transistors.

(Modification 3) In the above embodiment, when the external power supply voltage VDD is equal to or lower than the step-down level set by the reference voltage Vref, the switch element 4 is turned on to supply the external power supply voltage VDD directly to the load circuit 2. Although the switch element 4 is turned off when the voltage is higher than the step-down level, the following control is preferable. That is, ideally, the potential of the step-down level is set to be the inflection point of the activation signal SLEEP (the on / off switching point of the switch element 4). In this case, however, the external power supply voltage VDD It is conceivable that the switch element 4 remains on even when is a voltage higher than the step-down level. As a result, there is a concern that a power supply voltage higher than the step-down level is supplied to the load circuit 2. Therefore, in order to prevent this, the inflection point of the activation signal SLEEP is preferably set to a voltage lower than the step-down level.

  (Modification 4) Other design matters regarding the configuration of the above-described embodiment and each modification can be appropriately changed within the scope of the technical idea of the present invention.

  Next, the technical idea of the present invention that can be grasped from the above-described embodiments and modifications will be described below.

(Supplementary note 1) In the step-down circuit according to any one of claims 1 to 3,
The switch control circuit includes:
A voltage monitor circuit that monitors the external power supply voltage and outputs an activation signal according to the level of the external power supply voltage;
A switch drive circuit that generates the drive signal for turning on the switch element when the external power supply voltage is lower than a step-down level for stepping down the external power supply voltage based on the activation signal. A step-down circuit.

  According to this configuration, when the switch element is turned on when the external power supply voltage is lower than the step-down level, supply of a power supply voltage at the step-down level or higher to the load circuit can be suitably suppressed.

1 is a block diagram illustrating a schematic configuration of a semiconductor device including a step-down circuit according to an embodiment. The circuit block diagram which shows the structure of a step-down circuit. The circuit diagram which shows a voltage monitor circuit. The circuit diagram which shows a switch drive circuit. The wave form diagram which shows an activation signal. The wave form diagram which shows a drive signal. The wave form diagram which shows the mode of a displacement of an internal power supply voltage. The block diagram which shows the semiconductor device provided with the conventional step-down circuit. The wave form diagram which shows the mode of the displacement of the conventional internal power supply voltage.

Explanation of symbols

  2: load circuit, 3: step-down circuit, 4: switch element, 5: voltage monitor circuit, 6: switch drive circuit, 7: step-down unit, 11: differential amplifier, 12: inverter circuit, 13: NOR gate, 14, 15: current source, 21: NAND gate, 22, 23: inverter circuit, IL: load current, VDD: external power supply voltage, Vint: internal power supply voltage, Vref: reference voltage, Vout: differential amplification voltage, DRV: drive signal , SLEEP: active signal, TP1, TP2: PMOS transistor, TN1, TN2: NMOS transistor.

Claims (3)

A step-down circuit that generates an internal power supply voltage to be supplied from an external power supply voltage to a load circuit,
A step-down unit that steps down the external power supply voltage to generate the internal power supply voltage and supplies the internal power supply voltage to the load circuit;
A switch element for supplying the external power supply voltage directly to the load circuit;
A switch control circuit that outputs a drive signal for controlling on / off of the switch element in accordance with the level of the external power supply voltage;
A step-down circuit comprising: The switch control circuit outputs a drive signal for on / off control of the switch element while the step-down unit maintains generation of the internal power supply voltage.
The step-down circuit according to claim 1. The switch control circuit outputs a drive signal for controlling the switch element to be turned on when the external power supply voltage is lower than a predetermined voltage;
The step-down circuit according to claim 1 or 2.

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