JP2006293429A - Device and method for random number generation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device for random number generation that generates random numbers having excellent normal distribution characteristics with a very small hardware scale when normal random numbers are generated. <P>SOLUTION: The device for random number generation has an M-series cyclic code generating means (101) of generating an M-series cyclic code having designated cycles, a uniformly random number generating means (102) of generating a plurality of uniformly random numbers each having uniform distribution characteristics based upon the M-series cyclic code, and a normal random number generating means (103) of generating a normal random number having normal distribution characteristics by using the plurality of uniformly random numbers. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a random number generation technique, and more particularly to a random number generation technique having a normal distribution characteristic.

  In color copiers and color printers, image signals input from original image reading devices such as color image scanners and computers are converted to Log conversion, CMYK color space conversion, and printer engine characteristics. After the gamma conversion is performed, pseudo intermediate processing such as error diffusion processing is performed. Normally, in the pseudo-intermediate processing, random number addition processing for intentionally adding a random number to an image signal is performed in order to make the Mach band due to quantization distortion inconspicuous.

  The pseudo intermediate processing is configured by hardware, and when processing of one pixel per cycle is performed, it is necessary to generate a normal random number used for the random number addition processing once per cycle.

  As a method for generating the normal random numbers, the box mueller method, the polar coordinate method, and the central limit theorem are mainly used. Further, methods for generating uniform random numbers mainly include a linear congruential method and a method using an M-sequence cyclic code (see Non-Patent Document 1 below).

  In order not to increase the circuit size of the normal random number generator, a plurality of short bit random numbers are extracted from the long bit uniform random number generated using a method of generating a uniform random number, and the plurality of short bit random numbers are extracted. There is a method of generating normal random numbers using. For example, a long-bit uniform random number is generated from an M-sequence cyclic code, a plurality of short-bit random numbers are extracted from the long-bit uniform random number, and a normal random number is generated using the plurality of short-bit random numbers. There is a way.

  However, in the above method, since the cross-correlation of the plurality of short bit random numbers extracted from the long bit uniform random number becomes strong, the self-regulation of the normal random number generated using the plurality of short bit random numbers. There is a problem that the correlation becomes strong.

  In order to solve the above problem, for example, as shown in FIG. 8, a plurality of uniform random numbers generated by a plurality of M-sequence cyclic code generators 1012 to 1023 having different seeds in the seed registers 1000 to 1011 are bits. There is a technique in which a bit is operated by the operation units 1026 to 1037 and a normal random number is generated by the normal random number generation unit 1025 using the plurality of uniform random numbers. Also, as shown in Patent Document 1 below, an M-sequence cyclic code generator (hereinafter referred to as an EXOR generator) different from the M-sequence cyclic code generator for generating uniform random numbers is prepared, There is a method of generating a normal random number by calculating an exclusive OR for each bit of the random number generated from the M-sequence cyclic code generator and the random number generated from the EXOR generator.

Naoki Mikami, “Algorithm Textbook-Basics and Applications of Algorithms Shown in Practical Programming” CQ Publishing 1996/5 First Edition Japanese Patent Laid-Open No. 11-85474

  However, the normal random number generator for generating normal random numbers with weak autocorrelation as described above includes a plurality of M-sequence cyclic encoders, or EXOR generators, and seeds set in the M-sequence cyclic code generators or the EXOR generators. Therefore, the circuit scale increases accordingly. In addition, as the number of M-sequence cyclic code generators or EXOR generators increases, seed setting for the M-sequence cyclic code generator or EXOR generator becomes difficult.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a random number generation device and a random number generation method for generating random numbers having good normal distribution characteristics with a small hardware scale when generating normal random numbers. It is to provide.

  The random number generation device of the present invention includes an M-sequence cyclic code generation means for generating an M-sequence cyclic code having a predetermined period, and a plurality of uniform random numbers each having uniform distribution characteristics based on the M-sequence cyclic code. Uniform random number generation means for generating and normal random number generation means for generating normal random numbers having normal distribution characteristics using the plurality of uniform random numbers.

  Further, the random number generation device of the present invention includes a uniform random number generating means for generating an M-sequence cyclic code and generating a plurality of uniform random numbers having uniform distribution characteristics based on the M-sequence cyclic code; And normal random number generation means for generating normal random numbers having normal distribution characteristics by adding uniform random numbers.

  The random number generation method according to the present invention includes an M-sequence cyclic code generation step for generating an M-sequence cyclic code having a predetermined period, and a plurality of uniform distribution characteristics each having uniform distribution characteristics based on the M-sequence cyclic code. A uniform random number generating step for generating a random number; and a normal random number generating step for generating a normal random number having a normal distribution characteristic using the plurality of uniform random numbers.

  Further, the random number generation method of the present invention includes a uniform random number generation step of generating an M-sequence cyclic code and generating a plurality of uniform random numbers having uniform distribution characteristics based on the M-sequence cyclic code, And a normal random number generation step of generating normal random numbers having normal distribution characteristics by adding uniform random numbers.

  When generating normal random numbers, random numbers having good normal distribution characteristics can be generated with a small hardware scale.

(First embodiment)
FIG. 1 shows an outline of a uniform random number generation method of a normal random number generation apparatus according to the first embodiment of the present invention. 100 is a seed register, 101 is an M-sequence cyclic code generator, 102 is a uniform random number generation unit, 103 is a normal random number generation unit, 104 to 115 are bit operation units, and 116 to 127 are identification bits. With the above configuration, a first embodiment of the present invention will be described with reference to FIG. The first embodiment is a normal random number generator that generates a normal random number every cycle.

  The seed register 100 will be described. The seed register 100 is a register that stores a seed to be set in the M-sequence cyclic code generator 101 described later.

  The M-sequence cyclic code generator 101 will be described. The M-sequence cyclic code generator 101 constitutes a shift register having a predetermined number of stages, and generates a pseudo-random number by feeding back a predetermined output of the shift register by a logical operation using exclusive OR. Also, assuming that the M-sequence cyclic code generator 101 is composed of N stages of shift registers, the period of the pseudorandom number generated by the M-sequence cyclic code generator 101 is 2N-1. For example, when a 28-bit M-sequence cyclic code generator is used, a 28-stage shift register is configured, and the period of the pseudo random number to be generated is 2 * 28-1. M-sequence cyclic code generator 101 generates an M-sequence cyclic code having a predetermined period.

  Next, the uniform random number generation unit 102 will be described. The uniform random number generation unit 102 includes bit operation units 104 to 115 that receive the pseudo random numbers generated by the M-sequence cyclic code generator 101, and are identification values 116 to 127 each having a fixed hardware value and different values. It has. Thereby, the inputs to the bit operation units 104 to 115 are all different. For example, as shown in FIG. 2, the identification bit 116 is input to the bit operation unit 104 as a hardware fixed value “0000”, and the identification bit 117 is input to the bit operation unit 105 as a hardware fixed value “0001”. Bit 118 is input to bit operation unit 106 as hardware fixed value “0010”, identification bit 119 is input to bit operation unit 107 as hardware fixed value “0011”, and identification bit 120 is fixed to hardware fixed value “0100”. Is input to the bit operation unit 108, the identification bit 121 is input to the bit operation unit 109 as the hardware fixed value "0101", and the identification bit 122 is input to the bit operation unit 110 as the hardware fixed value "0110". Bit 123 is input to bit operation unit 111 as hardware fixed value “0111”, identification bit 124 is input to bit operation unit 112 as hardware fixed value “1000”, and identification bit 125 is fixed to hardware fixed value “1001”. As a bit By inputting to the operation unit 113, the identification bit 126 is input to the bit operation unit 114 as the hardware fixed value “1010”, and the identification bit 127 is input to the bit operation unit 115 as the hardware fixed value “1011”. Each of the bit operation units 104 to 115 inputs a different 32-bit length value.

With the above configuration, the uniform random number generation unit 102 generates a uniform random number u _k (0 ≤ k ≤ 11) having a uniform distribution characteristic and a weak cross-correlation. Details of the bit operation units 104 to 115 will be described later.

The normal random number generation unit 103 will be described. The normal random number generation unit 103 receives the uniform random number u _k (0 ≦ k ≦ 11) generated by the uniform random number generation unit 102 as an input. A normal random number v _n having a normal distribution characteristic is output according to the central limit theorem that the sum of several independent random numbers approaches a normal distribution. For example, the normal random number v _n is generated according to the central limit theorem using the 12-bit uniform random number u _k (k = 0, 1,... 11) generated by the uniform random number generation unit 102. The normal random number v _n is calculated by the equation (1). Normal random number generation unit 103 generates a normal random number v _n with normal distribution characteristics by using a uniform random number u _k.

Therefore, v _n = -24570 to 24570 (16 bits).

  Next, the bit operation unit 104 will be described with reference to FIG. 101 is an M-sequence cyclic code generator shown in FIG. 1, 116 is an identification bit shown in FIG. 1, 300 is a bit extraction circuit, 301 is an exclusive OR operation circuit, and 302 is a bit inversion circuit.

In the above configuration, the bit operation unit 104 that generates a 12-bit uniform random number u ₀ when the bit length of the M-sequence cyclic code generator 101 is 28 bits and the identification bit 116 is 4 bits will be described. . Counting from the LSB of the identification bit 116, the fourth bit is N3, the third bit is N2, the second bit is N1, and the first bit is N0.

The bit extraction circuit 300 will be described. Since the pseudo-random number generated by the M-sequence cyclic code generator 101 has a strong autocorrelation, the bit extraction circuit 300 is configured to reduce the autocorrelation of the uniform random number u ₀ generated by the bit operation unit 104. Extract random bits arbitrarily. For example, uniform random numbers in generating u _0, and it is necessary to extract a bit S0~S13 from the pseudo-random number which the M-sequence cyclic code generator 101 generates, counted from the LSB of the uniform random number u ₀ that produces S0 to generate the first bit, S1 to generate the second bit, S2 to generate the third bit, S3 to generate the fourth bit, and S5 to generate the fifth bit S4 to generate the sixth bit, S5 to generate the sixth bit, S6 to generate the seventh bit, S7 to generate the eighth bit, S8 to generate the ninth bit, Assuming S9 to generate the 10th bit, S10 and S11 to generate the 11th bit, and S12 and S13 to generate the 12th bit, the bit operation unit 104 has the formula It is configured as (2). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 12, S12 = 22, S11 = 1, S10 = 7, S9 = 25, S8 = 2, S7 = 18, S6 = 26, S5 = 3, S4 = 14, S3 = 23, S2 = 6, S1 = 21, S0 = 10 (2)

  Although the bit operation units 105 to 115 are not illustrated, the bit extraction unit of the bit operation units 105 to 115 will be described using S0 to S13. The bit operation unit 105 is configured as shown in Expression (3). . The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 20, S12 = 5, S11 = 0, S10 = 11, S9 = 15, S8 = 4, S7 = 19, S6 = 27, S5 = 9, S4 = 17, S3 = 16, S2 = 24, S1 = 13, S0 = 8 (3)

  Further, the bit operation unit 106 is configured as shown in Expression (4). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 26, S12 = 14, S11 = 10, S10 = 2, S9 = 21, S8 = 7, S7 = 18, S6 = 20, S5 = 5, S4 = 12, S3 = 22, S2 = 6, S1 = 0, S0 = 25 (4)

  The bit operation unit 107 is configured as shown in Equation (5). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 23, S12 = 4, S11 = 3, S10 = 17, S9 = 13, S8 = 1, S7 = 19, S6 = 27, S5 = 9, S4 = 11, S3 = 16, S2 = 24, S1 = 8, S0 = 15 (5)

  Further, the bit operation unit 108 is configured as shown in Expression (6). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 27, S12 = 16, S11 = 9, S10 = 6, S9 = 21, S8 = 7, S7 = 18, S6 = 20, S5 = 5, S4 = 12, S3 = 22, S2 = 2, S1 = 13, S0 = 8 (6)

  Further, the bit operation unit 109 is configured as shown in Expression (7). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 13, S12 = 0, S11 = 8, S10 = 19, S9 = 17, S8 = 1, S7 = 26, S6 = 23, S5 = 4, S4 = 11, S3 = 14, S2 = 24, S1 = 10, S0 = 15 (7)

  Further, the bit operation unit 110 is configured as shown in Expression (8). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 21, S12 = 15, S11 = 10, S10 = 5, S9 = 19, S8 = 7, S7 = 9, S6 = 20, S5 = 6, S4 = 12, S3 = 26, S2 = 4, S1 = 27, S0 = 13 (8)

  Further, the bit operation unit 111 is configured as shown in Expression (9). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 18, S12 = 3, S11 = 1, S10 = 25, S9 = 16, S8 = 0, S7 = 22, S6 = 23, S5 = 2, S4 = 11, S3 = 14, S2 = 24, S1 = 17, S0 = 8 (9)

  Further, the bit operation unit 112 is configured as shown in Expression (10). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 22, S12 = 24, S11 = 7, S10 = 8, S9 = 19, S8 = 1, S7 = 3, S6 = 20, S5 = 6, S4 = 12, S3 = 18, S2 = 10, S1 = 27, S0 = 13 (10)

  Further, the bit operation unit 113 is configured as shown in Expression (11). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 11, S12 = 9, S11 = 2, S10 = 16, S9 = 23, S8 = 0, S7 = 26, S6 = 5, S5 = 4, S4 = 21, S3 = 14, S2 = 15, S1 = 17, S0 = 25 (11)

  Further, the bit operation unit 114 is configured as shown in Expression (12). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 25, S12 = 19, S11 = 10, S10 = 6, S9 = 22, S8 = 7, S7 = 24, S6 = 20, S5 = 8, S4 = 12, S3 = 18, S2 = 2, S1 = 27, S0 = 3 (12)

  Further, the bit operation unit 115 is configured as shown in Expression (13). The value on the right side is the bit number of the M-sequence cyclic code 101.

    S13 = 13, S12 = 4, S11 = 1, S10 = 23, S9 = 15, S8 = 0, S7 = 26, S6 = 16, S5 = 9, S4 = 21, S3 = 14, S2 = 5, S1 = 17, S0 = 11 (13)

  Next, the exclusive OR operation circuit 301 will be described. The exclusive OR operation circuit 301 performs an exclusive OR logical operation of the bits S6 to S13 extracted from the pseudo random number output from the M-sequence cyclic encoder 101 by the bit extraction circuit 300 and the identification bit 116. The configuration of the exclusive OR operation circuit 301 is, for example, a 12-bit random number output, and when the random number sequence is counted from the LSB, the first bit is P0, the second bit is P1, the third bit is P2, 4 bits Eye P3, bit 5 P4, bit 6 P5, bit 7 P6, bit 8 P7, bit 9 P8, bit 10 P9, bit 11 P10, bit 12 P11, and using the bits S0 to S13 output from the bit extraction circuit 300 and the bits N0 to N3 of the identification bit, is expressed by equation (14). A EXOR B means a logical operation of exclusive OR of A and B.

    P11 = S13 EXOR S12, P10 = S11 EXOR S10, P9 = S9 EXOR N3, P8 = S8 EXOR N2, P7 = S7 EXOR N1, P6 = S6 EXOR N0, P5 = S5, P4 = S4, P3 = S3, P2 = S2, P1 = S1, P0 = S0 (14)

  Although the exclusive OR operation circuit and the identification bits 117 to 127 of the bit operation units 105 to 115 are not shown, the configuration of the exclusive OR operation circuit of the bit operation units 105 to 115 is the bit operation unit 104. When expressed using N0 to N3, P0 to P11, and S0 to 13 used in the description of the configuration of the exclusive OR operation circuit 301, the equation (14) is obtained. A EXOR B means a logical operation of exclusive OR of A and B. However, even if the symbols of the respective bit operation units 104 to 115 are the same, the bit values for the symbols are not necessarily the same. For example, the value of the output bit P11 of the bit operation unit 104 and the value of the output bit P11 of the bit operation unit 105 are not necessarily the same.

As described above, by performing a logical operation of exclusive OR, it is possible to avoid the generation of a uniform random number u ₀ having an extreme value continuously.

  Next, the bit inverting circuit 302 will be described. The bit inversion circuit 302 inverts an arbitrary bit among the bits P0 to P11 output from the exclusive OR operation circuit 301 to generate a normal random number. For example, P9, P7, P4, P3, P0 are bit-inverted, P11 is the 12th bit, P10 is the 11th bit, P9 is the 10th bit, P8 is the 9th bit, P7 is the 8th bit, P6 is the 7th bit First, a 12-bit uniform random number is generated, with P5 as the 6th bit, P4 as the 5th bit, P3 as the 2nd bit, P2 as the 3rd bit, P1 as the 2nd bit, and P0 as the 1st bit.

  Although not shown, when the inverting circuits of the bit operation units 105 to 115 are described using the above P0 to P11, they are the same as the configuration of the bit inverting circuit 302. However, the bits to be inverted are not limited to P9, P7, P4, P3, and P0.

  Bit operation sections 105 to 115 perform bit operations on M-sequence cyclic codes based on identification bits 116 that are different from each other. Specifically, the bit operation units 105 to 115 include a bit extraction circuit 300 that extracts bits from the M-sequence cyclic code, and an exclusive OR operation circuit 301 that calculates an exclusive OR of the extracted bits and the identification bits 116. And a bit inversion circuit 302 for inverting the extracted bit or the bit of the exclusive OR.

In the first embodiment, the uniform random number generation unit 102 includes the bit operation units 104 to 115 to generate, for example, a uniform random number u _k (0 <= k <= 11) having weak cross-correlation. If the cross-correlation of the uniform random number u _k (0 ≦ k ≦ 11) output from the uniform random number generator 102 is weak, for example, the uniform random numbers u ₀ and u ₁ are generated from the bit generator 104. In addition, there is no particular problem even if the bit generation units 104 to 115 generate a plurality of uniform random numbers u _k (0 ≤ k ≤ 11). Further, if the cross-correlation of the uniform random number u _k (0 ≦ k ≦ 11) generated by the uniform random number generation unit 102 is weak, whether or not the configuration of each of the bit operation units 104 to 115 is the same There is no particular problem. For example, when the bit operation units 104 to 115 perform hash operations, if the input of the bit operation units 104 to 115 is different, the output of the uniform random number u _k (0 ≤ k ≤ 11) Since the cross-correlation is weak, there is no particular problem even if the bit operation units 104 to 115 have the same configuration.

  In addition, since the uniform random number generation unit 102 requires different identification bits 116 to 127 for the bit operation units 104 to 115, the bit length of the identification bits 116 to 127 is 4 bits. Needless to say, the bit length of the identification bit is not particularly problematic as long as the identification bit can represent different values for each bit operation unit. Further, although the identification bits 116 to 127 have been described as hardware fixed values, there is no particular problem even if they are storage media such as registers.

  In addition, the configurations of the inverting circuits of the bit operation units 104 to 115 are all the same, but need not be the same.

(Second Embodiment)
FIG. 4 shows an outline of the uniform random number generation method of the normal random number generation apparatus according to the second embodiment of the present invention. 100 is a seed register shown in FIG. 1, 101 is an M-sequence cyclic code generator shown in FIG. 1, 104 to 109 are bit operation units shown in FIG. 1, 500 is a uniform random number generator, 501 to 506 are identification bits, 507 Is a normal random number generator, and 508 is a counter. With the above configuration, a second embodiment of the present invention will be described with reference to FIG.

Since the seed register 100, the M-sequence cyclic code generator 101, and the bit operation units 104 to 109 have the same configuration as that of the first embodiment, description thereof is omitted. A normal random number generator that generates a normal random number v _n once in several cycles, for example, a uniform random number u _k (0 ≤ k ≤ 11) is required to generate a normal random number v _n , and 1 in 2 cycles The normal random number generation device that generates the round normal random number v _n can reduce the circuit scale by the uniform random number generation unit 500 described later.

The uniform random number generation unit 500 will be described. The uniform random number generation unit 500 includes bit operation units 104 to 109 and identification bits 501 to 506 to be described later, generates a uniform random number u _k (0 ≤ k ≤ 5) in the first cycle, and in the next cycle. Generate uniform random number u _k (6 <= k <= 11).

  Next, the identification bits 501 to 506 will be described. Each of the identification bits 501 to 506 has a bit length of 3 bits and has the same configuration as that of the first embodiment.

Next, the normal random number generation unit 507 will be described. The normal random number generator 507 receives the uniform random number u _k (0 ≤ k ≤ 11) generated by the uniform random number generator and holds the uniform random number u _k (0 ≤ k ≤ 11). To do. The counter 508 is a 1-bit counter, and the normal random number generation unit 507 generates the normal random number v _n when the counter 508 is “1”, that is, once every two cycles.

The second embodiment requires a uniform random number _{u k (0 <= k <} = 11) for generating a normal random number v _n, has been described to generate a once normal random number v _n 2 cycles If the uniform random number output from the uniform random number generation unit is held by the normal random number generation unit and the timing for generating the normal random number from the normal random number generation unit is controlled by the counter, the configuration is not limited to the above. . For example, uniform random numbers u _k to generate a normal random number _{v n (0 <= k <} = 11) is required, normal random number generator for generating a normal random number v _n only once in six cycles, uniform random number This can be realized by providing the generation unit with two bit operation units, two 1-bit identification bits having different values, and a counter representing 0 to 5.

  In this embodiment, the bit length of the seed register 100 and the M-sequence cyclic code generator 101 is 28 bits, and the uniform random number generator 102 generates 12 12-bit uniform random numbers. Needless to say, the length and number are not limited.

  As described above, according to the normal random number generators of the first and second embodiments, since the seed register and the M-sequence cyclic code generator 101 have only one set, seed setting to be given to the M-sequence cyclic code Thus, it is possible to provide a normal random number generation device that does not increase the amount of circuit hardware, and avoids that an extreme value is continuously generated and autocorrelation is strengthened. In addition, when the output is not required every cycle, the circuit scale of the generation apparatus of the present embodiment can be reduced by using a counter.

  Thereby, in image processing, image quality deterioration due to autocorrelation of normal random numbers can be prevented, and high quality image quality can be obtained. FIG. 5 is a diagram showing the autocorrelation near the normal random number generated by the normal random number generation apparatus according to the present embodiment. FIG. 6 is a graph showing the autocorrelation around the period of a 28-bit M-sequence of normal random numbers generated by the normal random number generation apparatus according to the present embodiment. FIG. 7 is a frequency distribution table of normal random numbers generated by the normal random number generation apparatus according to the present embodiment. The standard deviation is 127/3. It can be proved that the present invention is a normal random number generation device that has a weaker correlation than FIGS. 5 to 7 and can generate normal random numbers having normal distribution characteristics.

(Third embodiment)
In color copiers and color printers, image signals input from original image reading devices such as color image scanners and computers are converted to Log conversion, CMYK color space conversion, and printer engine characteristics. After the gamma conversion is performed, pseudo intermediate processing such as error diffusion processing is performed. Normally, in the pseudo-intermediate process, random number addition processing is performed in which a uniform random number value or a normal random number value is intentionally added as small noise in order to make moire due to quantization noise less noticeable.

  The pseudo intermediate processing is configured by hardware, and when one pixel processing is performed per system clock, the random number addition processing is performed once every two pixels, so generation of normal random numbers is performed once every two system clocks. There is a need to do. A simple method of generating normal random numbers using normal hardware is to extract a single random number per system clock with a bit length that does not correlate normal random numbers within the desired number of pixels. A plurality of M-sequence cyclic code generators that can be used are prepared, and normal random values are generated by adding a plurality of uniform random numbers extracted according to the central limit theorem. Here, the reason why uniform random numbers are extracted from a plurality of M-sequence cyclic code generators is to eliminate correlation between uniform random numbers. At this time, each M-sequence cyclic code generator has a configuration based on the same primitive polynomial, and a different seed value is given to each M-sequence cyclic code generator to correlate between the extracted uniform random numbers. Is lost.

  For example, in order to generate a normal random number so that no correlation occurs for the number of pixels of A3 1200 DPI, an M-sequence cyclic code generator having a 28-bit length is required even if a normal random number is generated every other pixel. If the number of uniform random numbers added to the central limit theorem is 12, and two 12-bit uniform random numbers are extracted from the 28-bit long M-sequence cyclic code generator, the 28-bit long M-sequence cyclic code generator 6 are required.

  However, if the same primitive polynomial is prepared for all of the above cyclic codes and the same seed value is given, the M-sequence data is shifted by only 1 bit in one clock, so the normal random number generated from the uniform random number generated in this way Autocorrelation has a drawback that it appears strongly. In order to eliminate the above drawbacks, it is conceivable to give different seed values to each M-sequence cyclic code, but it is necessary to set different seed values from a CPU or the like for a plurality of M-sequence cyclic code generators. The register for storing the set value is required to be equivalent to the bit length of the cyclic code generator, resulting in an increase in hardware scale.

  For example, in the case of using six 28-bit length M-sequence cyclic code generators, a 28 × 6 = 168-bit length register is required as a seed value setting register.

  FIG. 9 schematically shows a random number generator according to the third embodiment of the present invention. 11 is a register unit that stores settings from the CPU, 12 is a control unit that controls the operation sequence of other blocks, 13 is a uniform random number generator that generates uniform random numbers, and 14 is the uniform random number generator 13 The normal random number generator 15 generates a normal random number, and 15 is a scaling unit that scales the normal random number generated by the normal random number generator 14. In the above configuration, a third embodiment of the present invention will be described with reference to FIG.

  The register unit 11 stores setting values from the CPU and the like and supplies them to other blocks. The control unit 12 performs operation sequence control of other blocks. The uniform random number generator 13 includes six 28-bit long M-sequence cyclic code generators, and extracts and outputs 12 12-bit uniform random numbers. Here, the bit length of the uniform random number is 12 bits in consideration of the operation error in the scaling unit 15 described later because the bit length of the output value in the scaling unit 15 described later needs to be 10 bits or more. It is said. The normal random number generation unit 14 adds the 12 uniform random numbers from the uniform random number generation unit 13 and outputs a normal random number according to the central limit theorem.

In this method, if Xi (i = 0,1, ... 11) is a uniform random number on the interval (0,1), the sum of these random numbers (X ₀ + X ₂ + ... + X ₁₁ ) Is well approximated to a normal distribution with an average value of 0 and a variance of 1. Here, if the output uniform random number is u _k (k = 1 to 12), the normal random number x is calculated by the equation (15).

  Therefore, x = -24570 to 24570 (16 bits).

  The scaling unit 15 performs scaling on the 16-bit normal random number output from the normal random number generation unit 14, and generates a 10-bit random number addition value. FIG. 10 shows an example of scaling. By scaling the value of 3σ to 255, the maximum value of 6σ of normal random numbers is scaled to 510. Therefore, a 10-bit random number addition value including the sign bit is generated.

  The above random number addition value of the output value of the scaling unit 15 is added to a 10-bit output density value Din (an integer value of 0 to 1023) of the preceding stage gamma conversion process (not shown). Thereafter, it is output to a subsequent clipping process and error diffusion process (not shown).

  Next, the details of the uniform random number generator 13 will be described with reference to FIG. 31 is a seed register that stores a common 28-bit seed value (initial value), 32 is a 28-bit M-sequence cyclic code generator that generates an M-sequence cyclic code, and 33 is a 28-bit length that differs from 32 in the primitive polynomial. M-sequence cyclic code generator, 34 is a 28-bit length M-sequence cyclic code generator with a different primitive polynomial of 32, 33, and 35 is a 28-bit length M-sequence cyclic code generator with a different primitive polynomial of 32, 33, 34 , 36 is an M-sequence cyclic code generator with a 28-bit length different from 32, 33, 34, 35 and a primitive polynomial, 37 is an M-sequence cyclic code with a 28-bit length different from 32, 33, 34, 35, and 36 Generator.

  In this embodiment, the M-sequence cyclic code generator 13 includes six 28-bit length M-sequence cyclic code generators. Each of the 28-bit length M-sequence cyclic code generators has a different primitive polynomial. For example, assuming that each of the six 28-bit long M-sequence cyclic code generators is Ma, Mb... Mf, Ma, Mb... Mf has a primitive polynomial expressed by Equation (16). Correlation between uniform random numbers can be suppressed by preventing the orders of the primitive polynomial combinations from overlapping as much as possible.

Ma: h (X) = X ²⁸ + X ³
Mb: h (X) = X ²⁸ + X ⁶ + X ⁴ + X ¹
Mc: h (X) = X ²⁸ + X ⁷ + X ⁶ + X ⁵
Md: h (X) = X ²⁸ + X ⁹ + X ⁸ + X ⁵
Me: h (X) = X ²⁸ + X ¹⁰ + X ³ + X ¹
Mf: h (X) = X ²⁸ + X ¹¹ + X ⁷ + X ³ (16)

  Here, Ma, Mb, Mc, Md, Me, and Mf are 28-bit long M-sequence cyclic code generators, and h (X) is a primitive polynomial. The seed register 31 for storing the seed value is extracted from the register unit 11 and clearly shown.

The M-sequence cyclic code generator 32 is a 28-bit M-sequence cyclic code generator, and operates using the seed value stored in the seed register 31 as an initial value. The 28-bit long M-sequence cyclic code generator 32 outputs 12-bit uniform random numbers u ₀ [11: 0] and u ₁ [11: 0]. Here, uniform random numbers u ₀ [11: 0] and u ₁ [11: 0] are output by extracting bits from the 28-bit long M-sequence cyclic code generator 32 as follows.

u ₀ [11: 0] = [22,7,11,2,18,1,3,13,23,9,21,10] (17)
u ₁ [11: 0] = [5,20,8,16,19,0,12,17,4,6,13,15] (18)

The number on the right side of Equation (17) is the bit number of the 28-bit long M-sequence cyclic code generator 32, and a uniform random number is generated by extracting desired bits. In addition, bits are extracted from discontinuous bit positions so as not to be continuous bit positions in order to improve characteristics as a random number. The same applies to u ₁ [11: 0] represented by formula (18). Here, u ₀ [11: 0] and u ₁ [11: 0] are arranged so that the bit positions extracted from the 28-bit long M-sequence cyclic code generator do not overlap with each other in order to eliminate the correlation.

The M-sequence cyclic code generator 33 is a 28-bit M-sequence cyclic code generator, and operates using the seed value stored in the seed register 31 as an initial value. The 28-bit long M-sequence cyclic code generator 33 outputs 12-bit uniform random numbers u ₂ [11: 0] and u ₃ [11: 0]. Here, uniform random numbers u ₂ [11: 0] and u ₃ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 28-bit M-sequence cyclic code. It is output by extracting the bits from the unit 33 as follows.

u ₂ [11: 0] = [7,11,2,18,1,3,13,23,9,21,10,22] (19)
u ₃ [11: 0] = [20,8,16,19,0,12,17,4,6,13,15,5] (20)

The expressions (19) and (20) are the same as those in expression (17) and the like. However, regarding the bit position extracted from the 28-bit length M-sequence cyclic code generator 33, u ₂ [11: 0] is shifted by 1 bit to the MSB side with respect to u ₀ [11: 0], and u ₀ [11: 0] is assigned MSB bit number '22' to LSB. Similarly u ₃ [11: 0] is u ₁ has allocated: [0 11] bit number '5' was MSB in the LSB [11 0] shifted one bit to the MSB side with respect to, u ₁ . Thus, by changing the extraction position from the M-sequence cyclic code generator between the uniform random numbers, the correlation between the uniform random numbers due to the dependency of the extraction position is reduced.

The M-sequence cyclic code generator 34 is a 28-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 31 as an initial value. The 28-bit long M-sequence cyclic code generator 34 outputs 12-bit uniform random numbers u ₄ [11: 0] and u ₅ [11: 0]. Here, uniform random numbers u ₄ [11: 0] and u ₅ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 28-bit M-sequence cyclic code. It is output by extracting the bits from the unit 34 as follows.

u ₄ [11: 0] = [11,2,18,1,3,13,23,9,21,10,22,7] (21)
u ₅ [11: 0] = [8,16,19,0,12,17,4,6,13,15,5,20] (22)

The expressions (21) and (22) are the same as those in expression (17) and the like. However, regarding the bit position extracted from the 28-bit length M-sequence cyclic code generator 34, u ₄ [11: 0] is shifted by 1 bit to the MSB side with respect to u ₂ [11: 0], and u ₂ [11: 0] is assigned MSB bit number '7' to LSB. Similarly u ₅ [11: 0] is u ₃ are assigned: [0 11] bit numbers '20' was the MSB in the LSB [11 0] shifted one bit to the MSB side with respect to, u ₃ .

The M-sequence cyclic code generator 35 is a 28-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 31 as an initial value. The 28-bit long M-sequence cyclic code generator 35 outputs 12-bit uniform random numbers u ₆ [11: 0] and u ₇ [11: 0]. Here, uniform random numbers u ₆ [11: 0] and u ₇ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 28-bit long M-sequence cyclic code. It is output by extracting bits from the device 35 as follows.

u ₆ [11: 0] = [2,18,1,3,14,23,9,21,10,22,7,11] (23)
u ₇ [11: 0] = [16,19,0,12,17,4,6,13,15,5,20,8] (24)

The expressions (23) and (24) are the same as those in expression (17) and the like. However, regarding the bit position extracted from the 28-bit length M-sequence cyclic code generator 35, u ₆ [11: 0] is shifted by 1 bit to the MSB side with respect to u ₄ [11: 0], and u ₄ [11: 0] is assigned MSB bit number '11' to LSB. Similarly u ₇ [11: 0] are u ₅ are assigned the:: [0 11] bit number '8' was MSB in the LSB [11 0] shifted one bit to the MSB side with respect to, u ₅ .

The M-sequence cyclic code generator 36 is an M-sequence cyclic code generator having a 28-bit length, and operates using the seed value stored in the seed register 31 as an initial value. The 28-bit long M-sequence cyclic code generator 36 outputs 12-bit uniform random numbers u ₈ [11: 0] and u ₉ [11: 0]. Here, uniform random numbers u ₈ [11: 0] and u ₉ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 28-bit M-sequence cyclic code. It is output by extracting the bits from the unit 36 as follows.

u ₈ [11: 0] = [18,1,3,13,23,9,21,10,22,7,11,2] (25)
u ₉ [11: 0] = [19,0,12,17,4,6,13,15,5,20,8,16] (26)

The expressions (25) and (26) are the same as those in expression (17) and the like. However, regarding the bit position extracted from the 28-bit length M-sequence cyclic code generator 36, u ₈ [11: 0] is shifted by 1 bit to the MSB side with respect to u ₆ [11: 0], and u ₆ [11: 0] is assigned MSB bit number '2' to LSB. Similarly u ₉ [11: 0] is u ₇ are assigned: [0 11] bit numbers '16' was the MSB in the LSB [11 0] shifted one bit to the MSB side with respect to, u ₇ .

The M-sequence cyclic code generator 37 is a 28-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 31 as an initial value. The 28-bit long M-sequence cyclic code generator 37 outputs 12-bit uniform random numbers u ₁₀ [11: 0] and u ₁₁ [11: 0]. Here, uniform random numbers u ₁₀ [11: 0] and u ₁₁ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 28-bit long M-sequence cyclic code. It is output by extracting bits from the device 37 as follows.

u ₁₀ [11: 0] = [1,3,14,23,9,21,10,22,7,11,2,18] (27)
u ₁₁ [11: 0] = [0,12,17,4,6,13,15,5,20,8,16,19] (28)

The expressions (27) and (28) are the same as those in expression (17) and the like. However, regarding the bit position extracted from the 28-bit length M-sequence cyclic code generator 37, u ₁₀ [11: 0] is shifted by 1 bit to the MSB side with respect to u ₈ [11: 0], and u ₈ [11: 0] is assigned MSB bit number '18' to LSB. Similarly u ₁₁ [11: 0] are u ₉ are assigned: [0 11] bit numbers '19' was the MSB in the LSB [11 0] shifted one bit to the MSB side with respect to, u ₉ .

  According to the present embodiment, by using the uniform random number generating means, it is possible to generate random numbers having good normal distribution characteristics even if only one seed value is used. In addition, since the registers for storing the seed value can be reduced, the hardware scale can be reduced.

(Fourth embodiment)
Next, details of the uniform random number generation unit 13 in the fourth embodiment of the present invention will be described with reference to FIG. 401 is a seed register that stores a 17-bit seed value, 402 is a seed register that stores an 11-bit seed value, 403 is a 17-bit M-sequence cyclic code generator that generates an M-sequence cyclic code, and 404 is an M-sequence cyclic code 11-bit length M-sequence cyclic code generator, 405 is a 17-bit length M-sequence cyclic code generator with a primitive polynomial different from 403, 406 is an 11-bit length M-sequence cyclic code generator with a different primitive polynomial 407 is an M-sequence cyclic code generator of 403,405 with a different primitive polynomial and 17-bit length, 408 is 404,406 and an 11-bit length of an M-sequence cyclic code generator with a different primitive polynomial, 409 is 403,405,407 and 17 bits with a different primitive polynomial It is a long M-sequence cyclic code generator. 410 is an M-sequence cyclic code generator with a different primitive polynomial of 404,406,408 and 11-bit length, 411 is an M-sequence cyclic code generator of 403,405,407,409 and a different primitive polynomial of 17-bit length, 412 is an 11-bit length different from 404,406,408,410 and a primitive polynomial An M-sequence cyclic code generator 413 is a 17-bit length M-sequence cyclic code generator having different primitive polynomials such as 403, 405, 407, 409, 411, and 414 is an 11-bit length M-sequence cyclic code generator having 404, 406, 408, 410, 412 and different primitive polynomials.

  In the third embodiment, only one 28-bit M-sequence cyclic code is used in the M-sequence cyclic code generator 31, but in the fourth embodiment, the M-sequence cyclic code generator 31 uses a 17-bit length. 6 M-sequence cyclic code generators and 6 11-bit M-sequence cyclic code generators. The 17-bit M-sequence cyclic code generator and the 11-bit M-sequence cyclic code generator have different primitive polynomials. For example, assuming that each of the six 17-bit long M-sequence cyclic code generators is M1a, M1b... M1f, M1a, M1b... M1f includes a primitive polynomial expressed by Equation (29). Further, assuming that each of the six 11-bit long M-sequence cyclic code generators is M2a, M2b... M2f, M2a, M2b... M2f includes a primitive polynomial expressed by Equation (30). The 17-bit M-sequence cyclic code generator and the 11-bit M-sequence cyclic code generator generate M-sequence cyclic codes having different periods.

Primitive polynomial for 17-bit M-sequence cyclic polynomial
M1a: h (X) = X ¹⁷ + X
M1b: h (X) = X ¹⁷ + X ⁵ + X ³ + X ²
M1c: h (X) = X ¹⁷ + X ⁶ + X ⁴ + X ²
M1d: h (X) = X ¹⁷ + X ⁷ + X ⁵ + X
M1e: h (X) = X ¹⁷ + X ⁸ + X ³ + X
M1f: h (X) = X ¹⁷ + X ⁹ + X ⁵ + X ⁴ (29)

Primitive polynomial for 11-bit M-sequence cyclic polynomial
M2a: h (X) = X ¹¹ + X ²
M2b: h (X) = X ¹¹ + X ⁴ + X ² + X
M2c: h (X) = X ¹¹ + X ⁵ + X ³ + X
M2d: h (X) = X ¹¹ + X ⁶ + X ² + X
M2e: h (X) = X ¹¹ + X ⁷ + X ⁵ + X ³
M2f: h (X) = X ¹¹ + X ⁸ + X ³ + X ² (30)

  Here, M1a, M1b, M1c, M1d, M1e, M1f are 17-bit long M-sequence cyclic code generators, M2a, M2b, M2c, M2d, M2e, M2f are 17-bit long M-sequence cyclic code generators, and h (X) is It is a primitive polynomial. Further, the seed register 401 and the seed register 402 for storing the seed value are extracted from the register unit 11 and clearly shown.

The M-sequence cyclic code generator 403 is a 17-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 401 as an initial value. The M-sequence cyclic code generator 404 is an 11-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 402 as an initial value. The 17-bit long M-sequence cyclic code generator 403 and the 11-bit long M-sequence cyclic code generator 404 output 12-bit uniform random numbers u ₀ [11: 0] and u ₁ [11: 0]. Here, the uniform random numbers u ₀ [11: 0] and u ₁ [11: 0] are transmitted from the 17-bit length M-sequence cyclic code generator 403 and the 11-bit length M-sequence cyclic code generator 404 as follows. Output by extracting.

u ₀ [11: 0] = [11,7 ', 0,2', 7,1 ', 3', 3,12,9 ', 10,10'] (31)
u ₁ [11: 0] = [5 ', 9,8', 5,8,0 ', 1,6,4', 6 ', 2,4] (32)

As for the number on the right side of Expression (31), the number without “′” is the bit number of the 17-bit length M-sequence cyclic code generator 403, and the number with “′” is the 11-bit length M-sequence cyclic code generator 404. A uniform random number is generated by extracting a desired bit. In addition, bits are extracted from discontinuous bit positions so as not to be continuous bit positions in order to improve characteristics as a random number. The same applies to u ₁ [11: 0] represented by formula (32). Here, u ₀ [11: 0] and u ₁ [11: 0] are arranged so that the bit positions extracted from the 28-bit long M-sequence cyclic code generator do not overlap with each other in order to eliminate the correlation.

The M-sequence cyclic code generator 405 is a 17-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 401 as an initial value. The M-sequence cyclic code generator 406 is an 11-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 402 as an initial value. The 17-bit long M-sequence cyclic code generator 405 and the 11-bit long M-sequence cyclic code generator 406 output 12-bit uniform random numbers u ₂ [11: 0] and u ₃ [11: 0]. Here, uniform random numbers u ₂ [11: 0] and u ₃ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 17-bit long M-sequence cyclic code. The bit is extracted from the generator 405 and the 11-bit long M-sequence cyclic code generator 406 as follows.

u ₂ [11: 0] = [7 ', 0,2', 7,1 ', 3', 3,12,9 ', 10,10', 11] (33)
u ₃ [11: 0] = [9,8 ', 5,8,0', 1,6,4 ', 6', 2,4,5 '] (34)

The expressions of Expression (33) and Expression (34) are the same as Expression (31) and the like. However, regarding the bit positions extracted from the 17-bit length M-sequence cyclic code generator 405 and the 11-bit length M-sequence cyclic code generator 406, u ₂ [11: 0] is MSB side with respect to u ₀ [11: 0]. The bit number “11” that was MSB in u ₀ [11: 0] is assigned to the LSB. Similarly u ₃ [11: 0] is u ₁ [11: 0] by one bit shifted to the MSB side of the, u ₁ [11: 0] bit number "5 '" was MSB by assigning the LSB Yes. Thus, by changing the extraction position from the M-sequence cyclic code generator between the uniform random numbers, the correlation between the uniform random numbers due to the dependency of the extraction position is reduced.

The M-sequence cyclic code generator 407 is a 17-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 401 as an initial value. The M-sequence cyclic code generator 408 is an 11-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 402 as an initial value. The 17-bit long M-sequence cyclic code generator 407 and the 11-bit long M-sequence cyclic code generator 408 output 12-bit uniform random numbers u ₄ [11: 0] and u ₅ [11: 0]. Here, uniform random numbers u ₄ [11: 0] and u ₅ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 17-bit M-sequence cyclic code. 407 and the 11-bit long M-sequence cyclic code generator 408 output the bits as follows.

u ₄ [11: 0] = [0,2 ', 7,1', 3 ', 3,12,9', 10,10 ', 11,7'] (35)
u ₅ [11: 0] = [8 ', 5,8,0', 1,6,4 ', 6', 2,4,5 ', 9] (36)

The expressions (35) and (36) are the same as those in expression (31) and the like. However, regarding the bit positions extracted from the 17-bit length M-sequence cyclic code generator 407 and the 11-bit length M-sequence cyclic code generator 408, u ₄ [11: 0] is MSB side with respect to u ₂ [11: 0]. The bit number “7 ′” that was the MSB in u ₂ [11: 0] is assigned to the LSB. Similarly u ₅ [11: 0] is u ₃ are assigned: [0 11] the bit number "9" was MSB in the LSB [11 0] shifted one bit to the MSB side with respect to, u ₃ . Thus, by changing the extraction position from the M-sequence cyclic code generator between the uniform random numbers, the correlation between the uniform random numbers due to the dependency of the extraction position is reduced.

The M-sequence cyclic code generator 409 is a 17-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 401 as an initial value. The M-sequence cyclic code generator 410 is an 11-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 402 as an initial value. The 17-bit long M-sequence cyclic code generator 409 and the 11-bit long M-sequence cyclic code generator 410 output 12-bit uniform random numbers u ₆ [11: 0] and u ₇ [11: 0]. Here, uniform random numbers u ₆ [11: 0] and u ₇ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating 17-bit long M-sequence cyclic codes. 409 and 11-bit length M-sequence cyclic code generator 410 to output the bits as follows.

u ₆ [11: 0] = [7,1 ', 3', 3,12,9 ', 10,10', 11,7 ', 0,2'] (37)
u ₇ [11: 0] = [5,8,0 ', 1,6,4', 6 ', 2,4,5', 9,8 '] (38)

The expressions of Expression (37) and Expression (38) are the same as Expression (31) and the like. However, regarding the bit positions extracted from the 17-bit length M-sequence cyclic code generator 409 and the 11-bit length M-sequence cyclic code generator 410, u ₆ [11: 0] is MSB side with respect to u ₄ [11: 0]. The bit number “2 ′” that was the MSB in u ₄ [11: 0] is assigned to the LSB. Similarly u ₇ [11: 0] are u ₅ [11: 0] by one bit shifted to the MSB side with respect to, u ₅ [11: 0] bit number "8 '" was MSB by assigning the LSB Yes. Thus, by changing the extraction position from the M-sequence cyclic code generator between the uniform random numbers, the correlation between the uniform random numbers due to the dependency of the extraction position is reduced.

The M-sequence cyclic code generator 411 is a 17-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 401 as an initial value. The M-sequence cyclic code generator 412 is an 11-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 402 as an initial value. The 17-bit long M-sequence cyclic code generator 411 and the 11-bit long M-sequence cyclic code generator 412 output 12-bit uniform random numbers u ₈ [11: 0] and u ₉ [11: 0]. Here, uniform random numbers u ₈ [11: 0] and u ₉ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 17-bit M-sequence cyclic code. The bit is extracted from the 411 and the 11-bit long M-sequence cyclic code generator 412 as follows.

u ₈ [11: 0] = [1 ', 3', 3,12,9 ', 10,10', 11,7 ', 0,2', 7] (39)
u ₉ [11: 0] = [8,0 ', 1,6,4', 6 ', 2,4,5', 9,8 ', 5] (40)

The expressions (39) and (40) are the same as expressions (31) and the like. However, regarding the bit positions extracted from the 17-bit long M-sequence cyclic code generator 411 and the 11-bit long M-sequence cyclic code generator 412, u ₈ [11: 0] is MSB side with respect to u ₆ [11: 0]. The bit number “7” that was MSB in u ₆ [11: 0] is assigned to the LSB. Similarly u ₉ [11: 0] is u ₇ are assigned: [0 11] the bit number "5" was a MSB in the LSB [11 0] shifted one bit to the MSB side with respect to, u ₇ . Thus, by changing the extraction position from the M-sequence cyclic code generator between the uniform random numbers, the correlation between the uniform random numbers due to the dependency of the extraction position is reduced.

The M-sequence cyclic code generator 413 is a 17-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 401 as an initial value. The M-sequence cyclic code generator 414 is an 11-bit long M-sequence cyclic code generator, and operates using the seed value stored in the seed register 402 as an initial value. The 17-bit long M-sequence cyclic code generator 413 and the 11-bit long M-sequence cyclic code generator 414 output 12-bit uniform random numbers u ₁₀ [11: 0] and u ₁₁ [11: 0]. Here, uniform random numbers u ₁₀ [11: 0] and u ₁₁ [11: 0] are generated in the same manner as u ₀ [11: 0] and u ₁ [11: 0] by generating a 17-bit M-sequence cyclic code. 413 and 11 bit length M-sequence cyclic code generator 414 extract the bits as follows.

u ₁₀ [11: 0] = [3 ', 3,12,9', 10,10 ', 11,7', 0,2 ', 7,1'] (41)
u ₁₁ [11: 0] = [0 ', 1,6,4', 6 ', 2,4,5', 9,8 ', 5,8] (42)

The expressions (41) and (42) are the same as expressions (31) and the like. However, regarding the bit positions extracted from the 17-bit length M-sequence cyclic code generator 413 and the 11-bit length M-sequence cyclic code generator 414, u ₁₀ [11: 0] is MSB side with respect to u ₈ [11: 0]. The bit number “1 ′” that was the MSB in u ₈ [11: 0] is assigned to the LSB. Similarly u ₁₁ [11: 0] are u ₉ are assigned: [0 11] bit number "8" were MSB in the LSB [11 0] shifted one bit to the MSB side with respect to, u ₉ . Thus, by changing the extraction position from the M-sequence cyclic code generator between the uniform random numbers, the correlation between the uniform random numbers due to the dependency of the extraction position is reduced.

  When generating one uniform random number from a plurality of M-sequence cyclic codes described in FIG. 12, not only the cross-correlation between the generated uniform random numbers but also the cross-correlation between M-sequence cyclic codes does not appear strongly. It is necessary to determine the seed value, but by giving a good seed value, the 11-bit M-sequence cyclic code and the 17-bit M-sequence cyclic are used, compared to the case where only one 28-bit M-sequence cyclic code is used. When one code is used, random numbers having good normal distribution characteristics can be generated.

  In addition, the said embodiment showed an example of this invention, and it cannot be overemphasized that this invention should not be limited to this.

  For example, an M-sequence cyclic code generator having a primitive polynomial with a combination represented by Equation (16) or Equation (29) and Equation (30) is used. If there is, there is no particular limitation.

  In addition, in order to generate uniform random numbers, bits were extracted from the above-mentioned bit positions of the 28-bit long M-sequence cyclic code generator. However, in order to improve the characteristics as random numbers, it is necessary to avoid consecutive bit positions. There is no particular limitation as long as it is extracted from consecutive bit positions.

  In the fourth embodiment, 11-bit and 17-bit M-type cyclic encoders are used. However, there is no particular limitation as long as the total bit length of this combination is 28 bits or more.

  As described above, according to the third and fourth embodiments, when generating a normal random number using the central limit theorem, a normal random number generator having a good normal distribution characteristic with a small hardware scale is provided. can do. In addition, since it is not necessary to set seed values for all M-sequence cyclic polynomials, it is easy to determine a seed value for generating random numbers having good normal distribution characteristics.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a figure explaining the normal random number generation method of the 1st Embodiment of this invention. It is a figure explaining the bit setting of the identification bit of 1st Embodiment. It is a figure explaining the bit operation part of 1st Embodiment. It is a figure explaining the normal random number generation method of the 2nd Embodiment of this invention. It is the graph which showed the correlation of the vicinity of the normal random number output by the normal random number generator of this embodiment. It is the graph which showed the correlation around the period of the 28-bit M series of the normal random number output by the normal random number generation apparatus of this embodiment. It is a frequency density graph of the normal random number output by the normal random number generation device of this embodiment. It is a figure explaining the normal random number generation method using a prior art. It is a figure explaining the 3rd Embodiment of this invention. It is a figure explaining the scaling of this embodiment. It is a figure explaining the structure of the uniform random number generation part using the 28bitM series cyclic code generator of this embodiment. It is a figure explaining the structure of the uniform random number generation part using the 17bitM sequence cyclic code generator and 11bitM sequence cyclic code generator of the 4th Embodiment of this invention.

Explanation of symbols

100 seed register,
101 M-sequence cyclic code generator,
102 uniform random number generator,
103 normal random number generator,
104-115 bit operation section,
116-127 identification bits,
300-bit extraction circuit,
301 exclusive OR circuit,
302 bit inversion circuit,
500 uniform random number generator,
501 to 506 identification bits,
507 normal random number generator,
508 counter,
1000-1011 seed register,
1012-1023 M-sequence cyclic code generator,
1024 uniform random number generator,
1025 normal random number generator,
1026 to 1037 Bit operation unit

Claims (12)

M-sequence cyclic code generation means for generating an M-sequence cyclic code having a predetermined period;
Uniform random number generating means for generating a plurality of uniform random numbers each having uniform distribution characteristics based on the M-sequence cyclic code;
A random number generation device comprising normal random number generation means for generating normal random numbers having normal distribution characteristics using the plurality of uniform random numbers.   2. The random number generation device according to claim 1, wherein the uniform random number generation means includes a plurality of bit operation means for performing bit operations on the M-sequence cyclic code based on different identification bits.   The bit manipulation means includes bit extraction means for extracting bits from the M-sequence cyclic code, logic operation means for obtaining an exclusive OR of the extracted bits and the identification bits, and the extracted bits or the exclusive logic 3. The random number generation device according to claim 2, further comprising bit inversion means for inverting the sum bit.   The random number generation device according to claim 2, wherein the bit operation means performs a hash operation.   The uniform random number generation means generates a plurality of sets of uniform random numbers in a plurality of cycles, and the normal random number generation means generates a normal random number using the plurality of sets of uniform random numbers. The random number generation device according to any one of 4. Uniform random number generating means for generating an M-sequence cyclic code and generating a plurality of uniform random numbers having uniform distribution characteristics based on the M-sequence cyclic code;
A random number generation device comprising normal random number generation means for adding the plurality of uniform random numbers to generate a normal random number having a normal distribution characteristic.   7. The uniform random number generating means includes a plurality of M-sequence cyclic code generating means for generating M-sequence cyclic codes of primitive polynomials having different predetermined periods based on a common initial value. Random number generator.   The random number generation device according to claim 6 or 7, wherein the uniform random number generation unit generates a plurality of uniform random numbers by extracting predetermined bits of the M-sequence cyclic code.   The random number generation device according to claim 6, further comprising scaling means for scaling the normal random number.   10. The uniform random number generation means generates an M-sequence cyclic code having a different period and generates a plurality of uniform random numbers based on the M-sequence cyclic code. The random number generator according to item. An M-sequence cyclic code generating step for generating an M-sequence cyclic code having a predetermined period;
A uniform random number generating step for generating a plurality of uniform random numbers each having a uniform distribution characteristic based on the M-sequence cyclic code;
And a normal random number generation step of generating a normal random number having a normal distribution characteristic using the plurality of uniform random numbers. A uniform random number generating step for generating an M-sequence cyclic code and generating a plurality of uniform random numbers having uniform distribution characteristics based on the M-sequence cyclic code;
And a normal random number generating step of generating a normal random number having a normal distribution characteristic by adding the plurality of uniform random numbers.

Images