JP2006287420A - Clock data recovery circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock data recovery circuit the stability of which is enhanced without the need for externally receiving a high speed reference clock. <P>SOLUTION: In the clock data recovery circuit, a phase comparison section 20 compares a phase of a trailing edge of input data DataIn with each phase of leading edges of output data D1, D2, D3, D4, D5 of each of 1-bit delay elements 11 arranged in a delay section 10, a charge pump filter 30 adjusts a delay amount of each of half-bit delay elements arranged to the delay section 10 on the basis of a result of the comparison, a clock generating section 40 generates a clock RCK with a period synchronously with an input period of the input data DataIn on the basis of output data D0h, D1h, D2h, D3h, D4h of the half-bit delay elements whose delay amount is adjusted, and a flip-flop 50 uses the clock RCK to capture the input data DataIn. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generates a clock synchronized with input data that may remain at an arbitrary number of bits H level or L level within a predetermined maximum number of bits, and uses the clock to recover the input data. Regarding the circuit.

  Conventionally, a clock and data recovery circuit using a PLL (Phase Locked Loop) technique (see, for example, Non-Patent Document 1) and a clock and data recovery circuit using a DLL (Delay Locked Loop) technique (for example, a non-patent document) 2) is known.

  FIG. 6 is a diagram illustrating an example of a clock / data recovery circuit using the PLL technology.

  The clock / data recovery circuit 100 shown in FIG. 6 includes a phase comparator 101 that outputs a phase difference signal between input data DataIn from the outside and a clock CK from the inside, and a signal corresponding to the phase difference signal at a DC level. A charge pump / loop filter 102 for converting the input voltage DataIn to the control voltage, a voltage controlled oscillator 103 that outputs a clock CK having a frequency corresponding to the control voltage, and a flip-flop 104 that takes in the input data DataIn using the clock CK. Is provided.

  In this clock and data recovery circuit 100, feedback is performed so that the phase of the clock CK from the voltage controlled oscillator 103 and the input data DataIn are in phase, and finally the timing of the input data DataIn from the flip-flop 104 is reset correctly. The retimed data (timed) RetimedData is output.

  FIG. 7 is a diagram showing another example of a clock / data recovery circuit using PLL technology.

  The clock / data recovery circuit 200 shown in FIG. 7 includes a phase frequency comparator 201 that outputs an error signal of the phase and frequency between an external reference signal REF and an internal clock, and a signal corresponding to the error signal. A charge pump / loop filter 202 for converting to a DC level control voltage, a voltage controlled oscillator 203 for outputting a plurality of clocks each having a phase shifted in accordance with the control voltage, and out of these clocks And a selector 204 that selectively outputs any one of the clocks.

  The clock / data recovery circuit 200 also includes a phase comparator 205 that outputs a phase difference signal between the clock CK selected and output from the selector 204 and externally input data DataIn, and a signal corresponding to the phase difference signal. And a flip-flop 207 that takes in the input data DataIn using the clock CK from the selector 204.

  In the clock / data recovery circuit 200, in the loop A, coarse adjustment is performed so that the phase and frequency of the clock output from the voltage controlled oscillator 203 matches the phase and frequency of the reference signal REF. Next, in the loop B, fine adjustment is performed so that the phase of the clock CK output from the selector 204 matches the phase of the input data DataIn, and the timing of the input data DataIn is correctly set using the clock CK. Retimed data RetimedData is output from the flip-flop 207.

  FIG. 8 is a diagram illustrating an example of a clock / data recovery circuit using DLL technology.

  The clock / data recovery circuit 300 shown in FIG. 8 includes a phase comparator 301 that outputs a phase difference signal between input data DataIn from the outside and a clock CK from the inside, and a DC level control according to the phase difference signal. Using the loop filter 302 that outputs the voltage Vcont, the voltage control delay line 303 that generates the clock CK by controlling the delay amount of the reference clock REFCK input from the outside according to the control voltage Vcont, and the clock CK A flip-flop 304 that takes in the input data DataIn is provided.

In the clock / data recovery circuit 300, the delay amount of the reference clock REFCK input to the voltage control delay line 303 is controlled according to the control voltage Vcont from the loop filter 302, and the generated clock CK is used. Then, the timing of the input data DataIn is correctly set, and the retimed data RetimedData is output from the flip-flop 304.
“Journal of Solid-State Circuits, Vol34, No12, December 1999, p1951-1960” A2-1600 MHz CMOS Clock Recovery PLL with Low-Vdd Capability “Journal of Solid-State Circuits, Vol37, No6, June 2002, p711-715” A900 Mb / s CMOS Data Recovery DLL Using Half-Frequency Clock

  In the clock / data recovery circuit 100 shown in FIG. 6 described above, the initial state of the voltage controlled oscillator 103 may fluctuate due to variations in the manufacturing process. In that case, the voltage controlled oscillator 103 may not perform an appropriate operation.

  In the clock / data recovery circuit 200 shown in FIG. 7, the phase and frequency of the clock output from the voltage controlled oscillator 203 are matched with the phase and frequency of the reference signal REF (after coarse adjustment), and then the digital Since the phase of the clock is adjusted (finely adjusted) to the phase of the input data DataIn using the filter 206, the above-described problem is solved, but depending on the setting of the constant of the loop filter in the charge pump / loop filter 202, There is a problem that the loop including the voltage controlled oscillator 203 becomes unstable. In particular, when a built-in capacitor is used as a loop filter, if the capacitor is set to be small for cost reduction, it tends to become unstable and therefore sensitive to variations in the manufacturing process.

  Further, the clock / data recovery circuit 300 shown in FIG. 8 inserts a voltage control delay line 303 (DLL) into the path of the clock CK that takes in the input data DataIn, and provides feedback so that the input data DataIn is most easily taken in. To adjust the DLL delay amount. In this way, since the clock / data recovery circuit is realized only by DLL without using a VCO (voltage controlled oscillator), stable loop control can be performed as compared with the case where a VCO is used. However, in this clock / data recovery circuit 300, it is necessary to input the reference clock REFCK. In addition, the frequency of the reference clock REFCK needs to be the same as the frequency of the input data DataIn. For this reason, for example, when the input data DataIn having a frequency of 2 GHz is captured, the reference clock REFCK having a frequency of 2 GHz is required, and therefore, a very high-speed reference clock REFCK is required. When the high-speed reference clock REFCK is input from the outside in this way, there arises a problem that the apparatus is increased in cost and the design is complicated.

  In view of the above circumstances, an object of the present invention is to provide a clock / data recovery circuit in which the stability of the circuit is enhanced without inputting a high-speed reference clock from the outside.

The clock and data recovery circuit of the present invention that achieves the above-described object provides:
In a clock / data recovery circuit that generates a clock synchronized with input data that may remain at an H level or an L level, which is an arbitrary number of consecutive bits within a predetermined maximum number of bits, and that takes in the input data using the clock,
1-bit delay element composed of two half-bit delay elements with a variable delay amount for delaying the time of ½ of one cycle of the data input period for each bit of the input data is equal to or more than the maximum number of bits in series. A delay unit connected to delay the input data;
The first edge that is one of the rising edge and the falling edge of the input data, and the other of the rising edge and the falling edge of the output of each 1-bit delay element arranged in the delay unit. A phase comparator for comparing the phase with the second edge,
Based on the phase comparison result by the phase comparison unit, the delay amount of each half-bit delay element arranged in the delay unit is adjusted to a time half of one cycle of the data input cycle for each bit of the input data. A delay amount adjustment unit;
A clock generation unit that generates a clock having a period synchronized with an input period of input data, based on outputs of a plurality of half-bit delay elements arranged in the delay unit;
And a data capture unit that captures the input data using the clock generated by the clock generation unit.

  The clock / data recovery circuit according to the present invention is one of the rising edge and falling edge of input data which may remain at an arbitrary number of consecutive bits within a predetermined maximum number of bits, H level or L level. 1 and the phase of the output of each 1-bit delay element arranged in the delay unit between the rising edge and the second edge which is the other of the falling edges, and the phase comparison result Based on this, the delay amount of each half-bit delay element arranged in the delay unit is adjusted. Based on the outputs of the plurality of half-bit delay elements arranged in the delay unit adjusted in this way, a clock having a period synchronized with the input period of the input data is generated, and the input is performed using the clock. It captures data. Accordingly, a clock / data recovery circuit using the DLL technology and a clock / data recovery circuit that does not require the input of a reference clock from the outside are configured.

  Therefore, it is not necessary to provide a VCO (Voltage Controlled Oscillator) compared to a clock / data recovery circuit using PLL technology, and therefore the range of loop constants to operate properly is wide, and fluctuations caused by variations in manufacturing processes, etc. Can be kept small, and the stability of the circuit is increased. Further, compared with a conventional clock / data recovery circuit using DLL technology, it is not necessary to input a high-speed reference clock from the outside, so that the cost can be reduced and the design can be simplified.

  Here, the phase comparison unit outputs the output level of the 1-bit delay element arranged in the delay unit and the two half-bit delays constituting the 1-bit delay element at the timing of the first edge of the input data. The output level of the half bit delay element on the preceding stage of the elements and the half bit on the preceding stage of the two half bit delay elements constituting the next 1 bit delay element connected to the subsequent stage of the 1 bit delay element Comparison with the output level of the delay element is performed for a plurality of 1-bit delay elements arranged in the delay unit, and the advance or delay of the phase of the data passing through the delay unit with respect to the phase of the input data is detected. It is preferable.

  In this way, it is possible to accurately detect the advance or delay of the phase of the data passing through the delay unit with respect to the phase of the input data.

  The clock generation unit includes an output of a 1-bit delay element arranged in the delay unit, and an output of a half-bit delay element on the preceding stage of two half-bit delay elements constituting the 1-bit delay element, It is also a preferable aspect that a clock is generated by obtaining an exclusive OR of a plurality of 1-bit delay elements arranged in the delay unit and obtaining an OR of the plurality of exclusive ORs.

  In this way, a clock for capturing input data can be generated with a simple circuit.

  According to the clock and data recovery circuit of the present invention, the stability of the circuit can be improved without inputting a high-speed reference clock from the outside.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a clock / data recovery circuit according to an embodiment of the present invention.

  The clock / data recovery circuit 1 shown in FIG. 1 generates a clock RCK synchronized with input data DataIn that may remain at an arbitrary number of bits H level or L level within a predetermined maximum number of bits, and the clock RCK Is a circuit that takes in the input data DataIn. Here, the predetermined maximum number of bits varies depending on the communication method or the like, but is 5 bits in the case of an application based on the well-known 8B / 10B coding system, for example. In the present embodiment, description will be made by taking 5 bits as an example.

  The clock / data recovery circuit 1 includes a delay unit 10 that inputs and delays input data DataIn. The delay unit 10 is configured such that a 1-bit delay element 11 formed of two serially connected half-bit delay elements each having a variable delay amount that delays a time of 1/2 of one data input period of each bit of the input data DataIn has a maximum bit. The same number (5) as the number is connected in series.

  The clock / data recovery circuit 1 includes a phase comparison unit 20. The phase comparison unit 20 includes a falling edge of input data DataIn (corresponding to a first edge in the present invention) and an output (data D1, D2, D3) of each 1-bit delay element 11 arranged in the delay unit 10. , D4, D5) with respect to the rising edge (corresponding to the second edge in the present invention). Here, details of the phase comparison unit 20 will be described with reference to FIGS.

  2 is a diagram showing a part of both the delay unit and the phase comparison unit shown in FIG. 1, and FIG. 3 is a diagram showing timings in the delay unit and the phase comparison unit shown in FIG.

  FIG. 2 shows only three 1-bit delay elements 11 constituting the delay unit 10. Further, flip-flops 21, 22, 23, AND gates 24, 25, and OR gates 26, 27 constituting the phase comparator 20 are shown.

  The phase comparison unit 20 configures the output level of the 1-bit delay element 11 arranged in the delay unit 10 (here, the level of the data D4) and the 1-bit delay element 11 at the timing of the falling edge of the input data DataIn. Of the two half-bit delay elements to be output, the output level of the half-bit delay element on the previous stage side (here, the level of the data D3h) and the next 1-bit delay element 11 connected to the subsequent stage of the 1-bit delay element 11 Comparison with the output level of the half-bit delay element on the preceding stage of the two half-bit delay elements to be configured (here, the level of the data D4h) is performed by the flip-flops 21, 22, 23 and the AND gates 24, 25. , The advance of the phase of data (here, data D4) passing through the delay unit 10 with respect to the phase of the input data DataIn or Detecting the record, the late_4 signal of H level representing a early_4 signal or delay of H level representing an advance, to output to the OR gate 26, 27. The remaining four 1-bit delay elements 11 arranged in the delay unit 10 are also output, and finally an H-level early signal indicating advance or an H-level late signal indicating delay is output from the OR gates 26 and 27. To do.

  That is, in the phase comparison between the input data DataIn and the data D4, the data D4 is captured at the timing of the falling edge of the input data DataIn. Therefore, when the data D4 is at the H level and the data D4h is at the L level, the AND gate 24 To H level early_4 signal is output. On the other hand, when the data D4 is at the L level and the data D3h is at the H level, the AND gate 25 outputs an H level late_4 signal.

  Specifically, as shown in FIG. 3A, at the timing of the falling edge of the input data DataIn, the data D4 that has changed from the L level to the H level and the data D4h that is still at the L level are flip-flops 21, 23. Is input. Then, the flip-flops 21 and 23 output the H level and the L level. Since these H level and L level are input to the AND gate 24, the AND gate 24 outputs an H level early_4 signal. As shown in FIG. 3B, when both of the data D4 and D4h are at the H level, the flip-flops 21 and 23 output the H level, so the AND gate 24 outputs the L level. The

  Further, as shown in FIG. 3C, at the timing of the falling edge of the input data DataIn, the data D4 that is still at the L level and the data D3h that has changed from the L level to the H level are input to the flip-flops 21 and 22. Is done. Then, the flip-flops 21 and 22 output the L level and the H level. Since these L level and H level are input to the AND gate 25, an H level late_4 signal is output from the AND gate 25. As shown in FIG. 3D, when both the data D4 and D3h are at the L level, the L level is output from the flip-flops 21 and 22, and therefore the L level is output from the AND gate 25. The

  In the present embodiment, in addition to the early_4 signal and the late_4 signal corresponding to the data D4, there are the early_1, early_2, early_3, early_5 signal and the late_1, late_2, late_3, and late_5 signals corresponding to the data D1, D2, D3, and D5. For this reason, the early and late signals output from the OR gates 26 and 27 may be at the H level with a plurality of signals. Therefore, the output is output toward the charge pump / loop filter 30 shown in FIG. 1 using the 5-input OR gates 26 and 27.

  By doing so, the falling edge of the input data DataIn that may stay at any arbitrary number of bits within the predetermined maximum number of bits (here, 5 bits) H level or L level, and the delay unit 10 are arranged. The phase of the output (data D1, D2, D3, D4, D5) of each of the 1-bit delay elements 11 thus made can be compared.

  In this example, the phase of the falling edge of the input data DataIn and the rising edge of the output of each 1-bit delay element 11 are compared. However, the rising edge of the input data DataIn and each 1-bit delay element are described. 11 may be compared in phase with the rising edge of the output, and by combining these, the phase between both edges of the input data DataIn and both edges of the output of each 1-bit delay element 11 may be compared. May be.

  With reference to FIG. 1 again, the configuration of the clock / data recovery circuit 1 will be described. The clock / data recovery circuit 1 is provided with a charge pump / loop filter 30 (corresponding to an example of a delay amount adjusting unit according to the present invention). The charge pump / loop filter 30 determines the delay amount of each half-bit delay element arranged in the delay unit 10 based on the early signal and the late signal, which are the phase comparison results by the phase comparison unit 20, as 1 of the input data DataIn. A Vcont signal for adjusting the data input period for each bit to ½ of one period is output. When the early signal is input to the charge pump / loop filter 30, the delay of the delay element 11 is increased, and when the late signal is input, the delay of the delay element 11 is decreased.

  The clock / data recovery circuit 1 includes a clock generation unit 40 and a flip-flop 50. Based on the data D0h, D1h, D2h, D3h, and D4h, which are the outputs of the plurality of half-bit delay elements arranged in the delay unit 10, the clock generation unit 40 is a clock RCK having a period synchronized with the input period of the input data DataIn. (RECOVERD CLOCK) is generated.

  Specifically, the clock generation unit 40 outputs the output (for example, data D1) of the 1-bit delay element 11 arranged in the delay unit 10 to the preceding stage of the two half-bit delay elements constituting the 1-bit delay element 11. The exclusive OR with the output (for example, data D0h) of the half bit delay element on the side is obtained for the five 1-bit delay elements 11 arranged in the delay unit 10, and the OR of these five exclusive ORs is obtained. As a result, the clock RCK is generated.

  FIG. 4 is a circuit diagram of the clock generator shown in FIG. 1, and FIG. 5 is a timing chart of the clock / data recovery circuit shown in FIG.

  The clock generation unit 40 shown in FIG. 4 includes exclusive OR gates 41, 42, 43, 44, 45 and an OR gate 46.

  The exclusive OR gate 41 receives the data D1 from the 1-bit delay element 11 and the data D0h from the preceding half-bit delay element of the two half-bit delay elements constituting the 1-bit delay element 11 Is done. Similarly, data D2 and D1h are input to the exclusive OR gate 42, data D3 and D2h are input to the exclusive OR gate 43, data D4 and D3h are input to the exclusive OR gate 44, and exclusive X Data D5 and D4h are input to the OR gate 45.

  In the clock / data recovery circuit 1, as shown in FIG. 5, the phase between the falling edge of the input data DataIn and the rising edges of the data D1, D5, D2, D1 and D4 from the 1-bit delay elements 11 in time order. As a result, the signals XOR (D0h, D1), XOR (D1 h, D2), XOR (D2 h, D3), XOR shown in FIG. 5 are obtained from the exclusive OR gates 41, 42, 43, 44, 45 described above. (D3h, D4) and XOR (D4h, D5) are output.

  The OR gate 46 obtains the OR of these signals (signal OR ALL shown in FIG. 5), and outputs a clock RCK represented by this signal OR ALL. In this way, the clock RCK having a period synchronized with the input period of the input data DataIn is generated.

  This clock RCK is input to the flip-flop 50. Further, input data DataIn is also input to the flip-flop 50. The flip-flop 50 takes in the input data DataIn using the clock RCK, and finally, the flip-flop 50 outputs the retimed data RetimedData in which the timing of the input data DataIn is correctly reset.

  The clock / data recovery circuit 1 of the present embodiment includes a falling edge of input data DataIn that may remain at an arbitrary number of bits H level or L level within a predetermined maximum number of bits (5 bits), and a delay unit. 10 is compared with the phase of the rising edge of the output (data D1, D2, D3, D4, D5) of each 1-bit delay element 11 arranged in 10, and the delay unit is based on the phase comparison result. The delay amount of each half-bit delay element arranged in 10 is adjusted by the charge pump / loop filter 30. Further, based on the outputs (data D0h, D1h, D2h, D3h, D4h) of the plurality of half-bit delay elements arranged in the delay unit 10 adjusted in this way by the clock generation unit 40, the input data DataIn The clock generator 40 generates a clock RCK having a period synchronized with the input period, and the flip-flop 50 takes in the input data DataIn using the clock RCK. Therefore, the clock / data recovery circuit 1 using the DLL technique and the input of the reference clock from the outside is not required.

  Therefore, it is not necessary to provide a VCO (Voltage Controlled Oscillator) compared to a clock / data recovery circuit using PLL technology, and therefore the range of loop constants to operate properly is wide, and fluctuations caused by variations in manufacturing processes, etc. Can be kept small, and the stability of the circuit is increased. Further, compared with a conventional clock / data recovery circuit using DLL technology, it is not necessary to input a high-speed reference clock from the outside, so that the cost can be reduced and the design can be simplified.

It is a figure which shows the clock data recovery circuit of one Embodiment of this invention. It is a figure which shows a part of both the delay part shown in FIG. 1, and a phase comparison part. It is a figure which shows the timing in the delay part and phase comparison part which are shown in FIG. FIG. 2 is a circuit diagram of a clock generation unit shown in FIG. 1. 3 is a timing chart of the clock / data recovery circuit shown in FIG. 1. It is a figure which shows an example of the clock data recovery circuit using PLL technology. It is a figure which shows another example of the clock data recovery circuit using PLL technology. It is a figure which shows an example of the clock data recovery circuit using DLL technique.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Clock data recovery circuit 10 Delay part 11 1 bit delay element 20 Phase comparison part 21, 22, 23, 50 Flip-flop 24,25 AND gate 26,27,46 OR gate 30 Charge pump loop filter 40 Clock generation part 41, 42, 43, 44, 45 Exclusive OR Gate

Claims (3)

In a clock and data recovery circuit that generates a clock synchronized with input data that may remain at an H level or an L level, which is continuously at an arbitrary number of bits within a predetermined maximum number of bits, and that takes in the input data using the clock,
The number of 1-bit delay elements consisting of two half-bit delay elements, which are variable in the amount of delay for delaying the time of ½ of one cycle of the data input period for each bit of the input data, is equal to or greater than the maximum number of bits in series. A delay unit connected to delay the input data;
The first edge that is one of the rising edge and the falling edge of the input data, and the other one of the rising edge and the falling edge of the output of each 1-bit delay element arranged in the delay unit. A phase comparator for comparing the phase with the second edge,
Based on the phase comparison result by the phase comparison unit, the delay amount of each half-bit delay element arranged in the delay unit is adjusted to a time half of one cycle of the data input cycle for each bit of the input data. A delay amount adjustment unit;
A clock generation unit that generates a clock having a period synchronized with an input period of input data, based on outputs of a plurality of half-bit delay elements arranged in the delay unit;
A clock / data recovery circuit comprising: a data capturing unit that captures the input data using the clock generated by the clock generating unit.   The phase comparison unit includes an output level of the 1-bit delay element arranged in the delay unit at the timing of the first edge of the input data and two half-bit delay elements constituting the 1-bit delay element. The output level of the half-bit delay element on the front stage side of the first half-bit delay element and the half-bit delay element on the front-stage side of the two half-bit delay elements constituting the next 1-bit delay element connected to the subsequent stage The comparison with the output level is performed for a plurality of 1-bit delay elements arranged in the delay unit, and the advance or delay of the phase of the data passing through the delay unit with respect to the phase of the input data is detected. The clock / data recovery circuit according to claim 1.   The clock generation unit excludes the output of the 1-bit delay element arranged in the delay unit and the output of the half-bit delay element on the preceding stage of the two half-bit delay elements constituting the 1-bit delay element 2. The clock according to claim 1, wherein a clock is generated by obtaining a logical sum of a plurality of 1-bit delay elements arranged in the delay unit and obtaining an OR of the plurality of exclusive ORs. -Data recovery circuit.

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