JP2006286190A - Semiconductor nonvolatile memory device and computer system using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor nonvolatile memory device and a computer system using the memory device, capable of setting a new operating sequence, suppressing erratic phenomena inside the device, and improving a rewrite resistance in an electrically rewritable semiconductor nonvolatile memory device. <P>SOLUTION: The nonvolatile semiconductor memory device comprises; flip-flops having a memory cell array in which a plurality of nonvolatile semiconductor memory cells are arranged in an array form, a word line to which the control gates of a plurality of memory cell groups (sectors) are connected in common, a bit line to which the drains of a plurality of memory cells are connected in common, and performing latching operation of data at the time of sense operation and increasing write-in data and a threshold voltage for each bit line; and a sense latch circuit including a circuit which automaticaly setting re-data of the flip-flop for each bit according to the threshold state of the memory cells after verified. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor nonvolatile memory device including a transistor capable of electrically rewriting a threshold voltage, and suitable for a case where the threshold voltage is electrically rewritten frequently. More particularly, the present invention relates to a technical field that enables stable read operation of a semiconductor nonvolatile memory device driven by a single power supply voltage and miniaturization of the device.

  There is a flash memory as a semiconductor non-volatile memory device having a one-transistor / cell structure that can electrically erase stored contents. The flash memory has a small area occupied per bit and can be highly integrated due to its structure, and thus has been attracting attention in recent years, and research and development on its structure and driving method are actively conducted.

  For example, the DINOR system described in Symposium on VLSI Circuits Digest of Technical Papers pp97-98 1993 (Non-patent Document 1), and the second is described in pp99-100 1993 (Non-patent Document 2). NOR method, third, the AND method described in pp 61-62 1994 (Non-patent Document 3), and fourth, International Electron Devices meeting Tech. Dig. The HICR system described in pp 19-22 (Non-Patent Document 4) has been proposed.

  In each of the above methods, the word line potential is set to the power supply voltage Vcc at the time of reading, a low voltage of about 1 V is applied to the bit line potential so that weak electrons are not extracted, and the sense amplifier circuit reads out information from the memory cell. Do. When the state in which electrons are accumulated in the floating gate is defined as the erased state, in the erased state, the threshold voltage of the memory cell becomes high. The charge potential is 1V. If a state in which electrons are not injected (electrons are emitted) is defined as a write state, the memory cell threshold voltage is low in the write state, so that when a word line is selected, a current flows and the bit line potential Becomes lower than the precharge potential of 1V. The bit line potential is amplified by a sense amplifier, and information “0” or “1” is determined.

  For example, the AND (AND) method described in International Electron Devices meeting Tech. Dig. Pp 991-993 1992 (Non-patent Document 5), and second, pp 19-22. The HICR system described in 1993 (Non-Patent Document 6) has been proposed.

  In each of the above methods, an operation for increasing the threshold voltage of a memory cell in a sector in units of word lines is defined as an erase operation.

The erase operation voltage of the AND method described in Symposium on VLSI Circuits Digest of Technical Papers pp 61-62 1994 (Non-Patent Document 3) is a selected sector, that is, a selected word. A positive high voltage of 16 V is applied to the line, and the drain and source terminal voltages of the memory cell are set to 0 V of the ground voltage Vss. A voltage difference occurs between the floating gate and the channel of the memory cell in the selected sector, and electrons in the channel are injected into the floating gate by the Fowler-Nordheim tunneling phenomenon, increasing the threshold voltage of the memory cell. Erase operation is possible.
Symposium on VLSI Circuits Digest of Technical Papers pp97-98 1993 Symposium on VLSI Circuits Digest of Technical Papers pp99-100 1993 Symposium on VLSI Circuits Digest of Technical Papers pp61-62 1994 International Electron Devices meeting Tech. Dig. pp19-22 International Electron Devices meeting Tech. Dig.pp991-993 1992 International Electron Devices meeting Tech. Dig.pp 19-22 1993

  By the way, in the flash memory of the above method, if the threshold voltage of the memory cell becomes a negative voltage, it may cause erroneous reading. Therefore, it is necessary to control the memory cell so that the threshold voltage does not become a negative voltage. is there. Therefore, conventionally, the write operation sequence shown in FIG. 29 is executed. For example, in the AND-type write operation as the third conventional technique, data write is performed collectively by setting a unit write time to a memory cell group (sector) connected to a predetermined word line of the memory cell array. Thereafter, when there is a memory cell that is insufficiently written by reading the memory cell data, an operation of performing rewriting (verify operation) is performed. The word line potential during the verify operation for confirming whether the threshold voltage of the memory cell has reached the write threshold voltage is determined by taking into account the spread of the distribution of the write threshold voltage in the memory cell group in the sector. The threshold voltage of all the memory cells is set to a value that does not become a negative value, for example, 1.5V.

  Symposium on VLSI Technology Digest of Technical Papers pp 83-84 1993 includes an erratic defect, that is, the injection and emission of electrons in the floating gate through the tunnel film which is an insulating film. The phenomenon that the internal electric field in the tunnel film is strengthened while the voltage is positively charged, and electrons are likely to be locally emitted from the floating gate, or the trap level is charged to a positive voltage depending on the number of rewrites. Have been reported. In the above conventional technique, as shown in FIG. 26, the erratic defect that occurred during the write operation cannot be detected, and when the erratic defect occurs, accurate information cannot be read from the semiconductor nonvolatile memory device. There was a point.

  On the other hand, in each of the above methods, the write operation is an operation for lowering the threshold voltage of the selected memory cell. In the AND type, according to the description, a sense latch circuit that performs a write data latching operation for each bit line of a memory cell is provided, and writing in units of sectors is performed collectively. A negative voltage of −9 V is applied to the control gate of the memory cell, that is, the word line, and the drain terminal voltage of the memory cell is set to 4 V in the selected cell and 0 V in the non-selected cell according to the data of the sense latch circuit. A voltage difference is generated between the floating gate and the drain of the selected memory cell, and electrons in the floating gate are extracted to the drain side by the Fowler-Nordheim tunnel phenomenon. In a non-selected memory cell, since the voltage difference between the floating gate and the drain is small, the emission of electrons in the floating gate can be prevented.

  In the write operation, the memory cell of the non-selected sector is weakened by the selected drain terminal voltage and the threshold voltage is lowered. In order to prevent this, the power supply voltage Vcc is applied to the unselected word lines.

  In the conventional AND-type semiconductor nonvolatile memory device described above, the breakdown voltage of the MOS transistor constituting the device needs to be 16 V or more, which is the word line voltage of the erase operation in which the potential difference becomes the largest among the write and erase operations. . In order to ensure the withstand voltage, the gate insulating film of the MOS transistor is made thicker, for example, 25 nm or more to reduce the electric field strength applied to the gate oxide film, and the diffusion layer has a high withstand voltage structure, and a minimum processing rule of 0.4 μm is used. Even if it is, the gate length must be 1.5 μm or more, for example. As a result, there is a problem that the layout area of the MOS transistor increases and the chip size of the semiconductor nonvolatile memory device increases.

  For such a flash memory, for example, an AND type described in Japanese Patent Laid-Open No. 7-176705 has been proposed. FIG. 19 is a connection diagram of memory cells, and FIG. 20 is a schematic layout diagram of FIG. 1 of JP-A-7-176705.

  A unit block in which a plurality of memory cells are connected in the column direction is formed, the drain of the memory cell is connected to a bit line via a MOS transistor, and the source of the memory cell is connected to a common source line via a MOS transistor. A plurality of unit blocks are connected to the bit line. As shown in FIG. 20, the common source line is formed of a diffusion layer in a direction perpendicular to the bit lines, and L (SL), and for each sub-number of bit lines, the bit lines are parallel to the bit lines. Wiring is performed using metal wiring M1 (SL) in the same layer.

  In the conventional AND type flash memory, the read operation and the verify operation of the threshold voltage of the memory cell after rewriting are performed in a batch for each sector of the memory cell group connected to the word line. Since the common source line L (SL) is formed of a diffusion layer, the common source line L (SL) is generated by the memory cell current flowing through the common source line L (SL) as shown in the equivalent circuit of the memory cell array in FIG. A voltage effect occurs at. As a result, the memory cell is effectively subjected to a substrate bias, and the threshold voltage is changed. The amount of variation in the threshold voltage varies depending on the information pattern stored in the memory cell and the position of the memory cell. On the other hand, although the sub source line Sub Source Line is also formed of a diffusion layer, only the current corresponding to one memory cell flows, so that it does not cause the memory cell threshold voltage variation for the sector.

  FIG. 56 shows the threshold voltage dependency on the bit line position of the memory cell. The substrate bias has the greatest influence on the memory cell far from the source line, and the threshold voltage of the memory cell increases due to the substrate bias effect. All bits in the memory cell are the write bits, that is, the maximum when the threshold voltage is low and the cell current flows. On the other hand, the threshold voltage is the lowest in the write cell of 1 bit of only the cell adjacent to the source line. The above threshold voltage difference ΔVth causes the threshold voltage variation of the memory cell in the sector.

  In reading the memory information, it is necessary to reduce the threshold voltage difference ΔVth and stabilize the reading operation. For this reason, it is necessary to form the common source line M1 (SL) in FIG. 20 for every 32 bit lines, but there is a problem that the area of the memory array portion increases by 3% or more.

  Accordingly, an object of the present invention is to provide a semiconductor non-volatile memory device that can newly set an operation sequence, suppress an erratic phenomenon inside the device, and improve rewrite durability in an electrically rewritable semiconductor non-volatile memory device. It is an object to provide a sexual storage device and a computer system using the same.

  Another object of the present invention is to reduce the chip size by reducing the maximum voltage of the erase operation of the electrically rewritable semiconductor nonvolatile memory device to the same level as the maximum operation voltage of the write operation. An apparatus and a computer system using the same are provided.

  Furthermore, another object of the present invention is to stabilize reading of information in units of sectors in a semiconductor non-volatile memory device that can be electrically rewritten, that is, to reduce threshold voltage variation, It is an object of the present invention to provide a semiconductor nonvolatile memory device in which the area of the device is reduced.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the semiconductor non-volatile memory device that solves the first problem of the present invention is a semiconductor non-volatile memory including a transistor that can electrically rewrite (erase, write) the threshold voltage represented by FIG. A memory cell that is applied to a device and that is newly connected to a word line after the threshold voltage is lowered collectively or selectively in a write operation (threshold voltage lowering) sequence Semiconductor nonvolatile memory with an operation sequence for verifying the threshold voltage in batches in groups and then increasing the threshold voltage in response to the threshold voltages of each memory cell Device.

  As shown in the functional block diagram of the semiconductor nonvolatile memory device of FIG. 12, for each bit line of the memory cell, a flip-flop that performs a sense operation and a data latch operation during an operation of increasing write data and a threshold voltage; A circuit that automatically sets flip-flop re-data for each bit according to the threshold state of the memory cell after verification, a generic sense latch circuit, and a voltage for returning the memory cell threshold voltage by the built-in power supply voltage circuit A semiconductor nonvolatile memory device that generates a verify word line voltage and the like.

  The computer system according to the present invention includes at least a central processing unit and its peripheral circuits in addition to the semiconductor nonvolatile memory device.

  According to the above-described semiconductor nonvolatile memory device and a computer system using the same, a memory cell newly newly connected to a word line in the device automatically in a write operation (threshold voltage lowering) sequence A semiconductor nonvolatile memory device having operation means for verifying a threshold voltage in batches in a group and then increasing the threshold voltage in response to the threshold voltage of each memory cell Thus, the memory cell threshold voltage lowered by the erratic phenomenon can be returned, and the threshold voltage distribution can be reduced. Further, by reading the verify word line voltage at the ground potential (Vss), the threshold voltage can be selectively returned to the bit that has been depleted by the erratic phenomenon, thereby preventing erroneous reading.

  For example, after the memory cell threshold voltage after writing is set to 1.5 V, the emission of electrons in the floating gate and the verify operation are repeated, and all the memory cell threshold voltages to be written are set to 1.5 V or less. Then, the potential of the selected word line is verified (read) with the ground potential (Vss), the cell having a memory cell threshold voltage of 0 V or less (depletion) and a cell that has dropped due to the erratic phenomenon is selected, and the read data of the sense latch circuit Using flip-flop data, the bit line, that is, the drain voltage is selectively set to the ground potential (Vss), the potential of the selected word line to which writing is performed is set to a high voltage of about 16 V, and the Fowler-Nordheim tunnel phenomenon on the entire channel surface is used. The memory cell threshold voltage is selectively returned by injecting electrons into the floating gate.

  Since the data in the flip-flop of the sense latch circuit connected to the memory cell that has not been depleted is the power supply voltage, there is sufficient space between the channel potential (power supply voltage) and the word line during the operation of raising the threshold voltage. Since no electric field difference occurs, the memory cell threshold voltage of 1.5 V after writing can be maintained.

  In addition, the number of rewrites can be greatly improved by the present invention without determining restrictions on the number of rewrites in consideration of the erratic phenomenon.

  Furthermore, by using the Fowler-Nordheim tunnel phenomenon for returning the memory cell threshold voltage, a single power source with a low voltage can be achieved.

  As a result, in the nonvolatile semiconductor memory device that can be electrically rewritten, it is possible to suppress the erratic phenomenon and improve the rewrite endurance by the write operation sequence in which the verify operation and the operation of returning the threshold value are added. In particular, in a computer system or the like using this, power consumption can be reduced and reliability can be improved by lowering the voltage.

  In the erase operation of the semiconductor nonvolatile memory device that solves the second problem, a positive high voltage has been applied only to the selected word line in the past. In the present invention, a positive voltage is applied to the word line voltage. The negative voltage is distributed and applied to the memory well to supply the erase operation voltage. The absolute value of the memory well voltage is approximately the same as or lower than the word line voltage at the time of reading.

  FIG. 33 shows a conceptual diagram of the memory mat of the present invention. Sectors constituting the memory mat of the semiconductor nonvolatile memory device are selected in the erase operation, a positive voltage is applied to the word line (selected sector), the erase is not selected, and the word line voltage and the memory well voltage are different. A sector (unselected sector) and a sector (completely unselected sector) in which erasing is not selected and the word line voltage is equal to the source-drain voltage (channel voltage) of the memory cell are provided.

  From a memory cell in which a completely unselected sector applies a negative voltage to the memory well in the erase operation and the channel voltage and the word line voltage are the ground voltage, or from the memory cell in which the memory well voltage, the channel voltage and the word line voltage are the ground voltage Become. In this case, the memory cell is connected to a unit block in which a plurality of memory cells are connected in parallel, the drain of the memory cell is connected to a bit line via a MOS transistor, and the source of the memory cell is connected to a MOS transistor. Connected to the source line.

  Therefore, the selected sector and the non-selected sector are the same unit block, and the sectors constituting the other blocks are completely non-selected sectors.

  FIG. 35 is a schematic cross-sectional view of a memory cell of a semiconductor nonvolatile memory device. In order to apply a negative voltage to the memory cell, the well DP well of the memory cell, the well of the MOS transistor, and the well of the MOS transistor that transfers the potential of the source line and bit line of the memory cell are connected to the substrate p-sub The separation layer is formed in the niso region for separation.

  As shown in the functional block diagram of the semiconductor nonvolatile memory device of FIG. 37, the semiconductor nonvolatile memory device of the present invention divides the memory mat without breaking the sector unit and switches the well voltage of the memory mat. A row decoder circuit XDCR for selecting a word line, that is, a sector, a sense latch circuit SL for performing a sensing operation and a writing data latching operation, a word line voltage Vh for an erasing operation voltage, a memory well voltage Vmw, and a word line for a writing operation voltage A built-in power supply circuit VS that generates a voltage Vl, a bit line voltage Vlb, and the like is provided.

  Further, the rising waveform of the erase voltage in the erase operation is applied with a load capacitance and is raised in several μs to several tens of μs, thereby preventing an abrupt electric field from being applied to the memory cell. The semiconductor nonvolatile memory device is provided with a mode control circuit MC that sets the voltage arrival time at the rise of the memory well voltage equal to the voltage arrival time of the word line voltage.

  The computer system of the present invention has at least a central processing unit and its peripheral circuits in addition to the semiconductor nonvolatile memory device.

  In the present invention, 12V is applied to the selected word line via the row decoder circuit XDCR, and -4V is applied to the memory well via the memory mat well switching circuit MWVC, so that the application to the memory cells required for the erase operation is performed. A voltage of 16V is achieved. Therefore, the maximum voltage applied to the MOS transistor of the row decoder circuit XDCR is 12V, and the breakdown voltage can be reduced from 16V to 12V.

  On the other hand, in the write operation, −9 V is applied to the selected memory cell via the row decoder circuit XDCR, 4 V is applied to the selected bit line according to the data of the sense latch circuit SL, and the unselected word line voltage is applied to the power supply voltage Vcc. It is said. For this reason, the MOS transistor of the row decoder circuit XDCR needs to select -9V and the power supply voltage Vcc. For the power supply voltage Vcc of 3.3V, 12.3V is required as the breakdown voltage of the MOS transistor.

  Therefore, in the MOS transistor constituting the device of the present invention, a maximum withstand voltage of 12.3 V may be ensured by the erase operation and the write operation, and a gate length of about 1 μm can be used.

  In addition, the connection of the memory cell is a unit block in which a plurality of memory cells are connected in parallel, the common drain is connected to the bit line through the MOS transistor, and the source of the unit is connected to the source line through the MOS transistor. In the connected system, only unselected sectors in the same block as the selected sector are disturbed by the memory well voltage. Therefore, the disturb life time can be reduced from the number of sectors crossing the bit line of 8 k bits (1k = 1024 bits) to the number of sectors constituting the unit block, for example, 1/128 of 64 bits, and the reliability can be improved.

  49 shows a layout of a metal wiring layer in which a plurality of unit blocks for solving the third problem are arranged in the bit line direction, and FIG. 2 shows a schematic diagram of a layout of the metal wiring layer of the memory mat.

  In the semiconductor nonvolatile memory device of the present invention, in the memory mat of the memory cell array, the common source line (M1) is not arranged between the bit lines but arranged in parallel with the word line. The metal wiring layer of the common source line (M1) is formed in a manufacturing process prior to the metal wiring layer used for the bit line. At the end of the memory mat including the dummy memory cell column, a layout configuration in which a common source line (M2 or more) in the column direction (parallel to the bit line) is arranged in the same metal wiring layer as the bit line. In addition, the width of the common source line is about 100 times thicker than the width of the bit line.

  The memory cell connection method of the present invention is a unit block configuration in which a plurality of memory cells are connected to at least a bit line via MOS transistors, and the source of each unit block is connected to a common source line (M1). Yes.

  As shown in the functional block diagram of the semiconductor nonvolatile memory device of FIG. 57, the semiconductor nonvolatile memory device of the present invention divides a memory mat without breaking the sector unit and selects a word line, that is, a sector. , A sense latch circuit SNS that performs a sense operation and a write data latch operation, and a built-in power supply circuit VS that generates a rewrite operation voltage.

  By connecting the common source line of the memory cell array mat for each memory cell column of the unit block and disposing no dummy memory cell column between the bit lines, the size of the memory mat can be reduced.

  Also, since the common source line width is about 100 times larger than the bit line width, the substrate bias applied to the same word line, that is, the memory cells connected to the sector, is constant, and variations in threshold voltage are reduced. To do. Therefore, reading of information in units of sectors is stable.

  The present invention relates to a semiconductor non-volatile memory device capable of electrically rewriting and newly setting an operation sequence, suppressing an erratic phenomenon inside the device, and improving the rewriting durability, and a semiconductor non-volatile memory device including the same The computer system used can be provided.

  The present invention also relates to a semiconductor nonvolatile memory device in which the maximum voltage of the erasing operation of the electrically rewritable semiconductor nonvolatile memory device is reduced to the same level as the maximum operating voltage of the write operation, and the chip size is reduced. The computer system used can be provided.

  Furthermore, the present invention provides a semiconductor non-volatile memory device that can be electrically rewritten, a semiconductor in which reading of information in a sector unit is stabilized, that is, a threshold voltage variation is reduced and a device area is further reduced. A nonvolatile memory device can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The basic configuration of the semiconductor nonvolatile memory device of this embodiment will be described with reference to FIG.

  The semiconductor nonvolatile memory device of this embodiment is, for example, an EEPROM composed of a plurality of memory mats composed of transistors whose threshold voltages can be electrically rewritten, and includes a memory mat Memory Mat, a row address buffer XADB, a row address. Decoder XDCR, sense latch circuit SL shared with sense amplifier and data latch, column gate array circuit YG, column address buffer YADB, column address decoder YDACR, input buffer circuit DIB, output buffer circuit DOB, multiplexer circuit MP, mode control circuit MC , A control signal buffer circuit CSB, a built-in power supply circuit VS, and the like.

  In this semiconductor nonvolatile memory device, the control signal buffer circuit CSB is not particularly limited. For example, a chip enable signal and output enable supplied to the external terminals / CE, / OE, / WE, SC, etc. A signal, a write enable signal, a serial clock signal, and the like are input, and a timing signal of an internal control signal is generated in response to these signals, and a ready / busy signal is output from the external terminal R / (/ B) to the mode control circuit MC. Is entered. In this embodiment, “/” such as / CE, / OE, / WE represents a complementary signal.

  Further, the built-in power supply circuit VS is not particularly limited. For example, a power supply voltage Vcc is input from the outside, and a read word line voltage Vrw, a write word line voltage Vww, a write verify word line voltage Vwv, an erase word line Voltage Vew, erase verify word line voltage Vev, read bit line voltage Vrb, read reference bit line voltage Vrr, write drain terminal voltage Vwd, write transfer gate voltage Vwt, low threshold verify word line voltage Vlv, select return word line voltage Vpw, selective return non-selected channel / drain voltage Vpc, selective return transfer gate voltage Vpt, high threshold verification word line voltage Vhv, reselection write word line voltage Vsw, reselection write drain terminal voltage Vsd, reselection Such as a can-inclusive transfer gate voltage Vst is adapted to be generated. The above voltages may be supplied from the outside.

  The voltages generated here are the read word line voltage Vrw, the write word line voltage Vww, the write verify word line voltage Vwv, the erase word line voltage Vew, the erase verify word line voltage Vev, the write transfer gate voltage Vwt, and the low threshold. The value verify word line voltage Vlv, the select return word line voltage Vpw, the select return transfer gate voltage Vpt, the high threshold verify word line voltage Vhv, the reselection write word line voltage Vsw, and the reselection write transfer gate voltage Vst are the row addresses. The decoder XDCR has a read bit line voltage Vrb, a read reference bit line voltage Vrr, a write drain terminal voltage Vwd, a selective return non-selected channel / drain voltage Vpc, a reselective write drain terminal voltage Vsd, a write traffic. Sufageto voltage Vwt, select return transfer gate voltage Vpt, reselected write transfer gate voltage Vst is input to the sense latch circuit SL.

  The built-in power supply voltage may be shared. For example, erase word line voltage Vew and selective return word line voltage Vpw, write word line voltage Vww and reselection write word line voltage Vsw, write drain terminal voltage Vwd and reselection write drain terminal voltage Vsd, and write transfer gate voltage Vwt The selective write transfer gate voltage Vst can be a common voltage.

  In this semiconductor nonvolatile memory device, a row supplied from an external terminal, a row receiving column address signals AX and AY, and a complementary address signal formed through column address buffers XADB and YADB are supplied to the row and column address decoders XDCR and YDCR. Supplied. Although not particularly limited, for example, the row and column address buffers XADB and YADB are activated by a chip enable selection signal / CE inside the device, and take in address signals AX and AY from external terminals, A complementary address signal composed of an internal address signal in phase with the address signal supplied from the terminal and an address signal in reverse phase is formed.

  The row address decoder XDCR forms a selection signal for the word line W of the memory cell group according to the complementary address signal of the row address buffer XADB, and the column address decoder YDCR selects the memory cell according to the complementary address signal of the column address buffer YADB. A selection signal for a group of bit lines B is formed. Thereby, an arbitrary word line W and bit line B are designated in the memory mat Memory Mat, and a desired memory cell is selected.

  Although there is no particular limitation, for example, memory cells are selected in units of 8 bits or 16 bits, in order to perform writing or reading in units of 8 bits or 16 bits, the row address decoder XDCR and the column address decoder YDCR provide 8 or 16 memory cells. Is selected. If the number of memory cells in one data block is m in the word line direction (row direction) and n in the bit line direction (column direction), there are 8 or 16 data blocks in the m × n memory cell group. Consists of

  Here, when an arbitrary memory cell of the memory matrix Memory Matrix is selected and data is read from the selected memory cell, a serial access method is used for the memory cell and a random access method is used. This will be described with reference to FIGS. In this embodiment, a significant effect can be expected by providing a sense latch circuit that latches temporary data at the time of output and adopting the serial access method.

  For example, in the serial access method, a timing chart as shown in FIG. 13 is obtained, and data is output as shown in FIGS. 14A and 14B showing a partial outline of the memory matrix Memory Matrix. That is, when the chip enable signal / CE, the output enable signal / OE, and the write enable signal / WE are activated and the address signal Address is input after the data input command Din is input, in synchronization with the serial clock signal SC, The address signal is sequentially incremented or decremented, and for example, 512-bit data Data from 0 to 511 bits is sequentially output.

  In this case, in the memory matrix Memory Matrix, one word line WLi is designated as shown in FIG. 14A, and further, the data line DLj is designated in order, whereby the memory cell connected to the word line WLi and the bit line BLj. Are sequentially selected and data is taken into the sense latch circuit. The data fetched into the sense latch circuit is sequentially output through the main amplifier as shown in FIG. 14B. For example, the time twsc from when the address signal Address is input to when the first data is output can be 1 μs, and the time tscc when one data is output can be 50 ns, which enables high-speed data reading. .

  On the other hand, in the random access method, a timing chart as shown in FIG. 15 is obtained, and data is output as shown in FIG. 16 showing a partial outline of the memory matrix Memory Matrix. That is, when the first address signal Address is input, in the memory matrix Memory Matrix, one word line WLi and one bit line BLj are designated, and memory cells connected to the word line WLi and the bit line BLj are stored. Selected. The data of the selected memory cell is output through a sense amplifier. Similarly, for the next address signal Address, the data of the memory cell selected by the word line WLi and the bit line BLj can be output after time tacc from the input of the address signal Address.

  The memory cell is not particularly limited, and has a configuration similar to, for example, an EPROM memory cell, and is a known memory cell having a control gate and a floating gate, or a control gate, a floating gate, and a selection gate. This is a known memory cell. Here, the structure of a memory cell having a control gate and a floating gate will be described with reference to FIG.

  In FIG. 5, this nonvolatile memory cell is, for example, International Electron Devices Meeting Tech. Dig. pp. It is the same structure as the transistor of the memory cell of the Ferrasch memory announced in 560-563. The memory cell is not particularly limited, but is formed on a semiconductor substrate made of single crystal P-type silicon, for example.

  That is, this nonvolatile memory cell includes a control gate electrode 1, a drain electrode 2, a source electrode 3, a floating gate 4, an interlayer insulating film 5, a tunnel insulating film 6, a P-type substrate 7, a drain / source as shown in FIG. One flash erasing is performed by one transistor element composed of high impurity concentration N type diffusion layers 8 and 9 in the region, low impurity concentration N type diffusion layer 10 on the drain side, and low impurity concentration P type diffusion layer 11 on the source side. A type EEPROM cell is constructed.

  Various examples of connection have been proposed for the memory cell group for connecting a plurality of these memory cells, and there are no particular restrictions. For example, a NOR type, a DINOR type, as shown in FIGS. There are AND type, HICR type, etc., which will be described in order below.

  FIG. 17 shows an example in which memory cells are connected in a NOR type, and word lines W1,..., Wm, bit lines B1,. A (write, erase) operation or a read operation is performed. That is, the word lines W1,..., Wm are connected to the gate of the MOS transistor, the bit lines B1,..., Bn are connected to the drain of the MOS transistor, and the Source Line is connected to the source of the MOS transistor.

  FIG. 18 is a connection example of a DINOR type memory cell, in which Select Gate and Sub Bit Line are added, the source of the MOS transistor of Select Gate is connected to bit lines B1,..., Bn, and the drain of this MOS transistor is It is connected to the drain of the MOS transistor of each memory cell through the Sub Bit Line.

  FIG. 19 shows an example of connection by AND type, which has Select Gate 1 and Select Gate 2 and Sub Source Line, and the source of the MOS transistor of Select Gate 1 is connected to bit lines B1,. The drain of this MOS transistor is connected to the drain of the MOS transistor of each memory cell through the Sub Bit Line. The source of the MOS transistor of Select Gate 2 is connected to the Source Line, and the drain of this MOS transistor is connected to the source of the MOS transistor of each memory cell through the Sub Source Line.

  FIG. 20 shows an example of connection of memory cells of the HICR type. The source of the MOS transistor of Select Gate 1 is connected to the bit lines B1,..., Bn, and the drain of this MOS transistor is connected to each memory cell through the Sub Bit Line. It is connected to the drain of the MOS transistor. The source of the MOS transistor of Select Gate 2 is connected to the Source Line, and the drain of this MOS transistor is connected to the source of the MOS transistor of each memory cell through the Sub Source Line.

  An operation for selectively raising or lowering the threshold voltage of the memory cell, that is, a rewriting operation method, will be described with reference to cross-sectional schematic diagrams of the memory cell and terminal applied voltages in FIGS. 6A, 6B, 7A, and 7B.

  6A and 6B show the operation of selectively reducing the threshold voltage of the memory cell. 6A and 6B are memory cells in which the respective control gates are connected to a common word line, and the terminal application voltage in FIG. 6A shows the terminal application voltage when lowering the threshold voltage of the memory cell. 6B shows the terminal applied voltage when the threshold voltage of the memory cell is held. A negative voltage of about −10 V, for example, is applied to the word line to which the control gates of FIGS. 6A and 6B are connected in common, and a voltage of about 5 V, for example, is selectively applied to the drain terminal of the memory cell of FIG. 6A. As a result, a voltage difference is generated between the floating gate and the drain, and electrons in the floating gate are extracted to the drought-in side by the Fowler-Nordheim tunnel phenomenon. By applying 0 V to the drain terminal of the memory cell of FIG. 6B, the voltage difference between the floating gate and the train is reduced, and emission of electrons in the floating gate is prevented.

  In the operation of lowering the threshold voltage of the memory cell, a positive voltage is applied to the voltage of the non-selected word line to prevent disturbance (electron discharge) due to the drain voltage. Therefore, in the rewriting operation, the source electrode is set to open to prevent a steady current from flowing.

  7A and 7B show the operation of selectively raising the threshold voltage of the memory cell. 7A and 7B are memory cells in which the respective control gates are connected to a common word line, and the terminal application voltage in FIG. 7A shows the terminal application voltage when raising the threshold voltage of the memory cell. 7B shows the terminal applied voltage when the threshold voltage of the memory cell is held. By applying a high voltage of about 16 V, for example, to the word lines to which the control gates of FIGS. 7A and 7B are commonly connected, and selectively applying a voltage of, for example, 0 V to the drain terminal of the memory cell of FIG. A voltage difference occurs between the floating gate and the channel, and electrons in the channel are injected into the floating gate by the Fowler-Nordheim tunneling phenomenon. By applying a voltage of about 8 V, for example, to the drain terminal of the memory cell in FIG. 7B, the voltage difference between the floating gate and the channel is reduced, and injection of electrons into the floating gate is prevented.

  It is also possible to lower the control gate, that is, the word line voltage, by setting the drain voltage, that is, the channel voltage in the operation of raising the threshold voltage of the memory cell as a negative voltage.

  As is clear from FIGS. 6A, 6B, and FIGS. 7A, 7B, the threshold voltage of the memory cell can be selectively rewritten by selectively controlling the voltage value applied to the drain terminal of the memory cell. In order to selectively control the voltage value applied to the drain terminal of the memory cell, as described later, a sense latch circuit having a flip-flop is connected to each bit line to which the drain terminal of the memory cell is connected. What is necessary is just to give the data regarding the voltage information of a drain terminal to a circuit.

  An outline of the connection between the memory mat Memory Mat and the sense latch circuit SL of this embodiment will be described with reference to FIGS. The present embodiment is characterized in that one sense latch circuit SL is provided for each of the bit lines B1 to Bn. For example, as shown in FIG. 21, the sense latch circuits SL1 to SLn are connected to the memory mats Memory Mat, b bit lines Ba1 to Ban, Bb1 to Bbn are arranged in an open bit line system, and two sense latch circuits SL are provided in two bit lines B1 to Bn as shown in FIG. Deploy.

  Next, a detailed circuit diagram of the sense latch circuit SL will be described. FIG. 23 shows a circuit diagram of the sense latch circuit SL when the connection between the memory mat Memory Mat and the sense latch circuit SL is arranged by the open bit line system of FIG.

  In the sense latch circuit SL shown in FIG. 23, a sense latch circuit SL including a flip-flop is connected to the bit lines Ban and Bbn, and the bit lines Ban and Ban and Bbn−1 and Bbn are identical ( Equivalent) connection configuration. Further, the sense latch circuit SL divides the control signal for the even / odd bit lines, and has the same (equivalent) connection configuration to the bit lines Ban-1 and Bbn. This is to prevent the parasitic line capacitance of the bit line from affecting the sensing operation. For example, during the sensing operation of the memory cell connected to the even bit line side (hereinafter referred to as the even side), the odd bit Even-side memory cells are read with the potential on the line side (hereinafter referred to as odd side) set to Vss and the capacitance between the parasitic lines is a constant value.

  The bit line Ba1 of the memory mat will be described as an example. The bit line Ba1 includes a MOS transistor M1 that receives a gate signal BDeu that discharges the potential of the bit line to the ground voltage Vss, and the potential of the bit line. A MOS transistor M2 that receives a gate signal RCeu that performs precharging and a MOS transistor M3 that uses the precharge signal PCeu as a gate are connected via a MOS transistor M4 that receives flip-flop information as a gate input signal.

  The connection between M3 and M4 is not limited, and the power supply voltage Vcc side may be M3 and the bit line side may be M4. Between the bit line Ba1 and the flip-flop side wiring Ba1f, a MOS transistor M5 that receives the gate signal TReu is connected.

  The flip-flop wiring Ba1f receives the MOS transistor M6 that receives the gate signal RSLeu for discharging the potential of the flip-flop to the ground voltage Vss, and the column gate signal Yadd corresponding to the column address, and the flip-flop information is stored in the data. It is connected to a MOS transistor M7 that performs output and a MOS transistor M8 that uses a gate input signal as information of a flip-flop. The drain of the MOS transistor M8 is the common signal ALeu, the source is the ground voltage Vss, and multi-stage input NOR circuit connection is established. That is, the MOS transistor determines that the information of all the connected flip-flops is the ground voltage Vss.

  The basic configuration of the semiconductor nonvolatile memory device of this embodiment has been described above. Next, the operation (write operation) sequence for reducing the threshold voltage, which is a feature of this embodiment, is shown in FIG. 1 to FIG. The sequence will be described.

  Note that the operation sequence shown in FIGS. 1 to 4 for lowering the threshold voltage can be applied to the erase sequence.

  The operation sequence of the first embodiment of the present embodiment is shown in FIG. In this embodiment, after the A sequence, that is, the operation sequence of FIG. 29 described above, the B sequence, that is, the memory cell data is read and the memory cell (hereinafter referred to as a low threshold memory) is overwritten by a predetermined level or more. A low threshold verify operation for checking whether or not there is a cell is performed, and an operation for selectively returning the threshold voltage of a memory cell having a low threshold voltage (selective return operation) has been added.

  The B sequence will be described in detail with reference to FIG. 31A. The word line potential during the low threshold verify operation is set to a voltage such that the threshold voltage of the memory cell does not become negative, for example, the ground voltage Vss. When a word line connected to a low threshold memory cell having a threshold voltage of Vss or less is selected, a current flows, so that the presence or absence of the low threshold memory cell can be confirmed. If a low-threshold memory cell exists, the unit return time is set and the threshold voltage of the low-threshold memory cell is operated once by the Fowler-Nordheim tunnel phenomenon shown in FIG. To selectively return the threshold value to Vss or higher.

  The operation sequence of the second embodiment of the present embodiment is shown in FIG. In the first embodiment, the selective return operation is performed by one operation, whereas in the second embodiment, the C sequence in which the low threshold verify operation and the selective return operation are performed in a plurality of times is performed as an A sequence. After that. While the C sequence is repeated, the memory cell whose threshold voltage has returned, that is, the memory cell that has ceased to have a low threshold, is excluded from the operation target of the C sequence, and an unnecessary selection return operation is performed. Set to not.

  Note that the word line voltage at the time of low threshold verification performed first in the C sequence and the word line voltage at the time of low threshold verification repeatedly performed after the second time do not need to match. For example, the word line voltage at the time of the first low threshold verification is set to the ground voltage Vss, the depleted memory cell as in the above B sequence is determined, the unit return time is set, and the low threshold is set. The threshold voltage of the memory cell is selectively returned to the threshold value of Vss or more in one operation, and the word line voltage at the time of low threshold verification repeatedly performed after the second time is as shown in FIG. 31B. For example, the threshold voltage of the memory cell may be returned to 0.5 V or higher by setting it to 0.5 V.

  The operation sequence of the third embodiment of the present embodiment is shown in FIG. In the third embodiment, after performing a low threshold verify operation and a selective return operation, it is confirmed whether or not there is a memory cell (hereinafter referred to as a high threshold memory cell) in which writing has not reached a predetermined level. A high threshold verify operation is performed, and if there is a high threshold memory cell, a threshold voltage selective write operation (hereinafter referred to as reselective write) is performed on the memory cell. Since the operation of lowering the threshold voltage is performed between the selective return operation and the reselective write operation, a re-data input verify operation is necessary. This is for distinguishing between those having the threshold voltage and those having the threshold voltage slightly changed.

  For example, a voltage of about 2 V is applied as the word line voltage for re-data input verification, and the write data is latched in the flip-flop. As will be described later, a memory cell to be reselected is determined according to the write data and the result of the high threshold verify operation. For example, a voltage of about 1.5 V is applied to the word line voltage during the high threshold verify operation, so that the threshold voltage of the write target cell is 1.5 V or less. The reselective write operation can be realized by the same sequence as the write operation.

  By this sequence, the threshold voltage level in the write state can be kept between the word line voltage 0.5V at the time of low threshold verification and the word line voltage 1.5V at the time of high threshold verification.

  FIG. 4 shows an operation sequence of the fourth embodiment of the present embodiment. The operation sequence of the fourth embodiment is an operation sequence in which the C sequence and D sequence, that is, the selective return operation and the reselective write operation are repeated a predetermined number of times.

  Hereinafter, the above-described A, B, C, and D sequences will be described in further detail.

  The data of the flip-flops in the sense latch circuit SL when performing the A, B, C, and D sequences shown in FIGS. 1 to 4 of this embodiment are shown in FIGS. 8, 9, 10, and 11, respectively. 24, 25, 26, and 27 are timing waveform diagrams of internal signals in the sense latch circuit SL of FIG. 23 when performing the A, B, C, and D sequences. The data “0” of the flip-flop described in FIGS. 8 to 11 is defined as a state in which the threshold voltage of the memory cell to which the flip-flop is connected is high (erased state). The voltage Vss. The flip-flop data “1” is defined as a state in which the threshold voltage of the memory cell is low (write state), and the flip-flop data is, for example, the external power supply voltage Vcc. Write drain terminal voltage Vwd, selective return unselected channel / drain voltage Vpc, and reselective write drain terminal voltage Vsd.

  The timing waveform diagrams of FIGS. 24 to 27 are waveform diagrams (on the target memory mat Memory Mat side) in which the memory cell group (sector) on the memory mat Memory Mat side is selected, and the solid line waveforms are subscripts in FIG. The waveform of the control signal with u added to it, and the broken line waveform is the waveform of the control signal with the suffix d in FIG.

  First, the write operation sequence (A sequence) will be described with reference to FIG. A memory in which a flip-flop in a sense latch circuit connected to a memory cell holding a high threshold value (erased state) via a bit line is set to “0” and rewritten to a low threshold value (write) Data in which the flip-flop connected to the cell via the bit line is set to “1” is input, and then electrons in the floating gate are extracted by the drain edge Fowler-Nordheim tunnel phenomenon shown in FIG. In the verification, the voltage of the selected word line is set to 1.5 V, and only the bit line corresponding to the flip-flop data “1” is selectively precharged. In a memory cell that has reached the write threshold voltage level, that is, the word line voltage of 1.5 V at the time of verification, a cell current flows and becomes Pass, and the bit line potential is discharged. Accordingly, the flip-flop data is rewritten to “0”. In the memory cell that has not reached 1.5V, the cell current does not flow and becomes Fail, the potential of the bit line maintains the precharged voltage, and the data of the flip-flop maintains “1”. The data in the flip-flop after the verification is used as rewrite data, and the write and verify operations are repeated. When all the data in the flip-flop becomes “0”, the write operation is completed. This collective determination is automatically performed in the chip.

  FIG. 24 shows a timing waveform diagram of internal signals in the sense latch circuit SL in the write operation sequence (A sequence).

  Write data is input to the flip-flop in the sense latch circuit SL by t1, and the data is written between t1 and t5, the verify on the even side from t5 to t9, the verify on the odd side from t9 to t11, and from t11 During t13, the end of all bits of the memory cell threshold voltage is determined. As described above, the write data input up to t1 is the data of the flip-flops connected to the bit lines B1,..., Bn corresponding to the memory cells for which the threshold voltage of the memory cells is to be selectively lowered is set to the high level. The data for which the threshold voltage is not desired to be lowered is defined as the ground voltage Vss.

  By selecting PCeu and PCou between t1 and t2, the flip-flop data is selectively transmitted to the bit lines B1,..., Bn. Thereafter, during the period from t2 to t4, TReu and TRou are selected to supply the write drain voltage.

  PCeu and PCou are selected before selecting TReu and TRou. When only TReu and TRou are selected, the capacity of bit lines B1,..., Bn is larger than the capacity of flip-flops B1f,. This is because the data of the group is destroyed. The reason why the potentials of TReu, TRou and SG1a / b are set to 6V is to transfer the drain voltage 5V (VSpe and VSPo) at the time of writing. When the drain voltage is increased, the TReu, TRou and gate signal SG1a / b are increased. The gate potentials of TReu, TRou and SG1a / b are set in consideration of the threshold voltage of the MOS transistor of the drain side Select Gate 1 of b. SG1a / b is selected (t3) after the potential of the selected word line voltage Wa is lowered (t2) because the delay time of the word line is longer than that of the drain side Select Gate 1. The net write time is between t3 and t4. By setting the word line to a negative voltage of −10V, the bit line voltage is selectively set to 5V to generate an electric field at the floating gate of the desired memory cell, Is released.

  Between t4 and t5, the BDeu / d, BDou / d, and drain side Select are used to discharge the potential of the bit lines B1,..., Bn and the sub bit line Sub Bit Line and the sub source line Sub Source Line to the ground voltage Vss. The gate signal SG1a / b of Gate 1 and the gate signal SG2a / b of the source side Select Gate 2 are selected.

  Between t5 and t6, PCeu and RCed are selected in order to selectively precharge the bit line by the flip-flop data and to supply the reference potential to the bit line of the non-selected memory mat. Considering the threshold voltage of the MOS transistor, when the precharge potential is 1.0 V, the PCeu potential is 2.0 V, and when the reference potential is 0.5 V, the RCed The potential is 1.5V.

  Until t6, the internal power supply voltages VSPe / o and VSNe / o are activated in order to hold the flip-flop data. From t5 to t10, the selected word line potential is the verify voltage of 1.5V.

  The discharge time of the memory cell at the time of even-side verification is from the selection of the gate signal SG2a of the source-side Select Gate 2 at t6 to the deactivation of the gate signal SG1a of the drain-side Select Gate 1 at t7. Is reset by the activation of the RSLeu / d signal. Thereafter, TReu / d is selected between t7 and t8, and the power supply voltages VSPe and VSNe of the even-side flip-flop are activated again, whereby the memory cell information after verification is taken into the even-side flip-flop. Can do. That is, the potential of the bit line is kept in the discharged state or the precharge voltage due to the low or high threshold voltage of the memory cell.

  During the period from t8 to t9, the potential of the bit line Bn-1 and the sub bit line Sub Bit Line and the sub source line Sub Source Line at the time of the even side verification are discharged to the ground voltage Vss.

  Next, the odd-side verify operation is performed between t9 and t10 in the same manner as the even-side verify. Thereafter, the end of all bits of the memory cell threshold voltage is determined between T11 and t13. If the threshold voltages of all the memory cells are lowered, the flip-flop data is the ground voltage Vss, and this Vss is determined. After activating ALeu and ALou (between t11 and t12), the potential is verified. If the ground voltage is Vss, the operation is repeated to t1 to continue the write operation. If ALeu and ALou are at a high level, the write operation is terminated.

  FIG. 9 shows the data of the flip-flop in the sense latch circuit in the B sequence. After the conventional write operation (A sequence) is completed, the above-described low threshold verify operation is performed on all the memory cells connected to the word line to be written. The word line voltage during the low threshold verify operation is, for example, the ground voltage Vss, and precharge is performed for all bits. In the bit (depletion bit) whose threshold voltage is lower than the verify word line voltage, the cell current flows, the flip-flop data becomes “0”, and in the bit for which the threshold voltage is secured, the precharge voltage is set. Maintained to be “1”. Thereafter, the data of the flip-flop is determined. If all the data is “1”, the operation is terminated, and even one bit is “0”, that is, a bit whose threshold voltage is lower than the word line voltage at the time of low threshold verification. If (depletion bit) exists, the selection return operation is performed. The potential of the word line to be written is set to a high voltage, for example 16V, the channel of the memory cell selected by the flip-flop data is set to the ground voltage Vss, and the channel / drain voltage Vpc of the non-selected memory cell is set to 8V, for example Performs selection return operation.

  FIG. 25 shows timing waveforms of internal signals in the sense latch circuit SL in the B sequence. Between t1 and t3, a low threshold verify operation is performed on the even side and odd side between t3 and t4, and it is determined whether or not a selective return operation is performed between t4 and t5. Between t6 and t9 Select return operation with.

  The difference from the verify operation in the A sequence described in FIG. 24 is the verify operation for all bits. Therefore, the precharge voltage and the reference voltage of the bit line between t1 and t2 are supplied, and the RCeu potential is set. This is because the potential of 2.0V and RCed is set to 1.5V.

  In the selective return operation, first, PCeu and PCou are activated between t5 and t6, and the flip-flop data is transmitted to the bit line. Thereafter, the selection return operation can be performed by activating the signal line in the same manner as the write operation. However, the word line voltage Vpw at the time of the selective return operation is a high voltage of 16 V, for example, and the power supply voltage VSPe / o of the flip-flop is a non-selected channel / drain voltage Vpc at the time of selective return, for example, a voltage of 8 V, Further, the potentials of the gate signals TReu / d, TROu / d and SG1u / d of the MOS transistor for transferring the drain voltage are set to the transfer gate voltage Vpt at the time of selective return, for example, 9V.

  FIG. 10 shows data of flip-flops in the sense latch circuit in the C sequence. After completion of the conventional write operation (A sequence), the low threshold voltage verification of the memory cell connected to the word line to be written is performed in the same manner as in FIG. 9, and the bit having the low threshold voltage (depletion bit) If exists, the selection return operation is performed. Thereafter, the low threshold verify operation is performed again at the voltage at which the threshold voltage is to be returned. For example, if the low threshold verify word line voltage is 0.5V, the threshold voltage of the memory cell can be 0.5V or higher.

  In the low threshold verification performed again, the case where the voltage of the selected word line is set to 0.5V will be described. First, all the bit lines are precharged. In a memory cell that has not reached the selected return threshold voltage level, that is, the verify word line voltage of 0.5 V, a cell current flows and becomes Fail, discharging the bit line potential. Therefore, the data of the flip-flop holds “0”. On the other hand, in the memory cell that has reached 0.5 V, the cell current does not flow and becomes Pass, the potential of the bit line is maintained at the precharged voltage, and is rewritten to “1” of the flip-flop data. The flip-flop data after the verification is used as reselection return data, and the selection return and the low threshold verification operation are repeated. The operation ends when all the data in the flip-flop becomes “1”. This collective determination is automatically performed in the chip.

  FIG. 26 shows timing waveforms of internal signals in the sense latch circuit SL during the C sequence.

  Whether flip-flop data is set between t1 and t2, low side verify operation is performed between t2 and t8, odd side between t8 and t9, and selective return operation between t9 and t10 The selection return operation is performed between t10 and t11.

  From t1 to t2, the non-selected RSLed and RSLod are selected and the flip-flop power supply voltages VSPe / o and VSNe / o are activated to set the flip-flop data to all bit selection.

  From t2 to t3, the RCeu voltage is set to 2.0V and the RCed voltage is set to 1.5V in order to supply the precharge potential to all the selected bit lines and the reference potential to the bit lines of the non-selected memory mats. To do. The discharge time of the memory cell at the time of even-side verification is from the selection of the gate signal SG2a of the source side Select Gate 2 at t3 to the inactivation of the gate signal SG1a of the drain side Select Gate 1 at t4.

  PCeu / d is selected between t4 and t5, and the flip-flop data is transmitted to the bit line. Thereafter, the flip-flop reset operation is performed between t5 and t6, TReu / d is selected between t6 and t7, and the power supply voltages VSPe and VSNe of the even-side flip-flop are activated again, so that The memory cell information can be taken into the even flip-flop.

  Next, the odd-side verify operation is performed between t8 and t9 in the same manner as the even-side verify. Thereafter, it is determined whether or not the threshold voltage of the memory cell has returned to a predetermined voltage or higher between t9 and t10. If the threshold voltages of all the memory cells are returned, the data of the flip-flop becomes the potential (High level) of the power supply voltage VSPe / o. Therefore, the threshold voltage of the memory cell is determined by the data of the flip-flop. It can be carried out. Verification of the flip-flop data is performed by activating ALed and ALod on the non-selected side. When the flip-flop data is the ground voltage Vss, a selective return operation from t10 is performed. As a result, when the flip-flop data becomes High level, the operation is terminated. The selection return operation is performed in the same manner as in FIG. After t11 when the selection return operation is completed, the operation sequence is continued by returning to t2.

  FIG. 11 shows flip-flop data in the D sequence. For example, a voltage of about 2V is applied as the word line voltage for re-data input verification, the write data is latched in the flip-flop, and a word line voltage of about 1.5V is applied during the high threshold verification. The threshold voltage of the memory cell to be written is set to 1.5 V or lower.

  The data of the flip-flop for the reselective write operation is the same as the data of the flip-flop for write described with reference to FIG.

  FIG. 27 shows timing waveforms of internal signals in the sense latch circuit SL during the D sequence. The timing waveform diagram which operates circuit SL is shown.

  A re-data input verify operation with a verify word line voltage of 2V is performed between t1 and t3, a high threshold verify operation with a verify word line voltage of 1.5V is performed between t3 and t4, and a re-select write operation between t5 and t6 It is determined whether or not to perform the reselection write operation between t6 and t7. After the end of t7, the operation sequence returns to t2 and continues.

  FIG. 32 shows voltages applied to the terminals of the memory cells when the A, B, C, and D sequences are executed and during read, erase, and erase verify.

  Although specific description has been given based on the embodiments, the present invention is not limited to the above-described embodiments, and needless to say, various modifications can be made without departing from the scope of the invention.

  For example, the semiconductor nonvolatile memory device of this embodiment has been described as applied to a flash memory (EEPROM). However, the present invention is not limited to the above embodiment, and is electrically connected to an EEPROM, an EPROM, or the like. The present invention can be widely applied to other rewritable nonvolatile storage devices.

  Further, in the semiconductor nonvolatile memory device of the present embodiment, it is not limited to the case where it is used as a flash memory in units of storage devices, but as a storage device for various systems such as a computer system, a digital still camera system, and an automobile system. As an example, a computer system will be described with reference to FIG.

  In FIG. 28, this computer system includes a central processing unit CPU as an information device, an I / O bus built in the information processing system, a bus unit, a memory control unit Memory that accesses high-speed memory such as main memory and expansion memory. A control unit, a DRAM as a main storage memory, a ROM storing a basic control program, a keyboard controller KBDC having a keyboard connected to the tip, and the like. Further, a display adapter as a display adapter is connected to the I / O bus, and a display display is connected to the tip of the display adapter.

  The I / O bus is converted into a parallel port Parallel Port I / F, a serial port I / F such as a mouse, a floppy disk drive FDD, and an HDD I / F from the I / O bus. The buffer controller HDD Buffer to be connected is connected. Further, an expansion RAM and a DRAM as a main memory are connected to a bus from the memory control unit Memory Control Unit.

  Here, the operation of this computer system will be described. When the power is turned on and the operation is started, the central processing unit CPU first accesses the ROM through the I / O bus to perform initial diagnosis and initial setting. Then, the system program is loaded from the auxiliary storage device into the DRAM as the main storage memory. The central processing unit CPU operates as an HDD accessing the HDD controller through the I / O bus.

  When the loading of the system program is completed, the process proceeds according to the user's processing request. Note that the user proceeds with input / output of processing by the keyboard controller KBDC and the display adapter Display Adapter on the I / O bus. Then, an input / output device connected to the parallel port Parallel Port I / F and the serial port Serial Port I / F is utilized as necessary.

  Further, when the main memory capacity is insufficient in the DRAM as the main memory on the main body, the main memory is supplemented by the expansion RAM. When the user wants to read or write a file, the user requests access to the auxiliary storage device on the assumption that the HDD is an auxiliary storage device. In response to this, the flash file system constituted by the flash memory of the present invention accesses the file data.

  As described above, the semiconductor nonvolatile memory device such as the flash memory of the embodiment can be widely applied as a flash file system of a computer system.

  Further, the embodiment of the ground will be described with reference to FIGS.

  FIG. 33 is a schematic diagram of a memory mat representing the concept of the embodiment of the present invention. FIGS. 34A and 34B are cross-sectional views showing transistors of a conventional semiconductor nonvolatile memory cell and a diagram showing an example of voltage application in an erase operation. 35 and 36A, 36B, and 36C are diagrams showing examples of voltage application to selected and non-selected memory cells in the erase operation of this embodiment. FIG. 37 is a functional block diagram showing a semiconductor nonvolatile memory device of the present invention. 38 is a circuit diagram showing the sense latch circuit of the present invention, FIG. 39 is a circuit diagram showing the memory mat of the present invention, FIG. 40 is a functional block diagram for generating a voltage supplied to the memory mat, and FIGS. 41 and 42 Is a circuit diagram of a memory well voltage switching circuit and a row decoder circuit, FIGS. 43 to 47 are waveform diagrams showing timings of an erase operation, and FIG. 48 is a semiconductor nonvolatile memory of this embodiment. It is a functional block diagram of a computer system using a location.

  First, the configuration of the semiconductor nonvolatile memory device of this embodiment will be described with reference to FIG. The semiconductor nonvolatile memory device according to the present embodiment is a flash memory including, for example, a plurality of memory mats composed of transistors whose threshold voltages can be electrically rewritten, and includes a memory mat and a memory mat well voltage. Switching circuit MWVC, row address buffer circuit XADB, row address decoder circuit XDCR, sense latch circuit SL and column gate array circuit YG shared by sense amplifier and data latch, column address buffer circuit YADB, column address data circuit YDCR, input buffer circuit DIB , An output buffer circuit DOB, a multiplexer circuit MP, a mode control circuit MC, a control signal buffer circuit CSB, a built-in power supply circuit VS, and the like.

  As for the connection between the memory mat of this embodiment and the sense latch circuit SL, one sense latch circuit SL is provided for one of the bit lines B1 to Bn. For example, as shown in FIGS. SL1 to SLn are arranged in an open bit line system with respect to the bit lines Bu1 to Bun and Bu1 to Bun of the memory mat u and d.

  In the semiconductor nonvolatile memory device of FIG. 37, the control signal buffer circuit CSB is not particularly limited, but for example, a chip enable signal supplied to the external terminals / CE, / OE, / WE, SC, etc. A timing enable signal, a write enable signal, a serial clock signal, and the like are input, and a timing signal of an internal control signal is generated in response to these signals, and the mode control circuit MC receives a ready / read signal from an external terminal R / (/ B). A busy signal is input.

  In this embodiment, “/” such as / CE, / OE, / WE represents a complementary signal.

  Further, in the built-in power supply circuit VS, although not particularly limited, for example, the power supply voltage Vcc and the ground voltage Vss are inputted from the outside, and the word line voltage Vh at the time of erasing (raising the threshold voltage), Verify word line voltage Vhv, word line voltage Vl during write (lower threshold voltage) operation, verify word line voltage Vlv, memory well voltage Vmw during erase operation, read bit line voltage Vrb, read reference bit line voltage Vrr, drain terminal voltage Vld at the time of write operation, transfer gate voltage Vlt, and the like are generated. The suffix of the voltage name is the same as the suffix u / d of the supplied memory mat. The above voltages may be supplied from the outside.

  The voltages generated here include word line voltages Vh, Vhv, Vl, Vlv and transfer gate voltage Vlt as row address decoder circuit XDCR, and bit line voltages Vrb, Vrr, Vld and transfer gate voltage Vlt as sense latch circuit SL. The memory well voltage Vmw is input to the memory mat well voltage switching circuit MWVC, the row address decoder XDCR circuit, and the sense latch circuit SL.

  In this semiconductor nonvolatile memory device, a row supplied from an external terminal, a row receiving column address signals AX, AY, a complementary address signal formed through column address buffer circuits XADB, YADB are row, column address decoder circuits XDCR, Supplied to YDCR. Although not particularly limited, for example, the row and column address buffer circuits XADB and YADB are activated by a chip enable selection signal / CE inside the device, and take in address signals AX and AY from external terminals, A complementary address signal composed of an internal address signal in phase with the address signal supplied from the terminal and an address signal in reverse phase is formed.

  The row address decoder circuit XDCR forms a selection signal for the word line W of the memory cell group according to the complementary address signal of the row address buffer XADB, and the column address decoder circuit YDCR follows the complementary address signal of the column address buffer circuit YADB. A selection signal for the bit line B of the memory cell group is formed. Thereby, an arbitrary word line W and bit line B are designated in the memory mat and a desired memory cell is selected.

  Although not particularly limited, for example, memory cells are selected by 8 or 16 bit memory cells by row address decoder circuit XDCR and column address decoder circuit YDCR in order to perform writing or reading in units of 8 bits or 16 bits. A piece or the like is selected. If the number of memory cells in one data block is m in the word line direction (row direction) and n in the bit line direction (column direction), there are 8 or 16 data blocks in the m × n memory cell group. Consists of

  The memory cell is not particularly limited, and has a configuration similar to, for example, an EPROM memory cell, and is a known memory cell having a control gate and a floating gate, or a control gate, a floating gate, and a selection gate. This is a known memory cell.

  As an example, 64M bits of 512 bytes (1 byte = 8 bits), a memory mat has a 2-mat configuration as shown in FIG. 37, and a unit block j has 64 bits.

  In the AND type memory connection of FIG. 19, each bit line Bn (B1 to B4096) includes a unit block in which j = 64 plural memory cells are connected in parallel and one mat i = 128 memory cells. They are connected via a selection MOS transistor that receives a gate signal SiD. A common source line (Source Line) is connected to a sub source line (Sub Source Line) for each unit block via a selection MOS transistor that receives a gate signal SiS.

  The erase operation of the present invention will be described below. 35 and 36A, 36B, and 36C are memory cell cross-sectional views showing voltage application examples of selected and non-selected memory cells that are the erasing operation of the present invention. The memory cells shown in FIGS. 35 and 36A, 36B, and 36C are formed in the well DP well in the element isolation layer niso region for isolation from the substrate p-sub of the memory device. The voltage of the substrate p-sub is the same ground voltage Vss as in the past, and there is no particular limitation. However, the voltage of the element isolation layer niso is higher than the source and drain terminal voltages, for example, the power supply voltage Vcc and the ground voltage Vss. Supply. In the present invention, the voltage of the element isolation layer niso is the power supply voltage Vcc.

  As for the voltage of the erase operation of the selected memory cell in FIG. A voltage difference occurs between the floating gate and the channel, and electrons in the channel are injected into the floating gate by the Fowler-Nordheim tunnel phenomenon. Note that the drain electrode of the memory cell is open to prevent a steady current from flowing through the memory cell.

  By setting the channel voltage to −4V, the erase operation can be performed in the same time (about 1 ms) as the conventional erase time even when the word line voltage is 12V.

  Thereby, the threshold voltage of the memory cell at the time of erasing can be set to the upper limit voltage Vccmax of the power supply voltage Vcc which is the selected word line voltage at the time of reading.

  In the erasing operation, erasing is performed by repeatedly applying an erasing pulse divided into several times, and an operation (verification) for verifying the threshold voltage of the memory cell is performed every time after erasing. The word line voltage for erase verification is set to about 4.2V.

  36A, 36B, and 36C show voltage application methods for unselected memory cells.

In the system of FIG. 36A, the control gate is set to 0 V, the well DP well and the source terminal are set to −4 V, and the drain terminal is open. Unselected memory cells are disturbed by a channel voltage of -4V. The disturbance applied voltage is the same as the voltage application in which the word line disturbance during reading is reversed. The selected word line voltage at the time of reading is Vcc as a power supply voltage, the maximum voltage Vccmax is 3.6 V, and 3.9 V is a general guarantee voltage, and the guarantee time is 10 years (3 × 10 ⁸ seconds). It is.

Now, taking 512 Mbytes (1 byte = 8 bits) as an example, the time for receiving erase disturbance is calculated. When the memory mat configuration is an open bit line system for the sense latch circuit SL as shown in FIG. 8 and the like, the memory mat is divided into two. The number of bits of memory cells connected to the same bit line on the same memory mat is 8k bits (1k = 1024). For example, the number of parallel bits j that is a unit block is 64 bits, the maximum erase time is 10ms, and rewriting is performed. When the number of times is 10 ⁶ times, the memory cell of the non-selected sector of the same memory mat having the selected sector receives the erase disturb of 4V corresponding to the word line voltage for 8 × 10 ⁷ seconds.

  Therefore, the voltage value of the erase disturb life is approximately the same as the guaranteed voltage value of the power supply voltage Vcc, and the maximum guaranteed time is within the read guaranteed time.

  36B, the control gate is 0 V, the well DP well is −4 V, the source terminal is open, the drain terminal is 0 V, the control gate voltage and the channel voltage are 0 V of the same potential, and the floating gate of the unselected memory cell It completely prevents the injection of electrons into the inside.

In the system of FIG. 36C, the control gate and well DP well are set to 0 V, the drain terminal and the source terminal are set to 0 V or open, and the control gate voltage and the channel voltage are 0 V of the same potential as in FIG. It completely prevents the injection of electrons into the floating gate. For example, when the memory cells are connected as shown in FIGS. 19 and 20, and the method of FIG. 36B is used for memory cells of unselected sectors in the same block, the erase guarantee maximum guarantee time can be reduced to 6.3 × 10 ⁵ seconds.

  FIG. 33 shows a conceptual diagram of the memory mat of the present invention. Sectors constituting the memory mat of the semiconductor nonvolatile memory device are selected in the erase operation, a positive voltage is applied to the word line (selected sector), the erase is not selected, and the word line voltage and the memory well voltage are different. A sector (unselected sector) and a sector (completely unselected sector) in which erasing is not selected and the word line voltage is equal to the source-drain voltage (channel voltage) of the memory cell are provided.

  Next, FIG. 39 is a circuit diagram of a memory mat in which the connection of the memory cells is the AND type connection shown in FIG. 19, FIG. 40 is a functional block diagram of voltage generation supplied to the memory mat, and FIG. FIG. 41 shows a circuit diagram of the circuit MWVC, and FIG. 42 shows a voltage conversion circuit such as the row decoder circuit XDCR and a driver circuit.

  The built-in power supply circuit VS of FIG. 40 includes a reference voltage generation circuit, a step-down circuit, a step-up pump circuit, a limiter circuit, and a power supply switching circuit, and is controlled by a mode control circuit MC. The write verify word line voltage Vlv (1.5 V) can be generated by using a step-down circuit composed of a current mirror circuit or the like and a reference voltage of a reference voltage generation circuit. Further, 12V of the word line voltage Vh at the time of erasing, −4V of the memory well voltage Vmw, and −9V of the word line voltage Vl at the time of writing are generated by the boost pump circuit and then the reference voltage of the reference voltage generating circuit. The voltage is used for the limiter circuit.

  The memory well power supply switching circuit MWVC shown in FIG. 41 is a circuit that switches the memory well voltage between the ground voltage Vss and the negative voltage −4 V, and the built-in power supply circuit during the erasing operation when the input signal MC1 is low. The -4V power supply voltage in VS is also activated, and the rising waveform of the memory well voltage rises in several to several tens of microseconds depending on the junction capacitance between the memory well DPwell and the element isolation layer niso.

  The voltage conversion circuit and driver circuit shown in FIG. 42 include the word line W, drain, gate signals SiD and SiS of the source side selection MOS transformer, the gate signal BDC of the MOS transistor for discharging the potential of the bit line, and the same well as the memory mat. Are connected to a MOS transistor constituting the sense latch circuit SL, for example, a gate signal TR. This circuit has a voltage higher than the power supply voltage, 12V of the erase word line voltage Vh, 5V of the transfer gate voltage Vlh of the write voltage, and a negative voltage, −4V of the erase well voltage Vmw, and −9V of the write word line voltage Vl. This is a circuit that performs switching.

  Taking the word line W as an example, the source voltage of the PMOS transistors of the voltage conversion circuit and the driver circuit is connected to the power supply voltage Vcc during the write operation and to the erase word line voltage Vh of 12 V during the erase operation. The source voltage of the NMOS transistor in the element isolation layer niso region in the same circuit is connected to the erase well voltage Vmw which is -4V only during the erase operation.

  During the erasing operation, the control signals MC2 and NC are activated to a high level, only the word line W whose address signal is selected high has a voltage of 12V, and the voltage of the non-selected word line has the ground voltage Vss. During the write operation, the control signals MC2 and / NC are activated to high, only the word line W for which the address signal is selected has a voltage of -9V, and the voltage of the unselected word line has the power supply voltage Vcc.

  The word line voltage Vh at the time of erasing rises from the power supply voltage Vcc to 12V after selecting the sector. Due to the word line load capacitance of several pF, the rising waveform rises in several μs to several tens μs. This prevents the MOS transistor from being destroyed by passing through the minimum drain-source breakdown voltage BVdsmin of the MOS transistor when the gate signal as the sector address is switched after the built-in power supply voltage is raised.

  Further, in the semiconductor nonvolatile memory device, the threshold voltage of the memory cell is set by changing the rising waveform of the voltage applied to the word line and the memory well for the sector selected for erasure from several μs to several + μs. Can be prevented from being applied suddenly, and the number of rewrites can be improved.

  43 to 47 show timing waveform diagrams for one erase pulse when the word line W11 is selected in the erase operation. This waveform diagram is based on the circuit diagram of the memory mat shown in FIG. FIG. 43 shows a conventional example, and FIGS. 44 to 47 show erase timing waveforms of the present invention.

  As shown in FIG. 43, the waveform of the selected word line W11 is selected at the timing t1, and rises at the rise of the erase word line voltage Vh. S1D, S1S, and BDCu are set as the power supply voltage Vcc in order to set the drain and source as the channel voltage to the ground voltage Vss of Vmwu. At time t3, the word line is not selected and the activation of the erase word line voltage Vh is finished. A period between t2 and t3 is an erasing time for one pulse.

  FIG. 44 shows a first erase operation timing waveform diagram of the present embodiment. The word line W11 and the memory well of the selected sector are selected at the timing t1, and the Vh and Vmwu voltages are activated. Even if S1D, S1S, SiD, SiS, and BDCu are at Vss, the MOS transistor is in the ON state, so that the channel voltage of the memory cell on the selected sector side is −4 V of Vmwu. In addition, the voltage of TRu is set to −4V to prevent a voltage short circuit with Bunf. At time t4, the word line is not selected, and the activation of the erase word line voltage Vh and the memory well voltage Vmwu is finished. The period from t3 to t4 is the erase time for one pulse.

  FIG. 45 shows a second erase operation timing waveform diagram of the present embodiment. Similarly to FIG. 44, the Vh and Vmwu voltages are raised. In order to make only the same block of the selected sector a disturb sector, the channel voltage in the same block is set to −4V, and the channel voltages of other blocks are set to Vss. TRu is set to BDCu to -4V, Buns Vss supplied from the sense latch side is connected to the bit line Bn, S1S is set to Vss, S1D is set to -4V, channel voltage in the selected block is set to -4V, SiD is set to Vcc, SiS Is −4V and the channel voltage is Vss. At time t4, the word line is not selected, and the activation of the erase word line voltage Vh and the memory well voltage Vmwu is finished. The period from t3 to t4 is the erase time for one pulse.

  46 and 47 show waveforms with the rise of Vh set to t2, and other timings are the same as those in FIGS. 15 and 16. FIG. The time to reach the ultimate potential depends on the current supply capability of the built-in power supply voltage and the load capacity. Therefore, the erase start time is clarified by activating the voltage generation circuit at a timing when the voltage arrival time at the rise of the memory well voltage is equal to the voltage arrival time of the word line voltage.

  Next, the write operation of the memory cell will be described. By applying a negative voltage of, for example, about −9 V to the control gate, that is, the word line during the write operation, and selectively applying a voltage of, for example, about 4 V to the drain terminal of the memory cell for writing, the floating gate is connected to the drain. A voltage difference is generated in the floating gate, and electrons in the floating gate are extracted to the drain side by Fowler-Nordheim tunneling. By applying 0 V to the drain terminal of the non-selected memory cell, a voltage difference between the floating gate and the drain is suppressed, and emission of electrons in the floating gate is prevented.

  Note that the power supply voltage Vcc is applied as the voltage of the unselected word line during the write operation in order to prevent disturbance (electron discharge) due to the drain voltage. Therefore, the source electrode of the memory cell is set to open to prevent a steady current from flowing through the memory cell.

  The threshold voltage of the memory cell at the time of writing must be between the lower limit voltage Vccmin of the power supply voltage Vcc that is the selected word line voltage at the time of reading and 0 V of the ground voltage Vss that is the unselected word line voltage. When the threshold voltage of the non-selected memory cell is lowered to a negative voltage, current flows in the non-selected memory cell, so that erroneous reading is performed. Therefore, a write operation is performed by repeatedly applying a write pulse divided into several times, and an operation for verifying the threshold voltage of the memory cell is performed every time after the write. The word line voltage of the write verify is set to about 1.5V so that the threshold voltage of all the memory cells to be written does not become 0V.

  Note that voltage information applied to the drain terminal of the memory cell described above is stored in a flip-flop in the sense latch circuit connected to the drain terminal via the bit line.

  A circuit diagram of the sense latch circuit SL will be described. FIG. 38 shows a circuit diagram of the sense latch circuit SL when the connection between the memory mat and the sense latch circuit SL is arranged by the open bit line system of FIG.

  In sense latch circuit SL shown in FIG. 38, sense latch circuit SL including a flip-flop is connected to bit lines Bun and Bdn. The bit lines Bun and Bdn have the same (equivalent) connection configuration. Further, the sense latch circuit SL may separately connect control signals to even / odd bit lines. This is to prevent the parasitic line capacitance of the bit line from affecting the sensing operation. For example, during the sensing operation of the memory cell connected to the even bit line side, the potential of the odd bit line is set to Vss. The memory cell on the even bit line side is read with a constant capacitance between the parasitic lines.

  The configuration of the sense latch circuit SL shown in FIG. 38 will be described by taking a bit line Bu1 of a memory mat Memory Matu as an example. The bit line Bu1 is a MOS transistor that receives a gate signal RCu for precharging the potential of the bit line. A MOS transistor M2 having the precharge signal PCu as a gate is connected to M1 through a MOS transistor M3 having the flip-flop information as a gate input signal. The connection between M2 and M3 is not limited, and the power supply voltage Vcc side may be M2 and the bit line side may be M3. A MOS transistor M4 that receives a gate signal TRu is connected between the bit line Bu1 and the flip-flop side wiring Bu1f. In the flip-flop side wiring Bu1f, the MOS transistor M5 that receives the gate signal RSLu that discharges the potential of the flip-flop to the ground voltage Vss and the column gate signal Yadd according to the column address are input, and the information of the flip-flop is output as data The MOS transistor M6 is connected to the MOS transistor M7 that uses the gate input signal as flip-flop information. The drain of the MOS transistor M7 is the common signal ALu, the source is the ground voltage Vss, and a multi-stage input NOR circuit connection is established. That is, it is determined that the information of all connected flip-flops is the ground voltage Vss.

  Further, as shown in the configuration circuit diagram of the memory mat in FIG. 39, the bit line Bun is connected with a MOS transistor that receives a gate signal BDu that discharges the potential of the bit line Bun to the source line voltage. .

  38 and 39, the well of the MOS transistor to which a negative voltage is supplied to at least the source and drain diffusion layers is formed in the same memory well as the memory cell.

  While the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist thereof.

  Further, in the semiconductor nonvolatile memory device of the present embodiment, it is not limited to the case where it is used as a flash memory in units of storage devices, but as a storage device for various systems such as a computer system, a digital still camera system, and an automobile system. As an example, a computer system will be described with reference to FIG.

  As described above, the semiconductor nonvolatile memory device such as the flash memory of this embodiment can be widely applied as a flash file system of a computer system.

  Hereinafter, still another embodiment of the present invention will be described in detail with reference to FIGS. 49-60.

  The configuration of the semiconductor nonvolatile memory device of this embodiment will be described with reference to FIG.

  The semiconductor nonvolatile memory device according to the present embodiment is a flash memory including, for example, a plurality of memory mats including transistors whose threshold voltages can be electrically rewritten, and includes a memory mat Memory Mat, a row address buffer circuit XADB, A row address decoder circuit XDCR, a sense latch circuit SNS and a column gate array circuit YG shared with sense amplifiers and data latches, a column address buffer circuit YADB, a column address decoder circuit YDCR, an input buffer circuit DIB, an output buffer circuit DOB, a multiplexer circuit MP, A mode control circuit MC, a control signal buffer circuit CSB, a built-in power supply circuit VS, and the like are included.

  As for the connection between the memory mat Memory Sense and the sense latch circuit SNS of this embodiment, one sense latch circuit SNS is provided for one of the bit lines B1 to Bn. For example, as shown in FIG. 58, the sense latch circuit SNS1 To SNSn are arranged in an open bit line manner with respect to the bit lines B1u to Bnu and B1d to Bnd of the memory mats Memory Mat u and d.

  In the semiconductor nonvolatile memory device of FIG. 57, the control signal buffer circuit CSB is not particularly limited. For example, a chip enable signal supplied to the external terminals / CE, / OE, / WE, SC, etc. A timing enable signal, a write enable signal, a serial clock signal, and the like are input, and a timing signal of an internal control signal is generated in response to these signals, and the mode control circuit MC receives a ready / read signal from an external terminal R / (/ B). A busy signal is input.

  In this embodiment, “/” such as / CE, / OE, / WE represents a complementary signal.

  Further, in the built-in power supply circuit VS, although not particularly limited, for example, the power supply voltage Vcc and the ground voltage Vss are inputted from the outside, and the word line voltage Vh at the time of erasing (raising the threshold voltage), Verify word line voltage Vhv, word line voltage Vl during write (lower threshold voltage) operation, verify word line voltage Vlv, read bit line voltage Vrb, read reference bit line voltage Vrr, drain terminal voltage during write operation Vld, its transfer gate voltage Vlt, and the like are generated. The suffix of the voltage name is the same as the suffix u / d of the supplied memory mat. The above voltages may be supplied from the outside.

  The voltages generated here include word line voltages Vh, Vhv, Vl, Vlv and transfer gate voltage Vlt as row address decoder circuit XDCR, and bit line voltages Vrb, Vrr, Vld and transfer gate voltage Vlt as sense latch circuit SNS. Are entered respectively.

  In this semiconductor nonvolatile memory device, a row supplied from an external terminal, a row receiving column address signals AX, AY, a complementary address signal formed through column address buffer circuits XADB, YADB are row, column address decoder circuits XDCR, Supplied to YDCR. Although not particularly limited, for example, the row and column address buffer circuits XADB and YADB are activated by a chip enable selection signal / CE inside the device, and take in address signals AX and AY from external terminals, A complementary address signal composed of an internal address signal in phase with the address signal supplied from the terminal and an address signal in reverse phase is formed.

  The row address decoder circuit XDCR forms a selection signal for the word line W of the memory cell group according to the complementary address signal of the row address buffer XADB, and the column address decoder circuit YDCR follows the complementary address signal of the column address buffer circuit YADB. A selection signal for the bit line B of the memory cell group is formed. Thus, a desired memory cell is selected by designating an arbitrary word line W and bit line B in the memory mat Memory Mat.

  Although not particularly limited, for example, memory cells are selected by 8 or 16 bit memory cells by row address decoder circuit XDCR and column address decoder circuit YDCR in order to perform writing or reading in units of 8 bits or 16 bits. A piece or the like is selected. If the number of memory cells in one data block is m in the word line direction (row direction) and n in the bit line direction (column direction), there are 8 or 16 data blocks in the m × n memory cell group. Consists of

  The memory cell is not particularly limited, and has a configuration similar to, for example, an EPROM memory cell, and is a known memory cell having a control gate and a floating gate, or a control gate, a floating gate, and a selection gate. This is a known memory cell. For example, International Electron Devices Meeting Tech. Dig. This is the same structure as the transistor of the memory cell of the flash memory announced in pp. 560-563.

  The NAND type shown in FIG. 52 is a unit block in which a plurality of memory cells are connected in series, and the bit line side and the source line side are also connected via MOS transistors.

  Hereinafter, the layout configuration of the memory mat of this embodiment will be described. FIG. 51 shows a schematic layout diagram of the present invention with respect to the schematic layout diagram of FIG. 50 described in Japanese Unexamined Patent Publication No. 7-176705. As shown in FIG. 51, the bit line Bn is a metal wiring layer M2, the common source line SL is arranged by a metal wiring layer M1 wide in the direction parallel to the word line, and the source of the unit block is a common source for each unit block. This is a layout configuration connected to the line SL.

  The common source line has a line width that is about 100 times the line width of the bit line. FIG. 48 shows a layout of a metal wiring layer in which a plurality of unit blocks are arranged in the bit line direction, and FIG. 49 shows a schematic diagram of a layout of the metal wiring layer of the memory mat.

  In the memory mat of the memory cell array of the semiconductor nonvolatile memory device, the common source line is not arranged between the bit lines but has a layout configuration parallel to the word line. The metal wiring layer of the common source line is formed in a manufacturing process prior to the metal wiring layer used for the bit line. At the end of the memory mat including the dummy memory cell column, a common source line in the column direction (parallel to the bit line) is arranged in the same metal wiring layer as the bit line.

  FIG. 54 shows an equivalent circuit of the memory cell array in the case where the width of the common source line is sufficiently wide and the resistance is small. Since the wiring of the common source line SL is sufficiently wide and the resistance value is small, the value of the source resistance after the source-side MOS transistor becomes a constant value. Therefore, the threshold voltage of the memory cell due to the substrate bias effect does not vary in word line units, that is, sector units. Further, by eliminating the dummy memory cell column formed under the common source line in FIG. 50, the size of the device can be reduced.

  The manufacturing method of the semiconductor nonvolatile memory device of the present embodiment is a new process for forming a metal wiring layer and a contact hole connected to the metal wiring layer in the manufacturing method described in Japanese Patent Laid-Open No. 7-176705. Is added.

  Next, the erase operation and the write operation will be described. In order to set the threshold voltage of the memory cell after the erase operation to be equal to or higher than the upper limit voltage Vccmax of the power supply voltage Vcc that is the word line voltage at the time of reading, a high voltage of about 16 V is applied to the word line that is the control gate of the memory cell. When applied, electrons in the channel are injected into the floating gate by the Fowler-Nordheim tunneling phenomenon. Further, by applying a negative voltage of −4V to the memory well, the word line voltage can be lowered to 12V.

  In the write operation, a negative voltage of about −9 V is applied to the word line, and a voltage of about 4 V, for example, is selectively applied to the drain terminal of the write memory cell, so that a voltage difference is generated between the floating gate and the drain. The electrons in the floating gate are extracted to the drain side by Fowler-Nordheim tunneling. By applying 0 V to the drain terminal of the non-selected memory cell, a voltage difference between the floating gate and the drain is suppressed, and emission of electrons in the floating gate is prevented.

  The threshold voltage of the memory cell at the time of writing must be between the lower limit voltage Vccmin of the power supply voltage Vcc that is the selected word line voltage at the time of reading and 0 V of the ground voltage Vss that is the unselected word line voltage. When the threshold voltage of the non-selected memory cell is lowered to a negative voltage, current flows in the non-selected memory cell, so that erroneous reading is performed. Therefore, a write operation is performed by repeatedly applying a write pulse divided into several times, and an operation for verifying the threshold voltage of the memory cell is performed every time after the write. The word line voltage for write verification is set to about 1.5 V so that the threshold voltage of all memory cells to be written does not become 0 V.

  Note that voltage information applied to the drain terminal of the memory cell described above is stored in a flip-flop FF in the sense latch circuit connected to the drain terminal via the bit line.

  Next, read operation and verify operation will be described. In the verify operation, a voltage value for verifying the word line voltage, for example, 4.2V is set in the write verify and 1.5V in the erase verify, and the same operation as the read operation is performed. 58 shows a circuit diagram of the sense latch circuit SNS, and FIG. 59 shows a timing waveform diagram of the read operation. As shown in FIG. 58, the connection between the memory mat Memory Mat u / d and the sense latch circuit SNS is arranged by the open bit line system. A sense latch circuit SNS including a flip-flop FF is connected to the bit lines Bnu and Bnd. The bit lines Bnu and Bnd have the same (equivalent) connection configuration. Further, the sense latch circuit SNS separately connects control signals to even / odd bit lines. This is to prevent the parasitic line capacitance of the bit line from affecting the sensing operation. As shown in the timing waveform diagram of FIG. 59, for example, during the sensing operation of the memory cell connected to the even bit line side. Reads out the memory cell on the even bit line side with the potential of the odd bit line as Vss and the capacitance between the parasitic lines at a constant value.

  The configuration of the sense latch circuit SNS shown in FIG. 58 will be described by taking the bit line B1U of the memory mat MemoryMu as an example. A MOS transistor that receives a gate signal RPeu for precharging the potential of the bit line is input to the bit line B1u. M1 is connected to a MOS transistor M5 that receives a gate signal BDeu for discharging the potential of the bit line. Between the bit line B1u and the flip-flop FF side wiring B1fu, a MOS transistor M2 that receives the gate signal TReu is connected. The flip-flop wiring B1fu has the MOS transistor M3 that receives the gate signal RFeu for discharging the potential of the flip-flop to the ground voltage Vss, and the column gate signal Yadd corresponding to the column address as input, and information on the flip-flop FF. A MOS transistor M4 for outputting data is connected.

  The read operation will be described with reference to the timing waveform diagram of FIG. The selected mat side is the Memory Mat side, the threshold voltage of the memory cell connected to the even side of the bit line is the write memory cell, and the odd side memory cell is the erased memory cell.

  The word line is selected at t1, and a precharge voltage is applied to the bit line and the sub bit line at t2 before t3 when the word line potential is fully increased. That is, at t2, the bit line reset signal BDe u / d is deactivated, the gate signal SiD u / d of the bit line side MOS transistor is activated, and the precharge signal RPeu / d is activated between t2 and t3. In order to set the drain voltage of the selected memory cell to 1 V, that is, the bit line Bnu potential to 1 V and the non-selected side bit line potential to 0.5 V, the threshold voltage of the transfer MOS transistor is taken into consideration, and the potential of RPeu is set to The potential of 2.0V and RPed is 1.5V.

  During the period from t3 to t4 when the voltage of the word line and the bit line reaches the ultimate potential, the potential of the bit line is discharged by the threshold voltage of the memory cell. Therefore, the gate signal SiS u / d of the source line side MOS transistor is activated at t3, and the gate signal SiD u / d of the bit line side MOS transistor is deactivated at t4. Further, the reset signal RFeu / d of the flip-flop FF is activated between t2 and t4.

  The threshold voltage information of the memory cell is taken into the flip-flop FF between t4 and t5. Data can be taken in by selecting TRe u / d and activating the power supply voltages VEPe and VFNe of the flip-flop FF on the even side. That is, when the threshold voltage which is information of the memory cell is low, the potential of the bit line is discharged, and when the voltage is equal to or lower than the reference voltage, the data of the flip-flop FF becomes the ground voltage Vss. When the threshold voltage of the memory cell is high, since the precharge voltage is maintained, the data of the flip-flop FF becomes the power supply voltage Vcc.

  Between t5 and t6, the even-side bit line, sub bit line Sub Bit Line, and sub source line Sub Source Line are discharged to the ground voltage Vss.

  Next, the odd-side read operation is performed between t6 and t7 in the same manner as the even-side read operation.

  When the memory cell data is taken into the even-side and odd-side flip-flops FF, the column address of the gate signal of the column gate array circuit YG is selected, and the memory cell information is input to the input / output terminal I / O. Is read.

  According to this embodiment, in reading memory cell information, the threshold voltage difference ΔVth shown in FIG. 56 can be reduced, and reading of information in units of sectors is stabilized, that is, variations in threshold voltage are reduced. Furthermore, the area of the apparatus can be reduced.

  Although specific description has been given based on the embodiments, the present invention is not limited to the above-described embodiments, and needless to say, various modifications can be made without departing from the scope of the invention.

  Furthermore, in a computer system such as a notebook personal computer or a portable information terminal, a PC card or the like provided so as to be detachable from the system is used. A flash array FLASH-ARRAY, which is connected to the processing unit CPU and the CPU so as to be able to transmit and receive data, a controller, and a control logic circuit which is connected to be able to transmit data Control Logic, buffer circuit Buffer, interface It consists of a circuit interface.

  In this PC card, data can be transmitted and received among the flash array FLASH-ARRAY, the control logic circuit Control Logic, the buffer circuit Buffer, and the interface circuit Interface, and the PC card is inserted into the system main body. It is connected to the system bus SYSTEM-BUS via the interface circuit Interface.

  For example, the central processing unit CPU performs overall management in an 8-bit data format, and manages interface control, rewrite and read operation control, and arithmetic processing. The flash array FLASH-ARRAY is a 32-Mbit flash device array, for example. For example, one sector consists of a 512-byte data area and a 16-byte utility area, and 8192 sectors are one device.

  The controller Controller is formed of a cell base or a discrete IC, and is provided with a sector table such as DRAM or SRAM. The control logic circuit Control Logic generates timing signals and control signals, and the buffer circuit Buffer is used for temporary storage of data at the time of rewriting.

  As described above, a storage device such as a flash memory can also be used for a PC card, and the nonvolatile semiconductor storage device can be widely used in various systems that require electrical data rewriting.

 The erratic phenomenon can be suppressed by adding the low threshold verify and the selective return operation to the write operation (threshold voltage lowering) sequence. Therefore, it is possible to greatly improve the number of rewrites without determining the restriction on the number of rewrites in consideration of the erratic phenomenon.

  By adding low threshold verification, selective return, high threshold verification, and reselective write operation sequences to the write operation (threshold voltage lowering) sequence, the threshold of the memory cell to be written to Since the value voltage can be suppressed within the range from the low threshold verification word line voltage to the high threshold verification word line voltage, it is possible to improve the read operation margin.

  Especially in electrically rewritable semiconductor non-volatile memory devices, the Fowler-Nordheim tunneling is used for the rewrite operation, selective return operation, and reselective write operation to achieve a low-voltage single power supply and to further reduce the erratic phenomenon. In particular, in a computer system or the like using this, it is possible to reduce system power consumption and improve reliability by lowering the voltage.

  By applying a voltage of 16V to the memory cell required for the erase operation, 12V to the selected word line, and -4V to the memory well, the maximum voltage of the erase operation is almost the same as the maximum operation voltage of the write operation. Thus, a MOS transistor having a gate insulating film of 19 nm and a gate length of about 1 μm can be used, and the chip size of the semiconductor nonvolatile memory device can be reduced.

  By making the rising waveform of the voltage applied to the word line and the memory well from several microseconds to several + microseconds for the sector selected for erasure, the electric field for rewriting the threshold voltage of the memory cell is rapidly applied. This can be prevented and the number of rewrites can be improved.

  Especially in electrically rewritable semiconductor non-volatile memory devices, the rewrite operation uses the Fowler-Nordheim tunnel phenomenon to achieve a single power source with a low voltage and to improve the number of rewrites. In the computer system used, the power consumption of the system can be reduced and the reliability can be improved by reducing the voltage.

  By connecting the common source line of the memory cell array mat for each memory cell column of the unit block and not arranging the dummy memory cell column between the bit lines, the size of the memory mat can be reduced by 3%, and the chip size of the semiconductor nonvolatile device Can be reduced.

  By making the wiring width of the common source line about 100 times thicker than the wiring width of the bit line, the substrate bias applied to the memory cells connected to the same word line, that is, the sector becomes constant, and it becomes a sector unit. Information read stability, that is, variation in threshold voltage can be reduced.

FIG. 3 is a flowchart of a write operation (an operation for lowering a memory cell threshold voltage) according to the first embodiment of the present invention. It is a flowchart figure of the write-in operation | movement which is 2nd Example of this invention. It is a flowchart figure of the write-in operation | movement which is the 3rd Example of this invention. It is a flowchart figure of the write-in operation | movement which is the 4th Example of this invention. It is sectional drawing which shows the transistor of a semiconductor non-volatile memory cell. 6A and 6B are cross-sectional views showing voltage application examples in the operation of selectively reducing the threshold voltage of the transistors of the semiconductor nonvolatile memory cell. 7A and 7B are cross-sectional views showing an example of voltage application in an operation of selectively increasing the threshold voltage of the transistor of the semiconductor nonvolatile memory cell. It is a figure which shows the data of the flip-flop in the sense latch circuit of the operation | movement (write operation) which selectively lowers the memory cell threshold voltage of this invention. It is a figure which shows the data of the flip-flop in the sense latch circuit of the operation | movement which selectively returns a memory cell threshold voltage by one operation | movement of this invention. FIG. 11 is a diagram showing flip-flop data when the selective return of the memory cell threshold voltage according to the present invention is performed by the flip-flop data in the sense latch circuit. It is a figure which shows the data of the flip-flop in the sense latch circuit of the operation | movement (write operation) which selectively lowers the memory cell threshold voltage of this invention again. It is a functional block diagram showing a semiconductor nonvolatile memory device of the present invention. It is a timing chart of a serial access system. 14A and 14B are output state diagrams of the memory cells. It is a timing chart of a random access system. It is an output state diagram of a memory cell. It is a circuit diagram which shows the example of a connection (NOR) of the memory cell which comprises a memory mat. It is a circuit diagram which shows the example of a connection (DINOR) of the memory cell which comprises a memory mat. It is a circuit diagram which shows the example of a connection (AND) of the memory cell which comprises a memory mat. It is a circuit diagram which shows the example of a connection (HICR) of the memory cell which comprises a memory mat. FIG. 3 is a block diagram in which the sense latch circuit of the present invention is an open bit line type with respect to a memory mat. FIG. 3 is a block diagram in which the sense latch circuit of the present invention is a folded bit line system with respect to a memory mat. FIG. 3 is a circuit diagram showing in detail a sense latch circuit of the present invention. It is a wave form diagram which shows the operation timing at the time of the operation | movement (write operation) which selectively lowers the conventional threshold voltage. It is a wave form diagram which shows the operation timing at the time of the operation | movement which selectively returns a memory cell threshold voltage by 1 operation | movement of this invention. FIG. 5 is a waveform diagram showing an operation timing in a selective return operation based on data of a flip-flop in a sense latch circuit for an operation of selectively returning a memory cell threshold voltage according to the present invention. It is a wave form diagram which shows the operation timing at the time of the operation | movement (write operation) which selectively lowers the memory cell threshold voltage of this invention again. It is a functional block diagram showing a computer system using a semiconductor nonvolatile memory device of the present invention. It is a flowchart figure of the conventional write-in operation | movement (operation which lowers a memory cell threshold voltage). It is a figure which shows the write state at the time of performing the operation | movement (write operation) which lowers the threshold voltage of the conventional memory cell. 31A, 31B, and 31C are diagrams showing a write state when an operation (write operation) for lowering the threshold voltage of the memory cell of the present invention is performed. It is a figure which shows the voltage applied to the terminal of the memory cell of this invention. It is a conceptual diagram of the memory mat of the semiconductor non-volatile memory device of one Example of this invention. 34A and 34B are cross-sectional views of a transistor showing an example of voltage application in an erase operation of a conventional semiconductor nonvolatile memory cell. It is sectional drawing of the transistor which shows the example of a voltage application of the selection memory cell in the erase operation of one Example of this invention. 36A, 36B, and 36C are cross-sectional views of transistors showing voltage application examples of unselected memory cells in the erase operation of the semiconductor nonvolatile memory cell according to one embodiment of the present invention. It is a functional block diagram which shows the semiconductor non-volatile memory device of the Example of this invention. FIG. 3 is a circuit diagram showing in detail a sense latch circuit according to an embodiment of the present invention. 1 is a circuit diagram showing in detail a memory mat formed of AND type memory cells in an embodiment of the present invention; FIG. FIG. 4 is a functional block diagram for generating a voltage supplied to a memory mat in an erase operation according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a memory well voltage switching circuit according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a row decoder circuit for selecting a word line according to an embodiment of the present invention. It is a wave form diagram which shows the timing of the erase operation of a prior art example. It is a wave form diagram which shows the timing of the 1st erase operation of one Example of this invention. It is a wave form diagram which shows the timing of the 2nd erase operation of one Example of this invention. It is a wave form diagram which shows the timing of the 3rd erase operation of one Example of this invention. It is a wave form diagram which shows the timing of the 4th erase operation of one Example of this invention. It is a figure which shows the layout of the metal wiring layer of the memory cell array mat part of this invention. It is a figure which shows the layout of the metal wiring layer of the memory cell array mat part of this invention. It is a figure which shows the outline of the layout of the conventional memory cell array part. It is a figure which shows the outline of the layout of the memory cell array part of this invention. It is a circuit diagram which shows the example of a connection of a NAND type memory cell. An equivalent circuit diagram of a conventional memory cell array is shown. 1 shows an equivalent circuit diagram of a memory cell array of the present invention. It is a figure which shows the area ratio of the source line with respect to the number of bit lines between source lines. It is a figure which shows the dependence of the threshold voltage with respect to the bit line position of a memory cell. It is a functional block diagram which shows the semiconductor non-volatile memory device of a present Example. FIG. 3 is a circuit diagram illustrating in detail a sense latch circuit of the present embodiment. It is a wave form diagram which shows the timing of the read-out operation | movement of a present Example. It is a block diagram which shows the example of application to a PC card.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control gate electrode 2 Drain electrode 3 Source electrode 4 Floating gate 5 Interlayer insulating film 6 Tunnel insulating film 7 P-type substrate 8,9 High impurity concentration N type diffusion layer 10 Low impurity concentration N type diffusion layer 11 Low impurity concentration P-type diffusion layer

Claims (16)

  A memory cell array in which a plurality of nonvolatile semiconductor memory cells having control gates, drains and sources are arranged in an array; a word line to which control gates of the plurality of memory cell groups (sectors) are commonly connected; A flip-flop that performs a sense operation and a data latch operation during an operation of raising the threshold voltage for each bit line, and a bit line after verification. A semiconductor nonvolatile memory device comprising a sense latch circuit including a circuit for automatically setting re-data of the flip-flop for each bit according to a threshold state of a memory cell.   Each has a memory mat of a memory cell array in which a plurality of nonvolatile semiconductor memory cells each having a control gate, a drain and a source are arranged in an array, and the control gates of the plurality of memory cell groups (sectors) are connected in common In the operation of increasing the threshold voltage of the memory cell in a sector in units of word lines, the information of the memory cell is rewritten by distributing the positive voltage applied to the word line and the negative voltage applied to the memory well. A semiconductor nonvolatile memory device.   2. The semiconductor nonvolatile memory device according to claim 1, wherein an absolute value of a positive voltage applied to a word line of the semiconductor nonvolatile memory device is larger than an absolute value of a negative voltage applied to a memory well. Semiconductor nonvolatile memory device.   2. The semiconductor non-volatile memory device according to claim 1, wherein the sector constituting the memory mat is selected to increase the threshold voltage, and a sector in which a positive voltage is applied to the word line (selected sector), threshold. The operation to raise the value voltage is not selected, the sector where the word line voltage and the memory well voltage are different (unselected sector), and the operation to raise the threshold voltage is not selected, the word line voltage and the source / drain of the memory cell A semiconductor nonvolatile memory device comprising a sector (completely unselected sector) having an equal inter-voltage (channel voltage).   2. The semiconductor nonvolatile memory device according to claim 1, wherein an absolute value of a memory well voltage in an operation of increasing a threshold voltage of the semiconductor nonvolatile memory device is equal to or lower than a word line voltage at the time of reading. Semiconductor nonvolatile memory device.   5. The semiconductor nonvolatile memory device according to claim 4, wherein the selected sector and the non-selected sector are the same memory mat, and the sectors constituting the other memory mat are completely non-selected. Storage device.   5. The semiconductor non-volatile memory device according to claim 4, wherein a completely non-selected sector of said semiconductor non-volatile memory device applies a negative voltage to the memory well in an operation of raising a threshold voltage, and a channel voltage and a word line voltage are A semiconductor nonvolatile memory device comprising: a memory cell having a ground voltage; or a memory cell having a memory well voltage, a channel voltage, and a word line voltage that are ground voltages.   8. The semiconductor nonvolatile memory device according to claim 7, comprising a unit block in which the plurality of memory cells are connected in parallel, the drain of the memory cell being connected to a bit line via a MOS transistor, The non-volatile semiconductor is characterized in that the source of the non-selected sector is connected to the source line via the MOS transistor, the selected sector and the non-selected sector are included in the same unit block, and the sectors constituting the other blocks are completely non-selected sectors. Sex memory device.   8. The semiconductor nonvolatile memory device according to claim 2, 5 or 7, wherein a rising edge of a voltage applied to a word line and a memory well for a sector selected to increase a threshold voltage of the semiconductor nonvolatile memory device. A semiconductor nonvolatile memory device characterized in that the waveform is set to several μs to several tens of μs.   10. The semiconductor nonvolatile memory device according to claim 9, wherein the voltage arrival time at the rise of the memory well voltage of the semiconductor nonvolatile memory device is equal to the voltage arrival time of the word line voltage. .   11. A computer system using the semiconductor nonvolatile memory device according to claim 2, 5, 7, 9, or 10, further comprising at least a central processing unit and its peripheral circuit in addition to the semiconductor nonvolatile memory device. A featured computer system.   11. The semiconductor nonvolatile memory device according to claim 2, wherein the operation for increasing the threshold voltage is an erasing operation.   In a memory cell array in which a plurality of unit blocks each including a plurality of nonvolatile semiconductor memory cells each having a control gate, a drain, and a source are connected in the column direction, the drains of the memory cells are arranged on bit lines via MOS transistors. The metal wiring layer used in the above is formed in a manufacturing process after the metal wiring layer of the common source line arranged in the row direction (parallel to the word line), and the common source line in the column direction (parallel to the bit line) is a dummy. A semiconductor nonvolatile memory device, which is disposed at a terminal end of a memory array including a memory cell column and is electrically connected to a common source line disposed in the row direction.   14. The semiconductor nonvolatile memory device according to claim 13, wherein a read operation of the memory cell and a verification read operation of the threshold voltage of the memory cell after the rewrite are performed in a word to which the control gates of the memory cells are connected in common. A semiconductor nonvolatile memory device comprising a sense latch circuit that performs a batch operation for each line and performs a sense operation and a rewrite data latch operation for each bit line.   14. The semiconductor nonvolatile memory device according to claim 13, wherein the width of the metal wiring of the common source line arranged in the row direction is arranged with a wiring width of 100 times or more of the metal wiring width of the bit line. A semiconductor nonvolatile memory device.   14. The semiconductor nonvolatile memory device according to claim 13, wherein the source of the memory cell of the unit block is connected to a common source line through a MOS transistor.

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