JP2006286111A - Management apparatus of semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the management apparatus of a semiconductor memory which can accurately discriminate abnormality when physical abnormality is caused in the semiconductor memory. <P>SOLUTION: This apparatus is applied to an EEPROM 25 which is provided to an electronic control unit 20 and can write the prescribed data. The same specific data are written in three storage areas (a, b, c) of the EEPROM 25. Data written in each storage area (a, b, c) are read respectively and compared, when all of respective data are coincident or only two data are coincident, the EEPROM 25 is decided to be normal. When all of the data are non-coincident, the EEPROM 25 is decided to be abnormal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory management device.

  In recent years, an electronic control unit is mounted on various products, and the electronic control unit includes a semiconductor memory (for example, a RAM, an EEPROM, a flash memory, or the like) that temporarily stores data as necessary.

As a method of determining such an abnormality of the semiconductor memory, for example, a method such as a parity check described in Patent Document 1 can be cited. As another abnormality determination method, the storage area of the semiconductor memory is divided into two areas and the same data is written to each of the areas. Conventionally, an abnormality determination method such as determining that the memory is abnormal has been adopted.
JP 2001-73864 A

  Here, as an abnormality of the semiconductor memory, a physical abnormality has occurred in the memory, so that a normal storage function is lost (physical abnormality), a writing error, a reading error, or a normal writing The stored data is damaged due to noise, etc., or the reliability of the stored data is temporarily lowered due to so-called garbled data, etc., but the storage function is normal (memory content abnormality). is there. Of course, in the latter case, by writing data into the semiconductor memory again, the semiconductor memory can be used without any trouble thereafter, and it is not necessary to replace it.

  However, in the conventional abnormality determination method for determining that the semiconductor memory is abnormal because the storage contents indicated by the data written in the two storage areas of the semiconductor memory are different, the above-described two abnormality determination methods are used. The abnormality of two semiconductor memories cannot be distinguished. That is, in the conventional abnormality determination method, it is determined that there is an abnormality when the stored contents indicated by the two read data are different, so the storage function of the semiconductor memory does not function normally. It is not possible to distinguish between a physical abnormality in which the storage contents indicated by the two data are both different from the true value and a storage abnormality in which one of the two data is different from the true value due to data corruption, Therefore, this cannot be appropriately dealt with according to each abnormality.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor memory management device capable of accurately determining an abnormality when a physical abnormality occurs in the semiconductor memory. It is in.

Hereinafter, means for achieving the above-described object and its operation and effects will be described.
First, in the semiconductor memory management device provided in the electronic control unit and capable of writing predetermined data, the storage area of the semiconductor memory is divided into three or more areas and divided. Writing means for writing the same data in the storage area, and reading the written data from each storage area, and the number of data indicating the same storage content is less than a predetermined determination value smaller than the number of divisions of the storage area The gist of the invention is to include an abnormality determination unit that determines that the semiconductor memory is abnormal based on a certain fact.

  According to the above configuration, even if a so-called garbled data, such as a write error or a read error, or data that is normally written is damaged due to the influence of noise or the like, this occurs only in a limited storage area. If the storage contents of the data written in the remaining storage areas match, it can be determined that there is no physical abnormality in the semiconductor memory and that the storage function is maintained. it can. Therefore, it is possible to preferably avoid erroneous determination that the data stored in the semiconductor memory is abnormal due to a temporary decrease in the reliability of the data stored in the semiconductor memory, and the storage function of the semiconductor memory is lost. If a physical abnormality such as this occurs, this can be accurately determined.

  The timing for determining the abnormality is, for example, when it is necessary to perform a data writing process on the semiconductor memory, or immediately after the writing or when it is necessary to perform a process of reading data stored in the semiconductor memory. In addition, it is desirable to carry out it together. In addition to the data writing process and the data reading process, the abnormality determination can be performed every time a predetermined period elapses.

  According to a second aspect of the present invention, in the semiconductor memory management device according to the first aspect, the abnormality determining means sets the determination value to a value larger than half of the number of divisions of the storage area. The gist.

  Here, when the determination value is set to a large value and it is determined that the semiconductor memory is abnormal even when the number of data indicating the same stored content is relatively large, If a physical abnormality has occurred in the semiconductor memory, this can be determined at an early stage, but the possibility of erroneous determination due to data corruption as described above increases. On the other hand, when the determination value is set to a small value and it is determined that the semiconductor memory is abnormal only when the number of data indicating the same storage content is relatively small, the data as described above Although it becomes possible to avoid erroneous determination due to garbled or the like, the determination is delayed when a physical abnormality actually occurs in the semiconductor memory.

  In view of this point, in the configuration according to claim 2, since the determination value is set to a value larger than half of the number of divisions of the storage area, the semiconductor memory is suppressed while minimizing erroneous determination due to data corruption or the like. When a physical abnormality occurs, the abnormality can be determined as early as possible.

  According to a third aspect of the present invention, in the semiconductor memory management device according to the first or second aspect, the semiconductor memory is a non-volatile semiconductor memory, and the electronic control unit includes a volatile semiconductor memory, The writing means writes the data stored in the volatile semiconductor memory to the semiconductor memory and is stored in the semiconductor memory on the condition that the abnormality determining means determines that there is no abnormality. The gist is to write the data indicating the same storage contents into the volatile semiconductor memory.

  According to this configuration, even if the data stored in the volatile semiconductor memory is lost or the reliability of the data is reduced, the data is stored in the nonvolatile semiconductor memory. The data can be recovered by writing the data to the volatile semiconductor memory again. At this time, even if data is garbled in a limited storage area of the semiconductor memory, if it is determined by the abnormality determination means that there is no abnormality, the data is written in each storage area of the semiconductor memory. Among the existing data, data indicating the same storage content is stored in the volatile semiconductor memory. Therefore, for example, unlike a configuration in which the semiconductor memory is divided into two storage areas and the storage contents indicated by the data stored in both storage areas are different, the semiconductor memory is determined to be abnormal. Data recovery can be performed with reliability.

According to a fourth aspect of the present invention, in the semiconductor memory management device according to the third aspect,
The electronic control unit is mounted on a vehicle and constantly supplies power from the battery of the vehicle to the volatile semiconductor memory and retains the stored contents thereof. The writing means stores information on the traveling history of the vehicle as the data. The gist of the present invention is that it further comprises notification means for notifying the abnormality when the abnormality determination means determines that the semiconductor memory is abnormal.

  According to this configuration, when an abnormality occurs in the semiconductor memory, this is notified through the notification means, so that appropriate measures can be taken based on the notification. For example, when an abnormality is notified, the data held in the volatile semiconductor memory is copied to another storage medium, the semiconductor memory is replaced with a normal one, and then the storage medium is stored in the normal semiconductor memory. It is possible to appropriately retain the vehicle travel history information such as copying data from the vehicle. Examples of such vehicle travel history information include the total travel distance of the vehicle, the deterioration history of the exhaust purification catalyst, the total fuel injection amount, the total engine speed, and various learning results relating to the vehicle state. Further, as a specific mode for notifying an abnormality, in a vehicle having a system having a screen for displaying information on the lighting of a warning light, a warning buzzer, or information on the vehicle, the display screen has an abnormality. A method of displaying a certain effect can be given.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor memory management device according to the present invention will be described below.
First, a schematic configuration of an electronic control unit to which the management device according to the present embodiment is applied will be described.

  As shown in FIG. 1, the electronic control unit 20 is provided in the vehicle-mounted internal combustion engine 10 and executes various engine controls such as fuel injection control. The exhaust passage 11 of the internal combustion engine 10 is provided with an exhaust purification catalyst 12 for purifying exhaust and a temperature sensor 13 for detecting the temperature of the exhaust purification catalyst 12. The detection signal of the temperature sensor 13 is taken into the electronic control unit 20. A warning lamp 18 is provided in the passenger compartment as a notification means that lights when an EEPROM 25 (described later) is abnormal.

  The electronic control unit 20 includes a ROM 21, a CPU 22, a RAM 23, a standby RAM (hereinafter referred to as SRAM) 24, an EEPROM 25, and the like. The ROM 21, CPU 22, RAM 23, SRAM 24 and EEPROM 25 are connected to each other via a bus 26. A battery 16 is connected to the electronic control unit 20 via a main relay 15. When the main relay 15 is turned on by turning on the main switch 17, power is supplied from the battery 16 to the electronic control unit 20.

  The ROM 21 is a read-only semiconductor memory that stores various control programs, maps that are referred to when the various control programs are executed, and the like. The CPU 22 executes arithmetic processing based on various control programs and maps stored in the ROM 21. The RAM 23, SRAM 24, and EEPROM 25 are writable semiconductor memories. The RAM 23, SRAM 24, and EEPROM 25 temporarily store calculation results in the CPU 22, data input from various sensors, and the like.

  Note that the RAM 23 and SRAM 24 are volatile semiconductor memories, and the EEPROM 25 is a nonvolatile semiconductor memory. However, the battery 16 is always connected to the SRAM 24, and power is constantly supplied from the battery 16. Thus, the data stored in the SRAM 24 is retained even when the main switch 17 is turned off and the engine operation is stopped.

  The SRAM 24 stores data that is continuously updated over a long period of time, such as information related to the travel history of the vehicle (hereinafter, specific data). Examples of the information related to the travel history of the vehicle include the total travel distance, the deterioration history of the exhaust purification catalyst 12, the total fuel injection amount, the total engine speed, and various learning values related to the vehicle state. Incidentally, as the deterioration history of the exhaust purification catalyst 12, a learning value (deterioration learning value ΣR) relating to thermal deterioration of the exhaust purification catalyst 12 is calculated. Specifically, the deterioration value R is calculated based on the temperature of the exhaust purification catalyst 12, and a value obtained by integrating the deterioration value R is calculated as the deterioration learning value ΣR.

  The specific data is also stored in the EEPROM 25. This is because the specified data stored in the EEPROM 25 when the battery 16 is removed and power is not supplied to the SRAM 24 or when the SRAM 24 is initialized when the SRAM 24 is abnormal, and the specific data in the SRAM 24 is lost. This is because the specific data in the SRAM 24 is recovered by writing the data into the SRAM 24.

  By the way, even if the specific data is stored in the EEPROM 25 in this way, it is meaningless if the EEPROM 25 has failed. Therefore, in the present embodiment, abnormality determination for determining abnormality of the EEPROM 25 is executed. Then, on the condition that the EEPROM 25 is determined not to be abnormal in this abnormality determination, the specific data stored in the SRAM 24 is written into the EEPROM 25, or the specific data stored in the EEPROM 25 is stored in the SRAM 24. Writing is executed.

Hereinafter, a specific processing procedure of processing relating to abnormality determination according to the present embodiment will be described.
In the present embodiment, as abnormality determination processing, abnormality determination processing executed as part of processing for writing specific data into the EEPROM 25 and abnormality determination executed as part of processing for reading specific data from the EEPROM 25 are performed. Two processes are executed.

First, the abnormality determination process executed as part of the writing process to the EEPROM 25 will be described with reference to the flowchart shown in FIG.
A series of processing shown in this flowchart shows a specific processing procedure of the writing processing, and is executed by the electronic control unit 20 as processing at predetermined intervals.

  As shown in FIG. 2, in this process, it is first determined whether or not it is time to write specific data to the EEPROM 25 (step S100). Here, for example, when a predetermined period has elapsed such as the elapse of a predetermined time after the previous writing to the EEPROM 25, it is determined that the timing for performing the writing is reached. When the timing is the same (step S100: YES), the same specific data (for example, the deterioration learning value ΣR stored in the SRAM 24) is stored in the three storage areas A, B, C of the EEPROM 25 (see FIG. 1). (Step S102). In the present embodiment, the process in step S102 functions as a writing unit that divides the storage area of the semiconductor memory into three or more areas and writes the same data in the divided storage areas.

  Thereafter, an abnormality determination process (steps S104 to S108) is executed based on the data written in the storage areas A, B, and C. In the present embodiment, this abnormality determination process functions as an abnormality determination unit that determines that the semiconductor memory is abnormal.

  Specifically, first, the data written in each storage area (a), (b), (c) is read and compared, and two or more of the data indicate the same stored contents, that is, match. It is determined whether or not there is (step S104).

  Then, as illustrated in “pattern a” in FIG. 3, when all the data match (step S <b> 104 in FIG. 2: YES), writing is performed normally and the EEPROM 25 is normal. Is determined (step S106).

  Further, as illustrated in “pattern b” in FIG. 3, even when only two pieces of data match (step S104 in FIG. 2: YES), it is determined that the EEPROM 25 is normal (step S106).

  On the other hand, as illustrated in “pattern c” in FIG. 3, when all the data do not match (step S104 in FIG. 2: YES), it is determined that the data cannot be normally written, It is determined that the EEPROM 25 is abnormal (step S108).

As described above, after it is determined that the EEPROM 25 is normal or abnormal, this processing is temporarily terminated.
If it is determined in this process that the EEPROM 25 is abnormal, the warning lamp 18 is turned on through a separate process. Thereafter, writing of the specific data stored in the SRAM 24 to the EEPROM 25 and writing of the specific data stored in the EEPROM 25 to the SRAM 24 are prohibited.

  Incidentally, if it is determined that the EEPROM 25 is abnormal, the EEPROM 25 is replaced in the following procedure. That is, first, an external device as a storage medium is connected to the electronic control unit 20, and specific data held in the SRAM 24 is copied to the external device. Next, the EEPROM 25 is replaced with a normal one, and then specific data is copied to the normal EEPROM 25 from the external device. Specific data is appropriately retained through such exchange operations.

Next, the abnormality determination process executed as part of the reading process from the EEPROM 25 will be described with reference to the flowchart shown in FIG.
Note that a series of processing shown in this flowchart shows a specific processing procedure of the reading processing, and is executed by the electronic control unit 20 as processing at predetermined intervals.

As shown in FIG. 4, in this process, it is first determined whether or not it is time to read specific data from the EEPROM 25 (step S200). Here, when both of the following conditions are satisfied, it is determined that the read timing is reached.
-There is a history that the SRAM 24 is initialized. The initialization of the SRAM 24 is executed when the power supply to the SRAM 24 is temporarily stopped by replacing the battery 16 or when abnormality of the SRAM 24 is determined in a separate process.
-There is no history of reading the specific data stored in the EEPROM 25 after the SRAM 24 is initialized.

  If it is time to read data (step S200: YES), the data stored in the three storage areas A, B, and C (see FIG. 1) of the EEPROM 25 are read (step S202).

  Thereafter, an abnormality determination process (steps 204, S206, S210) is executed based on the data read from the storage areas A, B, C. Specifically, first, it is determined whether or not two or more of the data read from each storage area A, B, C match (step S204).

  Then, as illustrated in “pattern d” in FIG. 5, when all the data match (step S <b> 204 in FIG. 4: YES), it is determined that the reading is performed normally and the EEPROM 25 is normal. (Step S206). In this case, any of the read data is written into the storage area of the SRAM 24 (step S208).

  Further, as exemplified in the “pattern e” of FIG. 5, even when only two data match (step S204: YES in FIG. 4), it is determined that the EEPROM 25 is normal (step S206). In this case, the matching data is written as normal data in the storage area of the SRAM 24 (step S208).

  On the other hand, as illustrated in “pattern f” in FIG. 5, when all the data do not match (step S <b> 204 in FIG. 4: YES), it is determined that the data cannot be read normally. Then, it is determined that the EEPROM 25 is abnormal (step S210). In this case, a predetermined initial value is written in the storage area of the SRAM 24 (step S212).

As described above, after the matching data or the initial value is written in the SRAM 24, the present process is temporarily terminated.
Even when it is determined in this process that the EEPROM 25 is abnormal, the warning lamp 18 is turned on through a separate process. Thereafter, writing of specific data stored in the SRAM 24 to the EEPROM 25 and writing of specific data stored in the EEPROM 25 to the SRAM 24 are prohibited.

Hereinafter, an effect of executing the abnormality determination process of the present embodiment will be described.
According to the above abnormality determination process, even if a so-called garbled data or the like occurs if a write error or read error or data written normally is damaged due to the influence of noise or the like, this is only for data in one storage area. If it occurs, it can be determined that there is no physical abnormality in the EEPROM 25 by matching the data read from the remaining two storage areas. In this case, although the reliability of the data stored in the EEPROM 25 is temporarily lowered, it can be determined that the storage function is maintained and the EEPROM 25 is normal.

  Therefore, it is possible to preferably avoid erroneous determination that the data stored in the EEPROM 25 is abnormal due to a temporary decrease in the reliability of the data stored in the EEPROM 25, and the storage function of the EEPROM 25 is lost. If a physical abnormality such as this occurs, this can be accurately determined.

  On the condition that it is determined to be normal by the abnormality determination process, the matching data among the data read from the storage areas A, B, C of the EEPROM 25 is written into the SRAM 24. As a result, when the data corruption or the like occurs only for the data in one storage area, the matching data read from the remaining two storage areas is written to the SRAM 24 as normal data. Therefore, unlike the configuration in which, for example, the same data is written in two storage areas of the EEPROM and then the storage contents indicated by the data read from the two areas are different, it is determined that the EEPROM is abnormal. It becomes possible to perform writing of specific data and thus recovery of specific data with high reliability.

As described above, according to the present embodiment, the effects described below can be obtained.
(1) When a physical abnormality occurs that causes the storage function of the EEPROM 25 to be lost, this can be accurately determined.

(2) The specific data in the SRAM 24 can be recovered with high reliability.
(3) Since the warning lamp 18 is lit when it is determined that the EEPROM 25 is abnormal, the driver can recognize that the EEPROM 25 is abnormal. Appropriate measures can be taken, such as prompting.

The embodiment described above may be modified as follows.
-Instead of turning on the warning lamp 18, a warning buzzer may be heard. In addition, in a vehicle having a system having a screen for displaying information related to the vehicle, such as a navigation system, it is possible to display that the display screen has an abnormality. In short, it is only necessary to be able to notify the abnormality when it is determined that the EEPROM 25 is abnormal. It is also possible to omit the configuration for notifying that the EEPROM 25 is abnormal.

  Only one of the abnormality determination process (FIG. 2) executed as part of the writing process and the abnormality determination process (FIG. 4) executed as part of the read process may be executed.

The abnormality determination process may be executed separately from the writing process and the reading process as a process executed every time a predetermined period elapses.
Although the same specific data is written in the three storage areas A, B and C of the EEPROM 25, it may be written in four or more storage areas. In the same configuration, a predetermined determination value smaller than the number of storage areas to which the same specific data is written is set, and the number of matching data among the data read from each storage area is less than the determination value. Based on this, it may be determined that the EEPROM 25 is abnormal.

  In this case, it is desirable to set the determination value to a value larger than half the number of storage areas in which the same specific data is written. Here, when the determination value is set to a large value and it is determined that the EEPROM 25 is abnormal even when the number of matching data is relatively large, the physical value is actually stored in the EEPROM 25. If an abnormality has occurred, this can be determined early, but the possibility of erroneous determination due to garbled data or the like as described above increases. On the other hand, when the determination value is set to a small value and it is determined that the EEPROM 25 is abnormal only when the number of matching data is relatively small, erroneous determination due to data corruption or the like is avoided. However, if a physical abnormality actually occurs in the EEPROM 25, the determination is delayed. In this regard, as in the above configuration, by setting a value larger than half the number of storage areas in which the same specific data is written as a determination value, it is possible to physically store the EEPROM 25 while suppressing erroneous determination due to garbled data as much as possible. When such an abnormality occurs, the abnormality can be determined as early as possible.

  -The management apparatus concerning this invention is applicable to other non-volatile semiconductor memories, such as flash memory, besides EEPROM. Moreover, the management apparatus according to the present invention can be applied not only to a nonvolatile semiconductor memory but also to a volatile semiconductor memory such as various RAMs.

1 is a schematic configuration diagram of an electronic control unit to which an embodiment of the present invention is applied. The flowchart which shows the specific process sequence of a writing process. 6 is a schematic diagram showing a relationship between data written in each storage area and a determination result. The flowchart which shows the specific process sequence of a read process. 6 is a schematic diagram showing a relationship between data read from each storage area and a determination result.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Internal combustion engine, 11 ... Exhaust passage, 12 ... Exhaust purification catalyst, 13 ... Temperature sensor, 15 ... Main relay, 16 ... Battery, 17 ... Main switch, 18 ... Warning light, 20 ... Electronic control unit, 21 ... ROM, 22 ... CPU, 23 ... RAM, 24 ... standby RAM (SRAM), 25 ... EEPROM, 26 ... bus.

Claims (4)

In a semiconductor memory management device provided in an electronic control unit and capable of writing predetermined data,
Writing means for dividing the storage area of the semiconductor memory into three or more areas and writing the same data in the divided storage areas;
Read the written data from each storage area, and determine that the semiconductor memory is abnormal based on the fact that the number of data indicating the same storage contents is less than a predetermined determination value smaller than the number of divisions of the storage area And a semiconductor memory management device. The semiconductor memory management device according to claim 1,
The abnormality determination means sets the determination value to a value larger than half of the number of divisions of the storage area. The semiconductor memory management device according to claim 1 or 2,
The semiconductor memory is a non-volatile semiconductor memory, and the electronic control unit includes a volatile semiconductor memory,
The writing means writes the data stored in the volatile semiconductor memory to the semiconductor memory, and is stored in the semiconductor memory on the condition that the abnormality determining means determines that there is no abnormality. A semiconductor memory management device, wherein the data indicating the same storage content is written into the volatile semiconductor memory. The semiconductor memory management device according to claim 3,
The electronic control unit is mounted on a vehicle and constantly supplies power from the battery of the vehicle to the volatile semiconductor memory to hold the stored contents.
The writing means writes information relating to the traveling history of the vehicle as the data in the memories.
A semiconductor memory management device, further comprising: a notifying means for notifying the abnormality when the abnormality determining means determines that the semiconductor memory is abnormal.

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