JP2006278953A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device whose ohmic resistance is less between an electrode and a channel and has a good high frequency characteristic. <P>SOLUTION: Recessed channels 16a, 17a are located at a position where a drain electrode 16 and a source electrode 17 are formed on an undoped gallium arsenide (GaAs) layer 15a as a cap layer, the drain electrode 16 and the source 17 are formed in the channels 16a and 17a respectively, and the distance is shortened between each electrode and an n-type gallium arsenide (GaAs) layer 13 as a channel layer. The exposure of surroundings of the channels 16a, 17a is prevented by forming the drain electrode 16 and the source electrode 17 in a shape to overhang the surface of the undoped gallium arsenide (GaAs) layer 15a as a cap layer, and the effect can be reduced that the variation of surface level at this position gives to the n-type gallium arsenide (GaAs) layer 13. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a heterojunction field effect transistor with reduced ohmic resistance between an electrode and a channel layer.

  A heterojunction field effect transistor (HFET) including a high electron mobility transistor (HEMT) using a compound semiconductor has good high frequency characteristics and is widely used particularly as a semiconductor device in a microwave band.

  An example of a cross section of a conventional heterojunction field effect transistor using gallium arsenide (GaAs) as a compound semiconductor is shown in FIG. The heterojunction field effect transistor 30 includes an aluminum gallium arsenide (AlGaAs) layer 32 as a buffer layer, an n-type gallium arsenide (GaAs) layer 33 and an undoped aluminum gallium arsenide (active layer) on a semi-insulating semiconductor substrate 31. A drain electrode 36 and a source electrode which are in ohmic contact with the undoped gallium arsenide (GaAs) layer 35 on a semiconductor layer substrate in which an AlGaAs) layer 34 and an undoped gallium arsenide (GaAs) layer 35 as a cap layer are sequentially stacked. 37, and a gate electrode 38 embedded in the undoped gallium arsenide (GaAs) layer 35 and Schottky joined to the undoped aluminum gallium arsenide (AlGaAs) layer 34.

  In the heterojunction field effect transistor 30, the gate electrode 38 is penetrated to the undoped aluminum gallium arsenide (AlGaAs) layer 34 so as to be embedded in the undoped gallium arsenide (GaAs) layer 35, thereby forming the undoped gallium arsenide (GaAs) layer 35. The influence of the fluctuation of the surface level formed on the surface on the n-type gallium arsenide (GaAs) layer 33 as the channel layer is reduced.

Such a conventional semiconductor device is disclosed in Patent Document 1 and the like.
JP-A-6-124965 (page 4, FIG. 1)

  As described above, the undoped gallium arsenide (GaAs) layer 35 can suppress variations in characteristics of the heterojunction field-effect transistor 30 due to variations in the surface state, but the gate electrode increases as the thickness of this layer increases. The parasitic capacitance generated between the heterojunction field effect transistor 30 and the high frequency characteristics of the heterojunction field effect transistor 30 is impaired. For this reason, the thickness of the undoped gallium arsenide (GaAs) layer 35 is set to about 100 nm to 500 nm in accordance with the target frequency band.

  However, when the undoped gallium arsenide (GaAs) layer 35 as the cap layer has a thickness in the above range, in the conventional heterojunction field effect transistor 30 illustrated in FIG. The distance between each of the electrodes and the n-type gallium arsenide (GaAs) layer 33 as the channel layer becomes longer. Two layers existing between them, namely, an undoped aluminum gallium arsenide (AlGaAs) layer 34 and an undoped gallium arsenide (GaAs) layer 35 are both undoped layers. For this reason, the ohmic resistance between each electrode of the drain electrode 36 and the source electrode 37 and the n-type gallium arsenide (GaAs) layer 33 is increased, and the high frequency characteristics of the heterojunction field effect transistor 30 are deteriorated. was there.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a semiconductor device having good high frequency characteristics with low ohmic resistance between an electrode and a channel layer.

  In order to achieve the above object, a semiconductor device of the present invention has a drain electrode, a source electrode, and a gate electrode on a semiconductor layer substrate in which a buffer layer, an active layer, and a cap layer are sequentially stacked on a semi-insulating semiconductor substrate. In the formed semiconductor device, an etching stopper layer having a composition different from that of the cap layer is inserted into a predetermined position in the cap layer, and the drain electrode and the source electrode are connected to the etching stopper layer in the cap layer or the etching layer. The bottom surface and side surface of the concave groove etched away deeper than the stopper layer, and the surface of the cap layer protruding from the surface of the cap layer are formed by ohmic contact, and the gate electrode penetrates the cap layer. The active layer is formed by Schottky junction.

  According to the present invention, it is possible to obtain a semiconductor device having good high frequency characteristics with little ohmic resistance between the electrode and the channel layer.

  The best mode for carrying out a semiconductor device according to the present invention will be described below with reference to FIGS.

  FIG. 1 is a sectional view showing a model of a first embodiment of a semiconductor device according to the present invention. The semiconductor device 1 of FIG. 1 illustrates the case where the semiconductor layer substrate contains gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs).

  As shown in FIG. 1, the semiconductor device 1 includes an aluminum gallium arsenide (AlGaAs) layer 12 as a buffer layer and an n-type gallium arsenide as an active layer on a semi-insulating semiconductor substrate 11 of, for example, gallium arsenide (GaAs). An (GaAs) layer 13 and an undoped aluminum gallium arsenide (AlGaAs) layer 14, and an undoped gallium arsenide (GaAs) layer 15 a inserted into the layer using an undoped aluminum gallium arsenide (AlGaAs) layer 15 b as an etching stopper layer as a cap layer. A semiconductor layer substrate is sequentially stacked. Each layer laminated on the semi-insulating semiconductor substrate 11 is formed by epitaxial growth using, for example, the MOCVD method for each layer and sequentially depositing them.

  In this embodiment, an undoped gallium arsenide (GaAs) layer 15a having an undoped aluminum gallium arsenide (AlGaAs) layer 15b inserted therein is deposited to a thickness of about 100 nm or more. The undoped aluminum gallium arsenide (AlGaAs) layer 15b as an etching stopper layer is provided for the purpose of stopping etching at a predetermined depth by utilizing the difference in etching rate with the undoped gallium arsenide (GaAs) layer 15a. In general, since the resistance of ohmic contact on undoped aluminum gallium arsenide (AlGaAs) is high, it is desirable to remove undoped aluminum gallium arsenide when forming the drain electrode 16 and the source electrode 17.

  A drain electrode 16, a source electrode 17, and a gate electrode 18 are formed on the surface of the undoped gallium arsenide (GaAs) layer 15. The drain electrode 16 and the source electrode 17 both cover the bottom and side surfaces of the concave grooves 16a and 17a formed so as to dig the undoped gallium arsenide (GaAs) layer 15a to the etching stopper layer 15b. And 17a are formed on the surface of the peripheral layer, and are formed in ohmic contact with the undoped gallium arsenide (GaAs) layer 15a. In this embodiment, the depth of the grooves 16a and 17a is set to a depth at which the remaining thickness up to the n-type gallium arsenide (GaAs) layer 13 as the channel layer is about 50 to 80 nm.

  The gate electrode 18 is disposed between the drain electrode 16 and the source electrode 17 and penetrates through the undoped gallium arsenide (AlGaAs) layer 14 so as to be embedded in the undoped gallium arsenide (GaAs) layer 15a. Are formed by Schottky bonding.

  In the semiconductor device 1 having the above-described configuration, the concave grooves 16a and 17a are provided at positions where the drain electrode 16 and the source electrode 17 are formed on the undoped gallium arsenide (GaAs) layer 15a serving as a cap layer. A drain electrode 16 and a source electrode 17 are formed in the grooves 16a and 17a, respectively. Accordingly, the distance between each electrode and the n-type gallium arsenide (GaAs) layer 13 as the channel layer can be shortened to reduce the ohmic resistance therebetween, so that good high frequency characteristics can be obtained.

  In addition, the drain electrode 16 and the source electrode 17 are formed in a shape protruding on the surface of an undoped gallium arsenide (GaAs) layer 15a as a cap layer. As a result, the peripheral portions of the grooves 16a and 17a are not exposed, and the influence of the fluctuation of the surface level at this portion on the n-type gallium arsenide (GaAs) layer 13 as the channel layer can be reduced. Characteristics can be obtained.

  FIG. 2 is a sectional view showing a second embodiment of the semiconductor device according to the present invention as a model. Regarding the respective parts of the second embodiment, the same parts as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals and the description thereof is omitted. The second embodiment is different from the first embodiment in that an insulating film is further laminated on the cap layer, and each electrode extends to the insulating film. Only the differences will be described below with reference to FIG.

  As shown in FIG. 2, the semiconductor device 2 includes an aluminum gallium arsenide (AlGaAs) layer 12, an n-type gallium arsenide (GaAs) layer 13, and an undoped aluminum gallium arsenide (AlGaAs) layer on a semi-insulating semiconductor substrate 11. 14 and an insulating film 19 is further laminated on a semiconductor layer substrate in which an undoped aluminum gallium arsenide (AlGaAs) layer 15b is used as an etching stopper layer and an undoped gallium arsenide (GaAs) layer 15a is sequentially laminated. . The insulating film 19 is, for example, a silicon nitride (SiN) film deposited by a plasma CVD method or the like.

  The drain electrode 16, the source electrode 17, and the gate electrode 18 are formed by removing the insulating film 19 corresponding to the formation site of these electrodes by, for example, RIE. At this time, the drain electrode 16 and the source electrode 17 cover the entire surfaces of the grooves 16a and 17a of the undoped gallium arsenide (GaAs) layer 15a serving as a cap layer and extend to the surface of the insulating film 19, respectively. And is formed by ohmic contact with the undoped gallium arsenide (GaAs) layer 15a. The gate electrode 18 that is Schottky bonded to the undoped aluminum gallium arsenide (AlGaAs) layer 14 also has a shape extending to the surface of the insulating film 19.

  In the semiconductor device 2 configured as described above, the insulating film 19 is further laminated on the undoped gallium arsenide (GaAs) layer 15a as the cap layer. The insulating film 19 reduces the fluctuation of the surface level of the semiconductor device 2 and improves the adhesion thereof, thereby stabilizing the interface. Therefore, in addition to the effect of the first embodiment, the influence from the interface to the channel layer can be further reduced, and more stable high frequency characteristics can be obtained.

  In the first and second embodiments described above, the configuration including gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) as the semiconductor layer substrate has been illustrated, but this is not limited to indium gallium arsenide (InGaAs), and A structure containing indium aluminum gallium arsenide (InAlGaAs) can also be used. Alternatively, a structure including gallium nitride (GaN) and aluminum gallium nitride (AlGaN) can be used. In any configuration, the same effects as those in the configuration including gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) can be obtained.

Sectional drawing which models and shows the 1st Example of the semiconductor device which concerns on this invention. Sectional drawing which models and shows the 2nd Example of the semiconductor device which concerns on this invention. Sectional drawing which shows an example of the conventional heterojunction field effect transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Semiconductor device 11 Semi-insulating semiconductor substrate 12 Aluminum gallium arsenide (AlGaAs) layer 13 n-type gallium arsenide (GaAs) layer 14 Undoped aluminum gallium arsenide (AlGaAs) layer 15a Undoped gallium arsenide (GaAs) layer 15b Undoped aluminum gallium arsenide (AlGaAs) layer 16 Drain electrodes 16a and 17a Groove 17 Source electrode 18 Gate electrode 19 Insulating film

Claims (5)

In a semiconductor device in which a drain electrode, a source electrode, and a gate electrode are formed on a semiconductor layer substrate in which a buffer layer, an active layer, and a cap layer are sequentially stacked on a semi-insulating semiconductor substrate.
An etching stopper layer having a composition different from that of the cap layer is inserted at a predetermined position in the cap layer,
The drain electrode and the source electrode protrude from the etching stopper layer in the cap layer or the bottom and side surfaces of the concave groove etched away deeper than the etching stopper layer, and the surface of the cap layer at the periphery of the groove. Formed by ohmic contact,
The semiconductor device according to claim 1, wherein the gate electrode penetrates the cap layer and is formed on the active layer by a Schottky junction.   2. The semiconductor device according to claim 1, wherein an insulating film is further laminated on the cap layer, and the drain electrode, the source electrode, and the gate electrode are extended on the insulating film.   The semiconductor device according to claim 1, wherein the semiconductor layer substrate includes gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs).   The semiconductor device according to claim 1, wherein the semiconductor layer substrate includes indium gallium arsenide (InGaAs) and indium aluminum gallium arsenide (InAlGaAs).   The semiconductor device according to claim 1, wherein the semiconductor layer substrate contains gallium nitride (GaN) and aluminum gallium nitride (AlGaN).

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