JP2006277888A - Semiconductor storage device and information readout method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which suppresses increase of a chip area and enables information unique to a chip to be recorded. <P>SOLUTION: The device has: a nonvolatile memory group for storing an addresses of unique information or defective cells; an enable nonvolatile memory element indicating that the information, saved in the nonvolatile memory group, is either the address of the defective cell or the unique information; a mode invertor in which the information on the enable nonvolatile memory element is referred to, when a test mode signal is inputted, a unique information activation signal is sent out to outside, and when the test mode signal is not inputted, a redundant cell activation signal is sent out to the outside; and a redundancy selector in which, if the address signal matches the information on the nonvolatile memory group, when a unique information activation signal is received from the mode inverter, a unique information detection signal is outputted, and when a redundant cell activation signal is received from the mode inverter, the information on the redundant cell is outputted. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and an information reading method for reading information unique to the semiconductor memory device from the semiconductor memory device.

  A semiconductor memory device has a main cell region in which a plurality of memory cells for storing information are provided, and a peripheral circuit region for reading information from and writing information to the memory cells. In a conventional semiconductor memory device, a redundant cell is generally provided as a cell for replacing a malfunctioning memory cell in the main cell region at the end of the main cell region. However, the number of redundant cells is smaller than that of the main cell region due to chip area restrictions.

  The memory cells in the main cell region are arranged in a predetermined number of rows and columns. The address of each memory cell is specified by a row address and a column address. By designating the address of the memory cell, the information stored in the designated memory cell can be read out through the peripheral circuit.

  If a pattern defect occurs in the memory cell during the manufacturing process of the semiconductor memory device, the memory cell becomes an inoperable defective cell. Information cannot be written to the defective cell. Therefore, a circuit for switching access to a defective cell in the main cell region to a redundant cell is provided in the peripheral circuit region. This circuit is provided with a plurality of fuses, and by switching the plurality of fuses corresponding to the address of the defective cell, the electrical connection path is switched, and a redundant cell can be used instead of the defective cell. Such replacement of a defective cell with a redundant cell is called redundant relief.

  After the completion of the wafer process, in the redundancy test step in the wafer sorting step, an operation test is performed on the memory cells in each semiconductor memory device formed on the substrate. If it is determined in this test that the cell is defective, the above-described redundancy repair process is performed.

  The yield, which is the ratio of the number of non-defective semiconductor memory devices manufactured from one substrate, is improved by redundancy relief, and the manufacturing cost for a single unit is reduced. On the other hand, when a problem occurs in a semiconductor memory device after being shipped to the market, it is possible to improve the yield and reliability by investigating the cause and feeding back to the manufacturing process. Therefore, the history from manufacture to shipment of the semiconductor memory device is important. A conventional history management method will be described below.

  Conventionally, a semiconductor memory device has been managed for each lot from the manufacturing process, and the history of the semiconductor memory device after commercialization has been managed by using a lot number. Therefore, when a malfunction occurs in a semiconductor memory device in the market, the history of the lot of the semiconductor memory device is examined to find the cause of the malfunction.

  However, even if the lot number of the semiconductor memory device in which the malfunction has occurred can be identified, normally, since one lot consists of a plurality of substrates, it is impossible to determine from the history to the substrate in that lot and the position on the substrate.

  In addition, despite the request for disposal of a semiconductor storage device that was defective in the inspection prior to product shipment, someone sold the product as if it were a good product before final disposal. The problem of doing is also happening. Explain that if a person who has purchased a defective product without knowing anything asks a legitimate manufacturer for compensation, but only the lot history remains, the defective product has been disposed of. I can't.

As described above, in order to be able to examine the history of each semiconductor memory device, it is desirable to record different unique information for each semiconductor memory device. Examples of the method are disclosed in Patent Document 1 and Patent Document 2. In the methods disclosed in these documents, a fuse element for recording additional information and a unique identification number is provided in advance, and a chip can be identified by writing chip-specific information therein.
JP 2002-299561 A JP 2000-068458 A

  In the methods of Patent Document 1 and Patent Document 2, a storage area must be reserved for recording additional information and a unique identification number. For this reason, when the chip area is increased and the chip area is increased, the number of chips manufactured per substrate is reduced, and as a result, there is a problem that the unit price of the product is increased.

  The present invention has been made to solve the above-described problems of the prior art, a semiconductor memory device and an information reading method capable of suppressing increase in chip area and recording chip-specific information. The purpose is to provide.

In order to achieve the above object, a semiconductor memory device of the present invention includes a plurality of memory cells and a redundant cell that replaces a defective cell in the plurality of memory cells.
A non-volatile memory group consisting of a plurality of non-volatile memory elements for storing unique information which is different information for each semiconductor memory device or an address of the defective cell;
An enable nonvolatile memory element provided corresponding to the nonvolatile memory group and storing information for determining whether the information stored in the nonvolatile memory group is an address of the defective cell or the unique information When,
When a test mode signal for reading the unique information is input with reference to information stored in the enable nonvolatile memory element, a unique information activation signal for activating the nonvolatile memory group storing the unique information is generated. A mode inverter that sends out a redundant cell activation signal that activates a nonvolatile memory group in which the address of the defective cell is stored if the test mode signal is not input,
When the input address signal and the information in the non-volatile memory group match, if the signal received from the mode inverter is a unique information activation signal, the unique information detection is a signal indicating that the unique information has been detected. A redundancy selector for outputting a signal and outputting the information stored in the redundancy cell instead of the memory cell specified by the address signal when the signal received from the mode inverter is a redundancy cell activation signal; ,
It is the structure which has.

  In the present invention, after storing the unique information in the nonvolatile memory group in advance, when a test mode signal is input to the mode inverter and an arbitrary address signal is input, the redundant selection is performed when the input address signal matches the unique information. A unique information detection signal is output from the device. For this reason, when a non-volatile memory group that is not used for redundancy relief is used for storing unique information, it is possible to read the information of the address signal when the unique information detection signal is output as the unique information.

On the other hand, an information reading method of the present invention for achieving the above object is a method for reading the unique information from the semiconductor memory device of the present invention,
Inputting a test mode signal for reading the unique information to the mode inverter;
Monitoring the output from the redundancy selector and changing the input address signal from the predetermined address to the upper or lower order by one count;
Reading the address signal as the unique information when the unique information detection signal is output from the redundant selector;
It is what has.

  In the present invention, the special information for storing the unique information is not required by storing the unique information of the chip in the non-volatile memory group that is not used for redundancy relief. Therefore, it is possible to prevent the manufacturing unit price from increasing without increasing the chip area.

  The semiconductor memory device of the present invention stores information for identifying a main body in a nonvolatile memory element that is not used for redundancy relief, among nonvolatile memory elements such as fuses provided for redundancy relief.

  The configuration of the semiconductor memory device of this embodiment will be described.

  FIG. 1 is a block diagram illustrating a configuration example of a main part of a semiconductor memory device. In FIG. 1, the portion related to the redundant switching circuit is mainly shown.

  The semiconductor memory device of this embodiment selects a main cell region 600, an address driver 602 for driving an address of a predetermined memory cell, a write circuit 606 for writing information to the memory cell, and a predetermined memory cell. It includes a multiplexer 604 that outputs stored information and an amplifier 608 that amplifies information received from the multiplexer 604. In the present embodiment, it is assumed that 16 memory cells are provided in the main cell region 600 in order to simplify the description. Then, the addresses of 16 memory cells are designated by a 4-digit binary number. That is, the addresses of the memory cells in the main cell area 600 are from “0000” to “1111”. A signal output from the amplifier 608 is referred to as memory cell information output.

  Further, the semiconductor memory device is enabled by a test mode signal, a fuse set 100 for storing a defective cell address or unique information, a fuse state reading circuit 104 for detecting a cutting state of a plurality of fuses in the fuse set 100, and a test mode signal. A mode inverter 106 that inverts a fuse cutting state signal, an address comparator 108 that compares whether the address signal and the fuse state reading circuit cutting state signal match, an address comparator signal and an enable fuse cutting state signal A redundancy selector 110 for stopping the address selector and selecting a redundant cell. In this embodiment, two sets of the fuse set 100, the fuse state reading circuit 104, the mode inverter 106, the address comparator 108, and the redundancy selector 110 are provided. In FIG. Different combinations are distinguished.

  The unique information includes information of an identifier that is different for each chip. In addition, information indicating a history such as a chip lot name, pass / fail information, a wafer number, and intra-wafer chip coordinates may be included in the unique information. The test mode signal is a signal for reading out the unique information. The test mode signal is a signal indicating information “1” in the on state, and a signal indicating information “0” in the off state. The address signal is a signal for designating the address of the memory cell in the main cell area. Although the signal line to which the address signal is input is shown in FIG. 1 as one thick line, as described above, in this embodiment, the address of the memory cell is designated by a 4-digit binary number. There are four signal lines for designating.

  Further, the semiconductor memory device includes an address selector 500 that selects a memory cell specified by the address signal, an output synthesizer 502 that synthesizes a redundant selector output that is an output signal from the redundant selector 110, and a test mode signal. The output switch 504 outputs either one of the memory cell information output and the redundant selector output information.

  Below, the structure of each part is demonstrated in detail.

  The fuse set 100 includes an address fuse group 10 for storing address information or unique information of a defective cell, and an enable fuse 102 for determining information to be stored in the address fuse group 10. The address fuse group 10 includes a plurality of fuses 11 to 14. When the address information of the defective cell is stored in the address fuse group 10, the enable fuse 102 is cut. On the other hand, when the unique information is stored in the address fuse group 10, the enable fuse 102 is not cut.

  In order to redundantly repair a defective cell, when storing address information of the defective cell in the address fuse group 10, the enable fuse 102 is cut and the fuses 11 to 14 are cut corresponding to the address of the defective cell. When the unique information is stored in the address fuse group 10, the enable fuse 102 is not cut, and the fuses 11 to 14 are cut corresponding to the unique information.

  In this embodiment, the fuse set 100a is used for redundancy relief, and the fuse set 100b is used for storing unique information. In the following, it is assumed that the cut fuse indicates information “1”, and the uncut fuse indicates information “0”. In the fuse set 100a used for redundancy relief, since the enable fuse 102a is cut, the fuses 11a to 14a indicate the address “0100” as the address of the defective cell. On the other hand, in the fuse set 100b used for storing unique information, since the enable fuse 102b is not cut, the fuses 11b to 14b indicate unique information of “0100” in binary.

  The fuse state reading circuit 104 detects a cut state for each of the fuses 11 to 14. The case of cutting is converted into an electric signal of information “1”, and the case of not cutting is converted into an electric signal of information “0”. Hereinafter, this electric signal is referred to as a fuse state reading signal. Table 1 shows the output of the fuse state reading circuit 104 with respect to the input.

  FIG. 2 is a block diagram showing a configuration example of the address comparator. As shown in FIG. 2, the address signal is a parallel signal corresponding to the fuses 11 to 14 on a one-to-one basis.

  As shown in FIG. 2, the address comparator 108 includes a plurality of XNOR (exclusive NOR) circuits 81 to 84 corresponding to the fuses 11 to 14 and an AND to which outputs from the plurality of XNOR circuits 81 to 84 are input. Circuit 85. Each XNOR circuit 81 to 84 sends a signal indicating information “1” to the AND circuit 85 when the address signal and the fuse state reading signal match, and ANDs a signal indicating information “0” if the two signals do not match. Send to circuit 85. The AND circuit 85 outputs an address comparator signal of information “1” when all the signals input from the XNOR circuits 81 to 84 match with the information “1”. When a signal of information “0” is input from at least one of the XNOR circuits 81 to 84, an address comparator signal of information “0” is output. Table 2 shows the correspondence between input and output.

  The mode inverter 106 is configured by an element having XOR (exclusive OR) logic, and when the test mode signal indicates information “1”, the mode inversion is obtained by inverting the enable fuse cutting signal indicating the cutting state of the enable fuse 102. Device signal is output. Referring to FIG. 1, when the test mode signal is information “0”, the mode inverter 106a activates the address fuse group 10a used for redundancy relief. On the other hand, when the test mode signal is information “1”, the mode inverter 106 b activates the address fuse group 10 b in which the unique information is stored. Table 3 shows the correspondence between input and output. As shown in Table 3, the mode inverter signal of information “1” when the test mode signal is information “0” is a redundant cell activation signal for activating the address fuse group 10a. Further, the mode inverter signal of information “1” when the test mode signal is information “1” becomes a unique information activation signal for activating the address fuse group 10 b.

  When both the mode inverter signal and the address comparator signal indicate information “1”, the redundancy selector 110 sends a redundancy selector signal of information “1” to the output combiner 502, and the address selector A stop signal of information “1” is sent to 500. Further, the redundant cell 112a is selected by the multiplexer 604 instead of the memory cell specified by the address signal. On the other hand, if at least one of the mode inverter signal and the address comparator signal is information “0”, the stop signal is not sent to the address selector 500 and the redundancy of the information “0” is output to the output combiner 502. Send selector signal. Table 4 shows the correspondence between input and output.

  When the address selector 500 receives the stop signal of information “1” from the redundancy selector 110, the address selector 500 stops the address selection operation. On the contrary, if the stop signal is not received from the redundancy selector 110, the address in the main cell area 600 specified by the address signal is selected. Table 5 shows the operation of the address selector 500 with respect to the input.

  The output synthesizer 502 is composed of elements having OR logic, synthesizes two redundant selector signals from the redundant selectors 110a and 110b, and sends the result to the output switch 504 as a unique information detection signal. If at least one of the two redundant selector signals from the redundant selectors 110a and 110b is information “1”, the address fuse group 10 in which the unique information is stored matches the address signal, and the unique information is detected. The unique information detection signal becomes information “1”. If the unique information detection signal is information “0”, it indicates that the address signal and the unique information do not match.

  When the test mode signal is information “0”, the output switch 504 outputs a memory cell information signal indicating information on the selected memory cell or redundant cell in the main cell region 600 as data. On the other hand, when the test mode signal is information “1”, the unique information detection signal from the output synthesizer 502 is output as data. Table 6 shows the correspondence between input and output.

  Next, the redundancy test and processing performed in the wafer sorting process after the wafer process manufacturing process is completed will be described. Hereinafter, the semiconductor memory device is referred to as a chip.

  The operator sets the wafer on which the chip is mounted on the LSI tester, and causes the LSI tester to perform an operation test on all the memory cells in the main cell region 600. When the LSI tester finds a chip with a defective cell, it determines whether the chip can be redundantly repaired. If it is determined that the redundancy can be repaired, the redundant cell for repairing the defective cell and the fuse set 100 corresponding to the redundant cell are selected. Then, a fuse pattern for cutting the fuses of the address fuse group 10 is obtained by calculation corresponding to the address information of the defective cell. For all defective cells in the chip, set position information and fuse patterns for specifying the fuse set 100 are obtained for each defective cell.

  Further, when the chip unique information is input, the LSI tester obtains a fuse pattern corresponding to the unique information. Also, it is checked whether there is a fuse set 100 that is not used for redundant relief. If it is determined that there is a fuse set 100 that is not used for redundant relief, the set position information of the fuse set 100 is registered together with the fuse pattern of the unique information.

  Subsequently, the operator operates the LSI tester to call the fuse pattern 100a for redundancy relief and the fuse pattern 100b for storing the unique information and the respective set position information from the LSI tester. Input to the repair device. Then, the worker sets the wafer on which the chip is mounted on the repair device, and inputs an instruction to operate the repair device to instruct a fuse cutting process. The repair device cuts the fuse with a laser in accordance with the input set position information and the fuse pattern. In this embodiment, as shown in FIG. 1, the enable fuse 102a and the fuse 12a of the fuse set 100a are cut, and the fuse 12b of the fuse set 100b is cut.

  Next, the information reading operation of the memory cell in the semiconductor memory device after performing the redundancy repair and the storage of the unique information will be described. Here, it is assumed that information of the address “0100” of the defective cell is read.

  Since reading of information from the memory cell is a normal usage method, the test mode signal is in the OFF state, and the information of the test mode signal is “0”. The address signal is “0100”. The address comparator 108a sends the address comparator signal of information “1” to the redundancy selector 110a because the address signal and the fuse state read signal information match.

  Further, since the test mode signal of information “0” and the enable fuse cutting signal of information “1” are input to the mode inverter 106a, the mode inverter signal of information “1” is sent to the redundancy selector 110a.

  Since the redundancy selector 110a receives the mode inverter signal of information “1” and the address comparator signal of information “1”, the redundancy selector 110a sends the redundancy selector signal of information “1” to the output synthesizer 502. A stop signal “1” is sent to the address selector 500. When the address selector 500 receives a stop signal of information “1” from the redundancy selector 110a, the address selector 500 stops the address selection operation.

  Also, the redundancy selector 110a causes the multiplexer 604 to select the redundancy cell 112a instead of the memory cell specified by the address signal. As a result, the defective cell having the address “0100” is switched to the redundant cell 112 a, and the data of the redundant cell 112 a is input to the output switch 504 via the amplifier 608. On the other hand, since the test mode signal is information “0”, the output switch 504 outputs the memory cell information signal from the amplifier 608 as data instead of the input from the output synthesizer 502.

  Thus, if the memory cell at the address of the address signal is a defective cell, the information stored in the redundant cell is output as data. If the address signal and the information in the address fuse group 10 do not match, the memory cell in the main cell area is selected and the data of the memory cell is output. In addition, since the enable fuse 102b is not cut in the fuse set 100b that is not used for redundancy relief, the mode inverter signal of the mode inverter 106b connected to the fuse set 100b becomes information “0”, and the redundancy selector 110b Stay inactive.

  Next, an operation when reading unique information from the semiconductor memory device will be described. Here, an LSI tester having a socket board for electrical connection with terminals such as input pins and output pins of the semiconductor memory device and a computer for processing signals received from the semiconductor memory device via the socket board is used. Shall. Further, the LSI tester computer stores a program for reading out the unique information in advance.

  FIG. 3 is a flowchart for explaining a method for reading the unique information.

  As shown in FIG. 3, the LSI tester inputs a test mode signal to the mode inverters 106a and 106b and the output switch 504 (step 301). Since the test mode signal is turned on, the information of the test mode signal is “1”. Since the test mode signal of information “1” and the enable fuse cutting signal of information “0” are input to the mode inverter 106 b, the mode inverter 106 b sends the mode inverter signal of information “1” to the redundancy selector 110 b.

  On the other hand, the mode inverter signal of the mode inverter 106a corresponding to the fuse set 100a used for redundancy relief is information “0”. In this case, the redundancy selector 110a sends the redundancy selector signal of the information “0” to the output combiner 502 regardless of whether the information output from the address comparator 108a is “0” or “1”. To do. Therefore, the output synthesizer 502 receives the information “0” from the redundancy selector 110a regardless of the address signal information.

  While monitoring the output of the output switch 504, an address signal of information “0000” is input to the address comparators 108a and 108b (step 302). When the address signal is the information “0000”, the address comparator 108b determines that the address comparator signal of the information “0” is the redundant selector because the information from the signal from the fuse state reading circuit 104b does not match the address signal. To 110b. The redundancy selector 110 b sends a redundancy selector signal of information “0” to the output combiner 502. The output synthesizer 502 receives the information “0” signal from the redundancy selector 110b and outputs the unique information detection signal of information “0” in order to receive the information “0” signal from the redundancy selector 110a as described above. The data is sent to the switch 504. Since the test mode signal is information “1”, the output switch 504 outputs the unique information detection signal from the output combiner 502 as data. Then, it is determined whether or not the unique information detection signal output from the output synthesizer 502 is information “1” (step 303). Since the unique information detection signal at this time is information “0”, the address signal is counted up (step 304).

  When the address signal is counted up from the information “0000” by one count, the unique information detection signal is the information “0” as in the case where the address signal is the information “0000” when the address signal is the information “0001” to “0011”. "

  When the input address signal becomes the information “0100”, the information from the fuse state reading circuit 104b matches the information in the address signal, so that the address comparator 108b outputs the address comparator signal of the information “1”. The data is sent to the redundancy selector 110b. Since the redundancy selector 110b receives the information “1” signal from the mode inverter 106b and the information “1” signal from the address comparator 108b, the redundancy selector 110b outputs the information “1” redundancy selector signal as an output synthesizer. Send to 502. When the output synthesizer 502 receives the information “1” from the redundancy selector 110 b, the output synthesizer 502 sends a unique information detection signal of the information “1” to the output switch 504. The output switch 504 outputs a unique information detection signal of information “1” as data. If the unique information detection signal is information “1”, the LSI tester stores the address signal information “0100” at this time as unique information (step 305).

  It should be noted that since the address signal is information “0101” to “1111”, the unique information detection signal is information “0” as in the case where the address signal is information “0000”. In the flowchart shown in FIG. 3, the address signal is counted up by one count from the lowest address “0000”, but the address signal may be counted down by one count from the highest address “1111”. Moreover, you may start not only with the lowest address or the highest address but also with an intermediate address.

  In this embodiment, since the unique information is stored in the address fuse group 10b of the fuse set 100b that is not used for redundancy relief, when the address signal information matches the unique information, the information “1” is obtained as described above. The unique information detection signal is output as data. Therefore, it is possible to read the information of the address signal when the unique information detection signal becomes information “1” as the unique information of the chip.

  In addition, by using a fuse set that is not used for redundancy relief for storing unique information, it is not necessary to provide a special storage area, and an increase in chip area can be prevented.

  Further, the recording operation of the specific information can be included in the trimming process for switching the defective cell to the redundant cell, and the specific information can be stored in the chip without providing a new process.

  Further, by reading out unique information for identifying a chip from the semiconductor memory device, it is possible to track a defective chip and identify an illegal outflow chip.

  In the present embodiment, two fuse sets 100a and 100b are used as shown in FIG. 1, but the number of fuse sets 100 is not limited to two.

  The semiconductor memory device of this embodiment has an output switch 504 as shown in FIG. 1, but outputs a unique information detection signal separately from a data output pin for outputting information of a memory cell. The output switch 504 may be omitted.

  The present embodiment is applied to a semiconductor memory device having a main cell region of a cell array in which memory cell addresses are designated by row addresses and column addresses.

  The configuration of the semiconductor memory device of this embodiment will be described.

  FIG. 4 is a block diagram showing a configuration example of a main part of the semiconductor memory device of this embodiment. In addition, the same code | symbol is attached | subjected about the structure similar to FIG. 1, and the detailed description of the structure and operation | movement is abbreviate | omitted.

  In the main cell region 610 shown in FIG. 4, a plurality of memory cells whose addresses are specified by row addresses and column addresses are provided. Corresponding to the address selector 500 shown in FIG. 1, a row address selector 500a is provided on the row address side, and a column address selector 500b is provided on the column address side. Corresponding to the address driver 602 shown in FIG. 1, a row address driver 602a is provided on the row address side, and a column address driver 602b is provided on the column address side.

  Each of the redundant cells 112a and 112b is provided with a number of memory cells corresponding to the number of columns of the main cell region 610. Each of the redundant cells 112c and 112d is provided with a number of memory cells corresponding to the number of rows of the main cell region 610. This is for replacing defective cells in the main cell region 610 with redundant cells for each row or column in which defective cells occur.

  The fuse sets 100a and 100b correspond to the redundant cells 112a and 112b on the row address side, and the fuse sets 100c and 100d correspond to the redundant cells 112c and 112d on the column address side.

  The unique information read operation of this embodiment will be briefly described.

  When reading the unique information, first, for any one of the row address input and the column address, the input signals are counted up from the lowest address to the highest address in the same manner as in the first embodiment. Thereafter, for the other address, the input signal is counted up from the lowest address to the highest address in the same manner as in the first embodiment. The information of the address signal when the data output from the output switch 504 becomes the information “1” becomes the unique information.

  Although the output synthesizer 502 is provided in the configuration shown in FIG. 4, the output of the redundancy selector is collected in each row and column, and the row redundancy selector output pin and the column redundancy selection are separated from the normal data output pins. An output pin may be provided. In this case, the output synthesizer 502 may not be provided. In the present embodiment, four fuse sets 100a to 100d are used, but the number of fuse sets 100 is not limited to four.

  As described above, in the present embodiment, the same effect as that of the first embodiment can be obtained for the memory cell array in which the main cell region is composed of the row address and the column address.

  In the first and second embodiments, the output switch 504 is provided in the semiconductor memory device, but the output pin for outputting the unique information detection signal separately from the data output pin for outputting the memory cell information. , The output switch 504 may be omitted.

  The storage capacity for recording the unique information is not limited to 4 bits. Each circuit is not limited to the logic of the present embodiment as long as the output signal information with respect to the input signal information is the same as that described in the first embodiment.

  Further, although a fuse is used as a non-volatile memory element that stores information without supplying power, an element such as a flash memory or an EEPROM (Electrically Erasable and Programmable Read Only Memory) may be used instead of the fuse.

  Further, the configuration of the redundant cell may be a single cell configuration as in the first embodiment, or may be a so-called redundant line arranged in a straight line as in the second embodiment.

  Further, the fuse is not limited to a structure that can select either a cut state or a conductive state depending on whether or not it is cut by a mechanical processing means such as a laser. It may be a structure like an antifuse that allows one of two states to be selected depending on whether or not it is cut by electrical processing means.

1 is a block diagram illustrating a configuration example of a main part of a semiconductor memory device according to a first embodiment. It is a block diagram which shows one structural example of an address comparator. It is a flowchart for demonstrating the reading method of specific information. FIG. 6 is a block diagram illustrating a configuration example of a main part of a semiconductor memory device according to a second embodiment.

Explanation of symbols

10, 10a to 10d Address fuse group 11 to 14 Fuse 100, 100a to 100d Fuse set 102, 102a to 102d Enable fuse 104, 104a to 104d Fuse state reading circuit 106, 106a to 106d Mode inverter 108, 108a to 108d Address comparison 110, 110a to 110d Redundant selector 500 Address selector 502 Output combiner 504 Output switcher 600, 610 Main cell area 602 Address driver 604 Multiplexer 606 Write circuit 608 Amplifier

Claims (6)

In a semiconductor memory device having a plurality of memory cells and a redundant cell replacing a defective cell in the plurality of memory cells,
A non-volatile memory group consisting of a plurality of non-volatile memory elements for storing unique information which is different information for each semiconductor memory device or an address of the defective cell;
An enable nonvolatile memory element provided corresponding to the nonvolatile memory group and storing information for determining whether the information stored in the nonvolatile memory group is an address of the defective cell or the unique information When,
When a test mode signal for reading the unique information is input with reference to information stored in the enable nonvolatile memory element, a unique information activation signal for activating the nonvolatile memory group storing the unique information is generated. A mode inverter that sends out a redundant cell activation signal that activates a nonvolatile memory group in which the address of the defective cell is stored if the test mode signal is not input,
When the input address signal and the information in the non-volatile memory group match, if the signal received from the mode inverter is a unique information activation signal, the unique information detection is a signal indicating that the unique information has been detected. A redundancy selector for outputting a signal and outputting the information stored in the redundancy cell instead of the memory cell specified by the address signal when the signal received from the mode inverter is a redundancy cell activation signal; ,
A semiconductor memory device comprising: A plurality of the nonvolatile memory groups are provided,
Corresponding to the plurality of nonvolatile memory groups, a plurality of each of the enable nonvolatile memory element, the mode inverter, and the redundancy selector are provided,
An output synthesizer connected to the plurality of redundant selectors and outputting the unique information detection signal to the outside when the specific information detection signal is received from any one of the plurality of redundant selectors. The semiconductor memory device according to claim 1.   When connected to the output synthesizer and the test mode signal is input, the signal received from the output synthesizer is output to the outside, and when the test mode signal is not input, it is stored in the memory cell or the redundant cell. 3. The semiconductor memory device according to claim 2, further comprising an output switch that outputs the received information to the outside. Having a memory cell array in which the addresses of the memory cells are specified at row and column addresses;
The nonvolatile memory group is provided corresponding to each of the row and the column,
4. The semiconductor according to claim 1, wherein each of the enable nonvolatile memory element, the mode inverter, and the redundancy selector is provided corresponding to the nonvolatile memory group. 5. Storage device.   The semiconductor memory device according to claim 1, wherein the nonvolatile memory element is a fuse. A method for reading out the unique information from the semiconductor memory device according to claim 1,
Inputting a test mode signal for reading the unique information to the mode inverter;
Monitoring the output from the redundancy selector and changing the input address signal from the predetermined address to the upper or lower order by one count;
Reading the address signal as the unique information when the unique information detection signal is output from the redundant selector;
A method for reading information.

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