JP2006277774A - Information processor having branch prediction mechanism - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the speed of processing performance of an information processor by providing a device for effectively deleting a phantom entry. <P>SOLUTION: A phantom entry in entries of branch history is surely detected by using a flag provided for an execution control queue of branch instructions and phantoms for identifying the phantoms and a flag for detecting a mismatch between the start position of an instruction and a position at which a branch prediction is executed, and is deleted when it is not necessary. When an instruction that may generate discontinuity is present in a sequence of instruction execution, a deliberate phantom entry is generated and an instruction prefetch is allowed to be executed for it. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus employing a branch prediction mechanism (branch history or the like) for executing an instruction sequence including a branch at high speed, and more particularly to an entry deregistration method that adversely affects performance.

  In an information processing device that employs an advanced instruction processing method after the pipeline processing method, performance has been improved by speculatively processing subsequent instructions without waiting for the end of execution of one instruction. It was. Among them, if there is a branch instruction, whether or not the branch instruction branches, or in the case of branching, the instruction to be executed next cannot be input unless the instruction address of the branch destination instruction is determined. In order to solve this problem, a branch prediction mechanism has been introduced to predict the branch direction of a branch instruction or the branch destination instruction address, thereby further improving the performance. For example, Japanese Patent Laid-Open No. 6-89173 has obtained superior performance by having a branch prediction mechanism (branch history) independent of the cache memory.

However, with the increase in the branch history scale, there have been conspicuous cases where the contents deteriorated depending on the contents.
In particular, since the branch history is independent of the cache memory, TLB (Translation Lookaside Buffer), etc., even if the state of the instruction area is updated by updating the instruction sequence, the branch history is normally updated. Information is not reflected or is not reflected for all update cases. as a result,
-Another instruction is loaded at the instruction address where the branch instruction used to exist-Another program is dispatched to the logical space by changing the TLB, etc., and branch prediction is performed for instructions other than the branch instruction. This happens. Such an entry existing in the branch history is called a phantom entry.

FIG. 9 is a diagram schematically illustrating a mechanism in which phantom entry occurs.
The conventional branch history does not actively delete phantom entries, but replaces that occur when a new entry is registered. I expected.

  However, as shown in FIG. 9, there are a program A and a program B, and considering that the processor is executing them in parallel by time-sharing control, the program A is executed in some cases. In this case, a state occurs in which the program B is executed. In the case of FIG. 9, it is assumed that there is a branch instruction at address 1500 of program A. In this case, a branch prediction mechanism such as a branch history performs branch prediction when the address 1500 is detected. If only program A is executed, the instruction stored at address 1500 is a branch instruction, so it is correct to make a branch prediction, but at some point, instruction execution moves to program B as in time-sharing control. Assuming that the branch prediction mechanism such as the branch history does not wait for the instruction to be decoded and performs branch prediction only by detecting the address, the branch prediction is automatically made when address 1500 is detected. However, since program B is currently being executed, an add instruction that does not require branch prediction is stored at address 1500 as shown in FIG. Therefore, if the branch history does not hold the entry correctly, it is determined that the add instruction of the program B, which should not be predicted as such, is also a branch instruction of the program A, and branch prediction is performed.

  In instruction execution control, if branch prediction is performed even though it is not a branch instruction, processing for eliminating the inconsistency is required, which involves overhead. Therefore, if this phantom entry is not deleted as soon as it is found, the branch history that should have been developed for improving the performance is conversely accompanied by performance degradation. In particular, when the branch history entry capacity is small, the time required for erasure by the replace operation is short, but as the capacity and association level increase, the phantom entry remains and the problem becomes apparent. It was way.

  In order to solve such a situation, an object of the present invention is to provide an apparatus that effectively erases a phantom entry, and therefore, to realize an increase in processing performance of the information processing apparatus.

  According to a first information processing apparatus of the present invention, in an information processing apparatus having a branch prediction mechanism, determination means for determining whether or not a target instruction for which branch prediction is performed is a branch instruction, and the branch prediction is performed. Phantom deletion means for deleting an entry for branch prediction corresponding to the instruction stored in the branch prediction mechanism when it is determined that the target instruction is not a branch instruction.

  The second information processing apparatus according to the present invention is a case in which, in an information processing apparatus having a branch prediction mechanism, a queue unit that cuts out an instruction and stores it for execution, and branch prediction is performed on the instruction stored in the queue unit Detecting means for detecting whether or not the address position where the branch prediction is made is at the boundary of the instruction word stored in the queue means, and determining that the address position where the branch prediction is made is not at the boundary of the instruction word In such a case, a misalignment deleting unit that deletes an entry for branch prediction stored in the branch prediction mechanism, which is a basis for performing the branch prediction, is provided.

  According to a third information processing apparatus of the present invention, in an information processing apparatus having a branch prediction mechanism, an instruction that is not executed at high speed even if it is a branch instruction or an instruction that makes the instruction sequence discontinuous although it is not a branch instruction. Phantom target instruction detecting means for detecting, and phantom entry generating means for generating and adding an entry corresponding to the instruction detected by the phantom target instruction detecting means to an entry for branch prediction stored in the branch prediction mechanism , High-speed instruction processing is realized by performing instruction prefetch using an entry for branch prediction.

  According to the present invention, even if the phantom entry, which is an extra entry, is reliably deleted from the branch history entries stored in the branch prediction mechanism, even when the application is executed by the information processing device in a time-sharing manner, Incorrect branch prediction can be avoided. Therefore, it is possible to save the time required for making an erroneous branch prediction and improve the processing performance of the information processing apparatus.

  In addition, the information processing apparatus intentionally registers instructions that take a long time to process in the branch history as phantom entries, and performs prefetching of these instructions, thereby speeding up the execution of these instructions. In addition, the processing performance of the information processing apparatus can be improved.

  By using this method, the phantom entry can be surely deleted and the performance deterioration of the branch history can be avoided. Further, by actively utilizing this function, it is possible to perform control that provides an instruction prefetch effect even for a complicated control transfer instruction, which is useful for improving performance.

  Naturally, branch prediction is closely related to execution control of branch instructions. As a result of the branch processing, the branch control unit knows whether or not the branch prediction is successful, and has an information / update control structure for updating the branch history. This configuration has been put into practical use (see Japanese Patent Application Laid-Open No. 2000-282710).

  Here, a device that reports the success or failure of branch prediction to the branch prediction unit (branch history) by generating an entry corresponding to a branch predicted instruction in spite of not being a branch instruction in the branch control unit. Since this is described in Japanese Unexamined Patent Publication No. 2000-181710, this is utilized effectively.

Further, since normal branch history update is described in, for example, Japanese Patent Laid-Open No. 2000-172503, this is also effectively utilized.
Some apparatuses employ an instruction set in which the instruction length is not constant but variable (having a plurality of instruction lengths). In the case of a microarchitecture that employs a branch history on such an instruction set, there is a case where branch prediction is performed at a position different from the instruction boundary as shown in FIG. This is also a kind of phantom entry, but it refrains from more difficult problems from the above situation.

FIG. 1 is a diagram for explaining a case in which branch prediction occurs at an instruction boundary.
In the normal branch prediction described in FIG. 1A, branch prediction is performed at a boundary portion between instructions. However, when another program is loaded and the branch history is not updated as described in the prior art, branch prediction may be performed at a place other than the instruction boundary as shown in FIG. . This is because, in the previous program, when the branch instruction is in the portion indicated by the dotted line in FIG. 1B, after the next program is read, the boundary of the instruction of the previous program is not necessarily the subsequent program. This means that it will not always be a boundary between orders.

  In this case, the phantom entry on the corresponding branch history cannot be deleted unless information that can accurately restore the predicted position, such as an offset from the instruction boundary, is not stored.

  There are also instructions that change the instruction address, like branch instructions, such as instructions that always generate interrupts (software trap instructions). Since these instructions change the processor address and the like at the same time as changing the instruction address, they may not be operated at high speed only by the branch instruction control unit.

  If these special instructions can also be registered in the branch history, the branch history is indexed, so that the branch prediction destination fetch can be performed from the information, so the instruction executed in the instruction cache area is prefetched. Effect, and cash miss penalty can be reduced.

  As described above, even in an instruction that is not operated by the branch execution control unit, by using the phantom entry erasing method according to the embodiment of the present invention, there is no contradiction and an operation including prediction of another branch instruction is not hindered. It will be able to work.

FIG. 2 is a diagram showing an outline of the information processing apparatus according to the embodiment of the present invention.
In this embodiment, a superscalar type information processing apparatus can simultaneously process three instructions. In the instruction fetch unit, a maximum of three instructions are set in IWR0 to IWR2 (Instruction Word Register). In addition, there are three instruction word lengths of 1, 4 and 6 bytes for one instruction. However, an instruction with a length of 6 bytes is set only to IWR0 (otherwise, it goes to the next and subsequent cycles). Shall. Hereinafter, expressions in half word units may be entered (therefore, Half-Word is 1, 2, or 3 half words).

  Here, the branch instruction queue for branch processing is RSBR, and each queue on RSBR has an instruction address PC and a branch destination address TPC of each branch instruction, a BRHIS Hit tag that is branch prediction information, and Hit-Way tag information. There shall be. This configuration is the same as that described in Japanese Patent Laid-Open No. 2000-172503. In the present embodiment, Hit-Offset is further provided, which is indicated by an offset from the instruction address PC at the position where the branch is predicted. Therefore, if a branch instruction is normally predicted for a branch instruction, Hit-Offset indicates 0.

  However, unlike the embodiment of the present invention, in a certain RISC instruction set, the instruction word is always a constant value such as 4 bytes, and there is a boundary position guarantee that brings the instruction execution position to the instruction word boundary. Has been made. On such an instruction set, the event that the branch prediction position does not become an instruction word boundary does not occur (it can be made to occur intentionally, but there is no merit). Accordingly, since Hit-Offset is not necessary in an apparatus that implements such an instruction set, the application of this embodiment to such an instruction set should be modified as appropriate by those skilled in the art.

  In FIG. 2, IF-EAG (Instruction Fetch-Effective Address Generator), that is, the fetch address generator 10 calculates the address of the instruction to be fetched. The calculated address is input to the branch prediction unit 11 having a branch history (BRHIS) and the I-Cache, that is, the instruction cache 12. The branch prediction unit 11 outputs whether or not branch prediction is performed from the input address and, when branch prediction is performed, a predicted branch destination address. The predicted branch destination address is transferred to the fetch address generation unit 10 and input to the instruction cache 12 as it is. Further, a signal indicating that the branch prediction is performed, which is an output of the branch prediction unit 11, is input to the instruction input control unit 13.

  The instruction cache 12 extracts an instruction to be executed from the input address and inputs the instruction to the instruction input control unit 13. The instruction input control unit 13 instructs the instruction decoding method together with information on whether or not the branch instruction is predicted, and passes it to the IWR, that is, the instruction decoding unit 14. When the instruction is decoded by the instruction decoding unit 14, it is passed to each instruction processing unit depending on the content of the instruction. In particular, in the case of a branch instruction, an RSBR generation control unit that controls generation of the branch instruction queue RSBR. 15 is input. The branch instruction queue RSBR is generated in the branch processing unit 16, and branch instruction processing is sequentially performed.

  The result of the branch instruction processing of the branch processing unit 16 is transferred to the branch completion control unit 17 to determine whether the branch prediction has succeeded or failed, and the branch information that has been processed is stored in the BRHIS update control unit 18. To pass. The BRHIIS update control unit 18 updates the branch history of the branch prediction unit 11 based on the acquired branch information.

  When an instruction is set in IWR, the branch prediction result is divided and sent for each instruction at the same time. Then, Hit-Offset is passed to RSBR together with branch prediction information including Hit-Way associated with the branch prediction.

  FIG. 3 is a diagram illustrating a generation circuit example of BRHIS-Hit and Hit-Offset (MISALIGN Half-Word). The circuit of FIG. 3 is provided in the instruction input control unit 13 in the configuration of FIG.

  In this figure, the L1 HWm ILC n signal is a signal that means that the instruction word length of an instruction at a halfword distance m from the instruction cut-out start point (if it is an instruction boundary point) is n (n is In this case, it is one of 2, 4, and 6 and indicates the length of the used instruction word, and m is the number of halfwords (for example, 2 halfwords) from the instruction cutout position. ) As a unit). The L1 HIT HW p signal is a signal indicating that the branch predicted point is at the half word distance p from the instruction start point.

  Even when the branch prediction is not at the instruction boundary position, it is detected as Hit (SET IWRx HIT) of the corresponding instruction, and at the same time, a SET IWRx MISALIGN HW y signal is issued to determine that there is no instruction word boundary.

  That is, in the “for IWR0” circuit in the upper part of FIG. 3, if the logical value of L1 HIT HW 0 indicating that the instruction cut-out position is an instruction word boundary is input as true, it indicates that IWR0 has been hit. Meaning logical value of SET IWR0 HIT becomes true. Similarly, when the instruction word length is 4 or 6, there is an instruction at a halfword distance 0 from the instruction extraction position (L1 HW 0ILC 4, 6), and the branch predicted point is the instruction. When the half word distance is 1 from the cutout start point, the logical value of SET IWR0 HIT is set to true, and the logical value of SET IWR0 MISALIGN HW 1 indicating that the instruction word boundary is not reached at the half word distance 1 Becomes true. Similarly, when there is a branch predicted point at a halfword distance 2 from the instruction cutout start point (L1 HIT HW 2) and the instruction word length is 6, the instruction cutout position When there is an instruction at a halfword distance of 0, the logical value of SET IWR0 MISALIGN HW 2 indicating that misalignment is performed at a halfword distance of 2 (branch prediction is performed not at an instruction word boundary) is Become true. However, SET IWR0 HIT is true to indicate that branch prediction has been performed in any case.

As described above, when the signal of FIG. 3 is read, in the case of the “for IWR1” circuit,
1) When a branch is predicted at a halfword distance of 1, an instruction word length of 2 and an instruction is at a halfword distance of 0, a logical value of SET IWR1 HIT indicating that a branch prediction has been made, not a misalignment Becomes true.
2) If a branch is predicted at a halfword distance of 2, an instruction word length of 4 and an instruction at a halfword distance of 0, the logical value of SET IWR1 HIT is true instead of misalignment.
3) When a branch is predicted at a halfword distance of 2, an instruction word length is 2 and an instruction is at a halfword distance of 0, and an instruction word length is 4 and an instruction is at a halfword distance of 1 , The logical values of SET IWR1 HIT and SET IWR1 MISALIGN HW 1 become true (in this case, the first instruction has an instruction word length of 2 and the next instruction has an instruction word length of 4, and branch prediction is Shows what happens in the middle of the next instruction).
4) When a branch is predicted at a halfword distance of 3, an instruction word length of 4 and an instruction at a halfword distance of 0, and an instruction word length of 4 and an instruction at a halfword distance of 2 Assuming misalignment, the logical values of SET IWR1 HIT and SET IWR1 MISALIGN HW 1 are set to true.

Furthermore, in the “for IWR2” circuit,
1) When a branch is predicted at a halfword distance of 2, the instruction word length is 2 and there are instructions at halfword distances 0 and 1, the logical value of SET IWR2 HIT becomes true as a normal hit.
2) When a branch is predicted at a halfword distance of 3, an instruction word length is 2 and an instruction is at a halfword distance of 0, and an instruction word length is 4 and an instruction is at a halfword distance of 2, usually The logical value of SET IWR2 HIT becomes true.
3) A branch is predicted at a halfword distance of 3, and if an instruction with an instruction word length of 4 is present at a halfword distance of 0 and an instruction with an instruction word length of 2 is present at a halfword distance of 1, a normal hit is found. As a result, the logical value of SET IWR2 HIT becomes true.
4) A branch was predicted at a halfword distance of 4, and when an instruction with an instruction word length of 4 was found at a halfword distance of 0 and an instruction with an instruction word length of 4 was found at a halfword distance of 2, a normal hit was found. The logical value of SET IWR2 HIT is made true.
5) A branch is predicted at a halfword distance of 3, an instruction with an instruction word length of 2 at a halfword distance of 0, an instruction with an instruction word length of 2 at a halfword distance of 1, and a halfword distance of 2. If there is an instruction with an instruction word length of 4, it is assumed that a misalignment has occurred, and the logical values of SET IWR2 HIT and SET IWR2 MALIGN HW 1 are true.
6) A branch is predicted at a halfword distance of 4, an instruction word length of 2 at halfword distance 0, an instructionword length of 4 at halfword distance 1, and an instruction at halfword distance 3. If there is an instruction with a word length of 4, it is assumed that a misalignment has occurred, and the logical values of SET IWR2 HIT and SET IWR2 MISALIGN HW 1 are set to true.
7) A branch is predicted at a halfword distance of 4, an instruction word length of 4 at a halfword distance of 0, an instruction of a word length of 2 at a halfword distance of 2, and an instruction at a halfword distance of 3 If there is an instruction with a word length of 4, the logical values of SET IWR2 HIT and SET IWR2 MISALIGNWW 1 are set to true, assuming that misalignment has occurred.
8) A branch is predicted at halfword distance 5, an instruction word length 4 instruction at halfword distance 0, an instruction word length 4 instruction at halfword distance 2, an instruction at halfword distance 4 If there is an instruction with a word length of 4, the logical values of SET IWR2 HIT and SET IWR2 MISALIGN HW 1 are set to true.

These are passed to RSBR in combination with other branch prediction information tags. Details of the configuration passed to the RSBR in combination with other branch prediction information tags are known.
FIG. 4 is a diagram showing a configuration example of the branch instruction and phantom execution control queue RSBR. The RSBR in the same figure is provided in the branch processing unit 16 in FIG.

  In this configuration, a valid flag indicating the validity of an entry in the queue RSBR, a phantom-valid flag indicating whether or not the entry is a phantom entry, branch control information describing the address of a conditional branch, a branch condition, etc., and the address of an instruction for branch prediction The IAR, the instruction address TIAR at the branch destination, the Hit part for storing the SET IWRy HIT (where y is an integer identifying IWR) in FIG. 3, the Way part indicating the WAY of the branch history, and the misalignment in FIG. It consists of a Misalign-HW unit for storing the signal shown. Misalign-HW data is valid only when the RSBR entry is a phantom entry.

Note that the RSBR Phantom-Valid flag is set using the technique described in Japanese Patent Laid-Open No. 2000-181710.
When the branch process or phantom entry process is completed by RSBR, the completion report is sent to the branch history.

FIG. 5 is a diagram for explaining the operation for reporting the completion of branch execution. The circuit in FIG. 5 is provided in the branch completion control unit 17 in FIG.
FIG. 6 is a diagram illustrating a circuit example for generating an instruction signal for erasing an entry. The circuit of FIG. 6 is provided in the BRHIIS update control unit 18 of FIG.

  When the phantom entry processing is completed, the branch completion control circuit, together with BR COMP AS PHANTOM indicating that the instruction is a phantom entry, the instruction address BR COMP IAR <0:31> of the completed instruction, the WAY position where the BRHIS Hit is performed BR COMP HIT WAY <1: 0>, and BR COMP MISALIGN HW y (and other control flags as necessary) when it is misaligned are sent to the BRHIS update control unit.

  In FIG. 6, in the case of normal branch prediction, since it is predicted at the instruction boundary position, the hit entry position is BR COMP IAR <0:31>, but it is a phantom entry and a misalignment is detected. When the hit is detected, the original position of the entry that detected the hit is BR COMP IAR <0:31> + BR COMPMISALIGN HW y (where y is a halfword distance value and is an integer. This calculation is performed by y = 1). In this case, 2 is added). The erasing operation may be performed on the WAY designated by the BR COMP HIT WAY at the address position determined by this.

  If the instruction that happens to be misaligned is a branch instruction, BR COMP AS TAKEN (if the branch is established) or BR COMP AS NOT TAKEN (if the branch is not established) is sent and processed in the same way as normal branch processing. The Also in this case, update control may be performed on the address to which the misalignment information is added. Except for adding misalignment, this is the same as a conventionally known technique.

  The lower circuit in FIG. 6 is a table of BRHIS ERASE ENTRY for notifying that the branch history entry should be erased when one of BR COMP AS PHANTOM indicating normal erase conditions and phantom entries is input. Send a signal. Further, which branch history entry is to be deleted is calculated by the upper circuit of FIG. The address of BR COMP IAR is input, and the address of half word distance indicated by the value of y is added to the input address BR COMP IAR by the adder 20 by BR COMP MISALGIN HWy, and output as BRHIS UPDATE IAR.

  In this way, the phantom entry is specified, and an erase request signal is provided for the phantom entry to be deleted among the phantom entries in the branch history. This erasure request signal is handled in the same way as a conventional branch history entry erasure request, and the phantom entry is erased using the entry erasure means of the conventional branch history.

  As described above, the embodiment in which the phantom entry can be surely deleted has been shown. Conversely, an embodiment in which an instruction prefetch effect is found by intentionally creating a phantom entry is shown below.

FIG. 7 is a diagram illustrating a configuration for intentionally generating a phantom entry. This circuit is provided in the RSBR generation control unit 15 in FIG.
A complicated instruction (an instruction that is not executed at high speed even if it is a branch instruction) when the instruction is decoded and issued (the start of processing is indicated by IWRx Release). Or an instruction that makes the instruction address discontinuous (such as an instruction that generates software exception handling or an instruction that directly rewrites the program counter, etc.). If it is found, an entry equivalent to a phantom entry is generated in RSBR. Here, a tag (CTI field in FIG. 7) that can identify that the instruction is a phantom entry that is intentionally generated is registered, and this is notified to the BRHIIS update unit upon completion. In RSBR, the instruction address change destination is received from the processing unit of the complex instruction. Therefore, at the time of completion, the address to be changed is sent to BRHIIS as BR COMP TIAR.

  In FIG. 7, when the instruction is not a branch instruction but makes the instruction address discontinuous (IWRx CTI inst) or hits the branch history (IWRx BRHIS Hit) and the instruction is not a branch instruction (logical inversion of IWRx BRANCH) ), And when IWRx Release (instruction decoding ends and processing start permission) is issued, a flag is set in Phantom-Valid. Since the branch history is hit, the Hit flag is also flagged. When IWRx BRANCH and IWRx Release are input, the Valid flag is set as the entry is valid.

FIG. 8 is a diagram illustrating an example of a BRHIS update signal generation circuit when a phantom entry is intentionally generated. The circuit of FIG. 8 is provided in the BRHIIS update control unit 18 of FIG.
When the BR COMP AS PHANTOM notification with the tag is received, the BRHIS update control unit 18 does not delete the same operation as the normal branch prediction information update, that is, the entry already exists (BRHIS If it is “Hit”, it is updated as necessary, and if there is no entry (Not hit), a new entry is generated. Other controls such as the use of the BR COMP TIAR sent from the RSBR as the branch destination address used for creating / updating the entry are the same as in the prior art.

  In FIG. 8, if the branch history entry is a phantom entry (BR COMP AS PHANTOM) and a branch instruction (inverted logic of BR COMP CTI INST), the branch history entry is the same as the normal erase condition. A command (BRHIS ERASE ENTRY) for erasing data is output. Also, if the entry is a phantom entry (BR COMP AS PHANTOM) and not a branch instruction (BR COMP CTI INST), the branch history is not hit (inverted logic of BR COMP BRHIS HIT). An instruction to intentionally generate a phantom entry (BRHIS CREATE NEW ENTRY) is issued together with the new entry generation condition. If the branch history is hit and the entry is a phantom and it is not a branch instruction, an instruction (BRHIS UPDATE OLD ENTRY) to maintain the phantom entry is output.

  In this way, at the next instruction fetch corresponding to the instruction address, the entry is read and a branch prediction instruction fetch is performed. Even if this cannot be used immediately in the execution unit, since the instruction prefetch can be performed, an operation equivalent to a prefetch request is made to the cache, which has a performance improvement effect.

(Supplementary note 1) In an information processing apparatus having a branch prediction mechanism,
Stored in the branch prediction mechanism when it is determined that the target instruction for which branch prediction has been performed is a branch instruction, and when it is determined that the target instruction for which branch prediction has been performed is not a branch instruction Phantom deletion means for deleting an entry for branch prediction corresponding to the instruction,
An information processing apparatus comprising:
(Supplementary Note 2) In an information processing apparatus having a branch prediction mechanism,
Cue means for cutting out instructions and storing them for execution;
When branch prediction is performed for an instruction stored in the queue means, detection means for detecting whether the address position where the branch prediction is performed is at the boundary of the instruction word stored in the queue means;
A misalignment that deletes an entry for branch prediction stored in the branch prediction mechanism, which is a basis for performing the branch prediction, when it is determined that the address position where the branch prediction has been performed is not at the instruction word boundary Delete means,
An information processing apparatus comprising:
(Supplementary Note 3) When it is found that the address position of the instruction to be branch-predicted is different from the actual instruction boundary position, in the mechanism that performs the branch processing, specific information for specifying the position from the boundary position is The information processing apparatus according to appendix 2, wherein the information is stored and the entry for branch prediction included in the branch prediction mechanism is deleted using the specific information.
(Supplementary Note 4) In an information processing apparatus having a branch prediction mechanism,
A phantom target instruction detection means for detecting an instruction that is not executed at high speed even if it is a branch instruction, or an instruction that is not a branch instruction but makes the instruction sequence discontinuous;
Phantom entry generation means for generating and adding an entry corresponding to the instruction detected by the phantom target instruction detection means to an entry for branch prediction stored in the branch prediction mechanism;
An information processing apparatus that realizes high-speed instruction processing by performing instruction prefetch using an entry for branch prediction.
(Supplementary Note 5) A method for deleting an unnecessary entry among entries for branch prediction in an information processing apparatus having a branch prediction mechanism,
A determination step of determining whether or not the target instruction for which branch prediction has been performed is a branch instruction;
A phantom deletion step of deleting an entry for branch prediction corresponding to the instruction stored in the branch prediction mechanism when it is determined that the instruction subjected to the branch prediction is not a branch instruction;
A method comprising the steps of:
(Supplementary note 6) A method of deleting an unnecessary entry among entries for branch prediction in an information processing apparatus having a branch prediction mechanism,
A cue step to cut out the instruction set and store it for execution;
A detection step for detecting whether or not the address position where the branch prediction is performed is at the boundary of the instruction word stored in the queue step when branch prediction is performed for the instruction stored in the queue step;
A misalignment that deletes an entry for branch prediction stored in the branch prediction mechanism, which is a basis for performing the branch prediction, when it is determined that the address position where the branch prediction has been performed is not at the instruction word boundary Delete step,
A method comprising the steps of:
(Supplementary note 7) When it is found that the address position of the instruction to be branched is different from the actual instruction boundary position, the mechanism for performing the branch process stores offset information from the boundary position. The method according to appendix 6, wherein an entry for branch prediction included in the branch prediction mechanism is deleted using the offset information.
(Supplementary note 8) A method for high-speed instruction processing in an information processing apparatus having a branch prediction mechanism,
A phantom target instruction detection step for detecting an instruction that is not executed at high speed even if it is a branch instruction, or an instruction that is not a branch instruction but makes the instruction sequence discontinuous;
A phantom entry generation step of generating and adding an entry corresponding to the instruction detected by the phantom target instruction detection means to an entry for branch prediction stored in the branch prediction mechanism;
A method for realizing high-speed processing of an instruction by performing an instruction prefetch using an entry for branch prediction.

It is a figure explaining the case where branch prediction arises in the place which is not an instruction boundary. It is a figure which shows the outline of the information processing apparatus in embodiment of this invention. It is a figure which shows the example of a production | generation circuit of BRHIS-Hit and Hit-Offset (MISALIGN Half-Word). It is a figure which shows the example of a structure of the branch instruction and the phantom execution control queue RSBR. It is a figure explaining the operation | movement for reporting a branch execution completion. It is a figure which shows the example of a circuit which produces | generates the instruction | indication signal for entry deletion. It is a figure explaining the structure which produces | generates a phantom entry intentionally. It is a figure which shows the example of a production | generation circuit of the update signal of BRHIIS when producing | generating a phantom entry intentionally. It is a figure which illustrates roughly the mechanism in which a phantom entry arises.

Explanation of symbols

10 IF-EAG fetch address generation unit 11 BRHIIS branch prediction unit 12 I-CACHE instruction cache 13 instruction input control unit 14 IWRs instruction decoding unit 15 RSBR generation control unit 16 branch processing unit RSBRs
17 Branch completion control unit 18 BRHIIS update control unit 20 Adder

Claims (4)

In an instruction control device having branch prediction means for storing an entry for branch prediction,
A specific instruction detecting means for detecting a specific instruction for changing a subsequent instruction address by being executed although it is not a branch instruction;
Instruction queue means for storing instruction control information of instructions;
Having instruction queue generation control means for generating instruction control information stored in the instruction queue means;
When the specific instruction is detected by the specific instruction detection unit, the specific instruction is regarded as a branch instruction, and information for identifying the instruction is a specific instruction by the instruction queue generation control unit Storing in the instruction queue means;
An instruction control apparatus comprising: a changed address registering unit that stores an address of a subsequent instruction changed by execution of the specified instruction as an entry in the branch predicting unit when the specified instruction is executed.   The instruction control apparatus according to claim 1, wherein the instruction control apparatus performs instruction prefetch using the entry. In an instruction control method of an instruction control apparatus having a branch history for storing an entry for branch prediction,
A specific instruction detection step for detecting a specific instruction for changing a subsequent instruction address by being executed, although not a branch instruction;
In the specific instruction detection step, when a specific instruction is detected, the specific instruction is regarded as a branch instruction, and information for identifying that the instruction is a specific instruction is stored in the instruction queue. A specific instruction queue storage step;
An instruction control method comprising: a change address registration step of registering, in the branch history, an address of a subsequent instruction changed by execution of the specific instruction when the specific instruction is executed.   The instruction control method according to claim 3, wherein the instruction prefetch is performed using the entry.

Images