JP2006276138A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small sized display device in which a manufacturing process is simplified. <P>SOLUTION: A liquid crystal display device 1 comprises; a display section 20 in which one thin film transistor (TFT) 23 for one pixel is formed on an insulating transparent substrate 10; and a scanning circuit section 50 for outputting a scanning signal to the display section 20. The scanning circuit section 50 is equipped with a decoder circuit including a plurality of scanning line selection sections DC<SB>1</SB>to DC<SB>4</SB>. All scanning line selection sections DC<SB>1</SB>to DC<SB>4</SB>include TFTs 61 to 65 formed on the insulating transparent substrate 10. The TFTs 61 to 65 have the same structures as that of the TFT 23. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix drive type display.

An active matrix drive display includes a plurality of scanning lines, signal lines orthogonal to the scanning lines in plan view, and a plurality of thin film transistors disposed at intersections of the scanning lines and the signal lines. A plurality of pixel electrodes connected to each thin film transistor are provided on the substrate. A portion in which the pixel electrodes and the thin film transistors are arranged in a matrix form a display portion, and a video is displayed on the display portion by outputting a signal from the peripheral drive circuit to the display portion. The peripheral drive circuit includes a data driver that outputs a data signal to each signal line and a scan driver that outputs a scan signal to each scan line (see, for example, Patent Document 1). A single crystal silicon transistor is used as the scan driver, and in particular, the scan driver is a CMOS circuit in which an N-channel transistor and a P-channel transistor are combined. Further, the scan driver is formed as a chip separately or integrally with the data driver.
Japanese Patent Laid-Open No. 9-311656

  By the way, when the scan driver is made into a chip, the scan driver must be mounted on the substrate by a COG (Chip On Glass) method. Therefore, a space for mounting the scanning driver must be secured on the substrate, and the display becomes large.

  Further, since amorphous silicon is used for the thin film transistor in the display portion, it is necessary to manufacture the thin film transistor in a separate process from the transistor of the scan driver including single crystal silicon. In addition, since the scan driver is a CMOS circuit, a P-channel transistor patterning step and an N-channel transistor patterning step are required for manufacturing the scan driver, and a completed scan driver mounting step is also required. And Therefore, many processes are required for manufacturing the display.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a miniaturized display that can simplify the manufacturing process.

  In order to solve the above problems, the invention according to claim 1 includes a plurality of scanning lines on a substrate, a scanning circuit unit connected to the plurality of scanning lines and outputting a scanning signal to the scanning lines, and the substrate In the display area, the scanning circuit unit includes a plurality of first switching elements connected to each of the plurality of scanning lines and driven by the scanning signal. And a decoder circuit having a plurality of scanning line selection sections that supply scanning signals to the plurality of scanning lines, each of the plurality of scanning line selection sections being a semiconductor made of the same material as the first switching element. It includes a plurality of second switching elements having layers.

  According to the first aspect of the present invention, since the plurality of second switching elements and the plurality of first switching elements in the display region have the same material semiconductor layer, the plurality of first switching elements in the display region are formed on the substrate. A plurality of second switching elements can be formed at the same time as the above formation. Therefore, the display manufacturing process can be simplified.

  In addition, since the plurality of second switching elements included in the scanning line selection unit constituting the decoder circuit included in the scanning circuit unit is formed on the substrate, it is not necessary to separately manufacture a chip-type scanning driver, Furthermore, it is not necessary to mount a chip-type scan driver. Therefore, the display manufacturing process can be simplified, and the display can be further downsized.

  According to a second aspect of the present invention, in the display according to the first aspect, the semiconductor layer is made of amorphous silicon.

  According to the second aspect of the present invention, the semiconductor layers of the first plurality of switching elements formed in the display region and the plurality of second lines included in the scanning line selection unit constituting the decoder circuit included in the scanning circuit unit. Since both of the semiconductor layers of the switching elements are made of amorphous silicon, the patterning of these transistors can be simplified. Therefore, the manufacturing process of the display can be simplified.

  According to a third aspect of the present invention, in the display according to the first aspect, the semiconductor layer is made of polysilicon.

  According to a fourth aspect of the present invention, in the display according to the first aspect, the semiconductor layer is made of single crystal silicon.

  According to a fifth aspect of the present invention, in the display according to any one of the first to fourth aspects, the semiconductor layer is an N-type semiconductor.

  According to a sixth aspect of the present invention, in the display according to any one of the first to fourth aspects, the semiconductor layer is a P-type semiconductor.

  According to a seventh aspect of the present invention, in the display according to any one of the first to sixth aspects, the decoder circuit includes a first power supply line to which a first constant potential is supplied, and the first constant voltage. A second power supply line to which a second constant potential different from the potential is supplied, and the plurality of second switching elements include a precharge switching element connected to the first power supply line, And a discharge switching element connected to the second power supply line.

  According to an eighth aspect of the present invention, in the display according to the seventh aspect, the display includes control means for controlling the plurality of second switching elements, and the display includes the plurality of second switching elements. Control means for controlling, the control means turning off the discharge switching elements of all the scanning line selection units included in the decoder circuit, and pre-setting all the scanning line selection units included in the decoder circuit. By turning on the charge switching element, a precharge operation for accumulating charges from the first power supply line to all the scan line selection units is performed, and then the precharge switching elements of all the scan line selection units And the discharge switch of the scanning line selection unit connected to the unselected scanning line among the plurality of scanning lines is turned off. By turning on the chucking element, a discharge operation is performed to discharge the charge from the scanning line selection unit to the second power supply line, and the scanning signal is output only to the scanning line selected from the plurality of scanning lines. It is characterized by doing.

  According to a ninth aspect of the present invention, in the display according to the seventh aspect, the plurality of second switching elements further include a signal output switching element connected to one of the plurality of scanning lines, and the scanning. The line selection unit includes a capacitor for accumulating charges on a wiring connecting the precharge switching element and the signal output switching element.

  According to a tenth aspect of the present invention, in the display according to the ninth aspect, the display includes a control unit that controls the plurality of second switching elements, and the control unit includes all the control circuits included in the decoder circuit. By turning off the discharge switching element and the signal output switching element of the scanning line selection unit and turning on the precharge switching elements of all the scanning line selection units included in the decoder circuit, the first power supply A precharge operation for accumulating charges in all the scanning line selection units and the capacitors from a line, and then turning off precharge switching elements in all the scanning line selection units to select among the plurality of scanning lines. By turning on the discharge switching element of the scanning line selection unit connected to the scanning line that is not Performing a discharge operation for discharging the charges from the capacitance of the scanning line selection unit and the scanning line selection unit to the second power supply line, turning on the signal output switching elements of all the scanning line selection units; The scanning signal is output only to the scanning line selected from the scanning lines.

  According to an eleventh aspect of the present invention, in the display according to any one of the first to tenth aspects, the decoder circuit is a NOR type.

  The invention according to claim 12 is the display according to any one of claims 1 to 11, wherein each of the first plurality of switching elements and the plurality of second switching elements has an inverted stagger structure. It is a transistor.

  The invention according to claim 13 is the display according to any one of claims 1 to 11, wherein each of the first plurality of switching elements and the plurality of second switching elements is a transistor having a coplanar structure. It is characterized by being.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to simplify the manufacturing process of a display, a display can be reduced in size.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

  FIG. 1 is a perspective view of the liquid crystal display 1. As shown in FIG. 1, the liquid crystal display 1 includes a liquid crystal display panel 2 and an LSI chip 3 mounted on the liquid crystal display panel 2.

  The liquid crystal display panel 2 includes a display unit 20 on which video is displayed and a scanning circuit unit 50 provided on the right side of the display unit 20. FIG. 2 is a schematic diagram showing the liquid crystal display 1 together with the circuit configuration of the display unit 20. As shown in FIG. 2, in the display unit 20, a plurality of scanning lines 21 extending in the horizontal direction are formed on the insulating transparent substrate 10, and the signal lines 22 insulated from the scanning lines 21 are viewed in plan view. Thus, the insulating transparent substrate 10 is formed so as to be orthogonal to the scanning line 21. A thin film transistor 23 is disposed at each intersection of the scanning line 21 and the signal line 22, and a pixel electrode 24 is disposed in each surrounding region surrounded by the scanning line 21 and the signal line 22. Pixel electrodes 24 are arranged in a matrix in the display unit 20. The gates of a plurality of thin film transistors 23 arranged in a line in the horizontal direction are connected to a common scanning line 21, and one of the sources and drains of the plurality of thin film transistors 23 arranged in a line in the vertical direction is connected to a common signal line 22. The other of the source and drain of the thin film transistor 23 is connected to the pixel electrode 24. The counter substrate 11 (shown in FIG. 1) on which the counter common electrode is formed is opposed to the insulating transparent substrate 10 on which the scanning lines 21, the signal lines 22, the thin film transistors 23, the pixel electrodes 24, and the like are formed. The display unit 20 of the liquid crystal display panel 2 is configured by sealing the liquid crystal between the insulating transparent substrate 10 and the insulating transparent substrate 10.

  The LSI chip 3 shown in FIG. 1 is mounted on the insulating transparent substrate 10 by the COG (Chip On Glass) method, and is connected to the bus line 51 connected to the signal line 22 and the scanning circuit unit 50. The LSI chip 3 includes a data driver 52 and a gate controller 53, and the gate controller 53 includes a power supply unit 54 that supplies constant voltage power to the scanning circuit unit 50. A data signal is output from the data driver to each signal line 22. The gate controller 53 outputs a constant voltage signal and a gate control signal from the power supply unit 54 to the bus wiring 51, and these signals are decoded by the decoder circuit of the scanning circuit unit 50, and a scanning signal is sent to each scanning line 21. Is output.

  The thin film transistor 23 is a three-terminal switching element. The thin film transistor 23 has a semiconductor layer between a drain and a source. The semiconductor layer of the thin film transistor 23 is made of amorphous silicon. The scanning line 21, the signal line 22, the thin film transistor 23, the pixel electrode 24, and the like are patterned by appropriately performing a vapor deposition method, a photoresist method, an etching method, or the like.

FIG. 3 is a schematic diagram of the scanning circuit unit 50. Scanning circuit 50, n (where, n ≧ 2) for transmitting a bit signal S ₁ to S _n present and the address signal lines AL ₁ ~AL _n of the inverted bit is an inverted signal of the bit signal S ₁ to S _n signals iS ₁ n the inverted address signal line transmitting ~IS _n IAL ₁ ~IAL _n and, one the high voltage power supply line HL that the high voltage V _GH is supplied, a lower voltage lower than the high voltage V _GH one and a low voltage power supply line LL to V _GL is supplied, one enable signal line EL of transmitting the enable signal OE, one and the precharge signal line PL for transmitting the pre-charge signal pRE, each scan A decoder circuit having _m scan line selectors DC _{1 to} DC m connected to the line 21; The bus wiring 51 in FIG. 2 is composed of at least these 2n + 4 wirings. Here, m is the number of scanning lines 21 in the display unit 20 and satisfies m ≦ 2 ⁿ .

In the present embodiment, n is set to 2 and m is set to 4 in order to simplify the description. The numbers n and m are not particularly limited, and may be any number that satisfies m ≦ 2 ⁿ .

FIG. 4 is an equivalent circuit diagram of the scanning line selection units DC _{1 to} DC ₄ included in the NOR type decoder circuit. As shown in FIG. 4, each of the scanning line selection units DC _{1 to} DC _{4 includes} five thin film transistors 61 to 65 and a capacitor 66. The thin film transistor 61 is a discharge switching element, the thin film transistor 64 is a precharge switching element, and the thin film transistor 65 is a signal output transistor.

  These thin film transistors 61 to 65 are formed on the insulating transparent substrate 10 around the display unit 20 (specifically, on the right side of the display unit 20), and any of the thin film transistors 61 to 65 is the thin film transistor 23 in the display unit 20. It has the same structure as

  Specifically, the thin film transistors 61 to 65 each have a semiconductor layer between the drain and the source. However, the semiconductor layers of any of the thin film transistors 61 to 65 are made of amorphous silicon like the semiconductor layer of the thin film transistor 23.

  Each thin film transistor 61 to 65 has the same layer structure as the thin film transistor 23. For example, when the thin film transistor 23 has an inverted staggered structure, the thin film transistors 61 to 65 also have an inverted stagger structure. In the case of a mold structure, the thin film transistors 61 to 65 also have a coplanar structure. Here, the formation widths of the thin film transistors 61 to 65 and the gates of the thin film transistors 23 when viewed in plan are not necessarily the same, and the formation width is suitable for each of the scanning circuit unit 50 and the display unit 10. Can do.

  When the thin film transistor 23 is an N-channel transistor, all the thin film transistors 61 to 65 are also N-channel transistors. When the thin film transistor 23 is a P-channel transistor, all the thin film transistors 61 to 65 are all. This is a P-channel transistor. Note that an N-channel transistor is a transistor whose semiconductor layer is an N-type semiconductor, and a P-channel transistor is a transistor whose semiconductor layer is a P-type semiconductor.

  The thin film transistor 23 is patterned by appropriately performing a vapor deposition method, a photoresist method, an etching method, and the like. The thin film transistors 61 to 65 are patterned at the same time and in the same process as the thin film transistor 23. is there. Therefore, when manufacturing the liquid crystal display 1, a manufacturing process can be simplified.

  Note that the thin film transistors 61 to 65 may not pattern the thin film transistor 23 at the same time, and the thin film transistors 61 to 65 may be patterned before or after the patterning of the thin film transistor 23. In this case, the patterning of the thin film transistor 23 and the patterning of the thin film transistors 61 to 65 are continued.

As described above, since the thin film transistors 61 to 65 are formed around the display unit 20, the scanning line selection units DC _{1 to} DC ₄ included in the decoder circuit included in the scanning circuit unit 50 are configured. There is no need to manufacture a separate type scan driver, and there is no need to mount a chip type scan driver on the insulating transparent substrate 10. Therefore, the manufacturing process of the liquid crystal display 1 can be simplified, and the liquid crystal display 1 can be further downsized.

In any of the scanning line selection units DC _{1 to} DC ₄ , the gate of the thin film transistor 61 is used as the enable signal input unit 67, and one of the source and drain of the thin film transistor 61 is used as the low voltage input unit 68. Is the bit signal input unit 69, the gate of the thin film transistor 62 is the bit signal input unit 70, the gate of the thin film transistor 64 is the precharge signal input unit 71, and one of the source and drain of the thin film transistor 64 is the high voltage input. The gate of the thin film transistor 65 is an enable signal input unit 73, and one of the source and drain of the thin film transistor 65 is a signal output unit 74.

In any of the scanning line selection units DC _{1 to} DC ₄ , the other of the source and drain of the thin film transistor 61 is one of the source and drain of the thin film transistor 62 and one of the source and drain of the thin film transistor 63. Connected with. In any of the scanning line selection units DC _{1 to} DC ₄ , the other of the source and drain of the thin film transistor 62 and the other of the source and drain of the thin film transistor 63 are the other of the source and drain of the thin film transistor 64 and The other of the source and drain of the thin film transistor 65 and the electrode of the capacitor 66 are connected. In any of the scanning line selection units DC _{1 to} DC ₄ , the other electrode of the capacitor 66 is grounded.

As shown in FIG. 3, in any of the scanning line selection units DC _{1 to} DC ₄ , the enable signal input unit 67 and the enable signal input unit 73 are connected to the enable signal line EL, and the precharge signal input unit 71 is precharged. Connected to the signal line PL, the high voltage input unit 72 is connected to the high voltage power supply line HL, and the low voltage input unit 68 is connected to the low voltage power supply line LL.

In the case of the scanning line selection unit DC ₁ , the bit signal input unit 69 is connected to the address signal line AL ₁ , the bit signal input unit 70 is connected to the address signal line AL ₂ , and the signal output unit 74 is connected to the first row. It is connected to the scanning line 21.

When the scan line selector DC _2, the bit signal input unit 69 is connected to the inverted address signal lines IAL _1, bit signal input unit 70 is connected to the address signal lines AL _2, the signal output section 74 is the second row Are connected to the scanning line 21.

In the case of the scanning line selection unit DC ₃ , the bit signal input unit 69 is connected to the address signal line AL ₁ , the bit signal input unit 70 is connected to the inverted address signal line IAL ₂ , and the signal output unit 74 is in the third row. Are connected to the scanning line 21.

In the case of the scanning line selection unit DC ₄ , the bit signal input unit 69 is connected to the inverted address signal line IAL ₁ , the bit signal input unit 70 is connected to the inverted address signal line IAL ₂ , and the signal output unit 74 has three rows. It is connected to the scanning line 21 of the eye.

The address signal lines AL _{1 to} AL ₂ , the inverted address signal lines IAL _{1 to} IAL ₂ , the high voltage power supply line HL, the low voltage power supply line LL, the enable signal line EL, and the precharge signal line PL are connected to the LSI chip via the bus wiring 51. 3 is connected.

The power supply unit 54 included in the gate controller 53 built in the LSI chip 3 applies the high voltage V _GH to the high voltage power line HL and the low voltage V _GL to the low voltage power line LL. The gate controller 53 outputs the bit signal S ₁ to the address signal line AL ₁ , outputs the inverted bit signal IS ₁ to the inverted address signal line IAL ₁ , outputs the bit signal S ₂ to the address signal line AL ₂ , and inverts it The bit signal IS ₂ is output to the inverted address signal line IAL ₂ , the enable signal OE is output to the enable signal line EL, and the precharge signal PRE is output to the precharge signal line PL. An inverter 81 and an inverter 82 that invert the bit signal S ₁ and the bit signal S ₂ , respectively, are provided in the gate controller 53.

FIG. 5 shows the timing of the bit signal S ₁ , the bit signal S ₂ , the enable signal OE, and the precharge signal PRE. The bit signal S ₁ is periodically switched between low and high, and the cycle of the bit signal S ₁ is 2T. The bit signal S ₂ is periodically switched between low and high, and the cycle of the bit signal S ₂ is 4T. The enable signal OE periodically switches between low and high, and the cycle of the enable signal OE is T, but the initial phase of the enable signal OE is T / 4 with respect to the initial phase of the bit signal S ₁ and the bit signal S _2. It's off. The precharge signal PRE is a signal that becomes a high-level pulse every period T.

A bit signal S ₁ , a bit signal S ₂ , an enable signal OE and a precharge signal PRE as shown in FIG. 5 are input to the scanning line selection unit DC ₁ . Further, the inverted bit signal IS ₁ , the bit signal S ₂ , the enable signal OE and the precharge signal PRE are input to the scanning line selection unit DC ₂ . The bit signal S ₁ , the inverted bit signal IS ₂ , the enable signal OE, and the precharge signal PRE are input to the scanning line selection unit DC ₃ . The inverted bit signal IS ₁ , the inverted bit signal IS ₂ , the enable signal OE, and the precharge signal PRE are input to the scanning line selection unit DC ₄ .

The operation of the scanning line selection units DC _{1 to} DC ₄ will be described. When the precharge signal input unit 71 becomes high level at the beginning of the cycle, the thin film transistor 64 is turned on, so that holes flow into the scanning line selection unit via the high voltage power supply line HL. The inflowing holes are accumulated in the scanning line selection unit including the capacitor 66, and the inside of the scanning line selection unit becomes a high voltage (precharge). At this time, when both the bit signal input unit 69 and the bit signal input unit 70 are at a low level, both the thin film transistor 62 and the thin film transistor 63 are turned off, so that the thin film transistor 73 and the thin film transistor inside the scanning line selection unit Only the portion sandwiched between 62 and the thin film transistor 63 has a high voltage. On the other hand, when at least one of the bit signal input unit 69 and the bit signal input unit 70 is at a high level, at least one of the thin film transistor 62 and the thin film transistor 63 is turned on. The portion sandwiched between the thin film transistors 61 becomes a high voltage. After that, when the precharge signal input unit 71 becomes low level and then the enable signal input units 67 and 73 become high level, when both the bit signal input unit 69 and the bit signal input unit 70 are low level, the capacitor The holes accumulated in 66 are not discharged to the low voltage power supply line LL through the low voltage input unit 68, and the high voltage due to the first precharge is held inside the scan selection unit, so that the signal output unit 74 Become high level. On the other hand, when at least one of the bit signal input unit 69 and the bit signal input unit 70 is at a high level, holes accumulated in the scanning line selection unit including the capacitor 66 are low-voltage via the low voltage input unit 68. Since the power supply line LL is discharged and the inside of the scanning line selection unit becomes a low voltage (discharge), the signal output unit 74 becomes a low level.

Therefore, as shown in FIG. 5, in the first cycle, the bit signal S ₁ and the bit signal S ₂ are both at the low level, so that the bit signal input of the scanning line selection unit DC ₁ connected to the address signal line AL ₁ is performed. The bit signal input unit 70 of the scanning line selection unit DC ₁ connected to the unit 69 and the address signal line AL ₂ is supplied with low level bit signals S ₁ and S ₂ , and the enable signal OE and the precharge signal PRE. scanning signals X ₁ from the scan line selector DC ₁ is output at a high level in the first row of the scanning lines 21 by. On the other hand, since at least one of the bit signal input section 69 or 70 of the scan line selector DC ₂ to DC ₄ is connected to the inverted address signal line IAL ₁ or IAL _2, bit scan line selector DC ₂ to DC ₄ The high-level inverted bit signal IS ₁ or IS ₂ is input to at least one of the signal input units 69 or 70, and the scanning signals X ₂ from the scanning line selection units DC _{2 to} DC _{4 are} received by the enable signal OE and the precharge signal PRE. to X ₄ is the a both low level are outputted respectively 2-4 row scanning line 21.

In the next cycle, since the bit signal S ₁ is at the high level and the bit signal S ₂ is at the low level, only the scanning signal X ₂ from the scanning line selection unit DC ₂ becomes the high level, and the scanning line 21 in the second row. The remaining scanning signals X ₁ , X ₃ and X ₄ are all at a low level and are output to the scanning lines 21 in the first, third and fourth rows, respectively. In the subsequent third cycle, only the scanning signal X ₃ becomes high level and in the fourth cycle, only the scanning signal X ₄ becomes high level and is output to the scanning lines 21 in the third row and the fourth row, respectively.

As shown in FIG. 5, the scanning signal X ₁ to the scanning signal X ₄ sequentially become high level in synchronization with the enable signal OE becoming high level. That is, the scanning signal X ₁ becomes high level in the first cycle, the scanning signal X ₂ becomes high level in the next cycle, the scanning signal X ₃ becomes high level in the next cycle, and in the next cycle. scanning signal X ₄ becomes high level. After the scanning signal X ₄ becomes high level, the scanning signal X ₁ becomes high level again, and thereafter, the scanning signal X ₁ to the scanning signal X ₄ sequentially repeat high level. Sequential scanning is possible.

The signal a ₁ shown in FIG. 5 represents the voltage of one electrode of the capacitor 66 of the scanning line selection unit DC ₁ , and the signal a ₂ represents the voltage of one electrode of the capacitor 66 of the scanning line selection unit DC _2. The signal a ₃ represents the voltage of one electrode of the capacitor 66 of the scanning line selection unit DC ₃ , and the signal a ₄ represents the voltage of one electrode of the capacitor 66 of the scanning line selection unit DC ₄ .

  The present invention is not limited to the above embodiment, and various improvements and design changes may be made without departing from the spirit of the present invention.

  In the above embodiment, both the thin film transistor 23 and the thin film transistors 61 to 65 have the semiconductor layer made of amorphous silicon. On the other hand, the semiconductor layer of the thin film transistor 23 and the semiconductor layers of the thin film transistors 61 to 65 may both be made of polysilicon or single crystal silicon.

Further, each of the scanning line selection units DC _{1 to} DC ₄ may have a configuration in which the thin film transistor 65 and the capacitor 66 are omitted. In this case, the precharge signal PRE becomes high level at the beginning of the cycle, and the scanning line selection unit is precharged and the inside of the scanning line selection unit becomes a high voltage. The signal output unit 74 of the scanning line selection unit becomes high level. At this time, each scanning line 21 is at a high level. After that, when the precharge signal PRE becomes a low level and then the enable signal OE becomes a high level, one scanning line selection in which both the bit signal input unit 69 and the bit signal input unit 70 of the scanning line selection units become a low level. Since the part is not discharged, the signal output part 74 remains at the high level. On the other hand, the remaining scanning line selection units are discharged, the internal voltage of the scanning line selection unit becomes low, and the signal output unit 74 becomes low level, so that only one scanning line 21 can be selected as high level. it can.

In the above embodiment, the two thin film transistors 62 and 63 are connected in parallel between the thin film transistor 61 and the thin film transistor 65, so that the scanning line selection units DC _{1 to} DC ₄ of the NOR type 2-bit decoder circuit are provided. The four scanning lines 21 are sequentially selected by decoding the two-bit signals of the bit signal S ₁ and the bit signal S _2. However, when the NOR-type n-bit decoder circuit is used, scanning is performed. What is necessary is just to connect n thin film transistors (these thin film transistors have the same structure as the thin film transistor 23) in parallel between the thin film transistors 61 and 65 included in the line selection units DC _{1 to} DC _m , respectively. In this case, any one of n pairs of address signal lines and inverted address signal lines and a gate formed on any one of n thin film transistors are connected to all scanning line selection units. _One- to-one connection is made so that the combinations do not overlap in DC _{1 to} DC _m , and the bit signal S _i input to the i-th address signal line AL _i satisfying i ≦ n is changed to low and high in the cycle 2 ⁱ T. By switching, a maximum of 2 ⁿ scanning lines 21 can be sequentially selected. If n = 8, a maximum of 256 scanning lines 21 can be sequentially selected with 8 bits of bit signal S ₁ to bit signal S ₈ . Therefore, for example, when 240 scanning lines 21 are scanned, the number of wirings required for the decoder circuit included in the scanning circuit unit 50 includes the address signal lines AL _{1 to} AL ₈ , the address signal lines IAL _{1 to} IAL ₈ , and the high voltage. The power supply line HL, the low voltage power supply line LL, the enable signal line EL, and the precharge signal line PL are 20 in total, and the area occupied by the wiring in the scanning circuit unit 50 is much larger than the mounting area of the conventional scanning driver. Few.

  In the above embodiment, the scanning circuit unit 50 is provided on the right side of the display unit 20, but may be provided on the lower side, upper side, or left side of the display unit 20. Further, the scanning circuit unit 50 may be equally divided into at least two regions among the lower side, the upper side, the left side, and the right side of the display unit 20.

  Moreover, in the said embodiment, although this invention was applied to the liquid crystal display 1, in the display part (for example, the electroluminescent display which used the electroluminescent element as a pixel) in which the 1 or several thin-film transistor was provided per pixel in the display part. The present invention may be applied. Also in such a display, a scanning circuit unit in which a plurality of thin film transistors are combined is formed on the substrate on which the display unit is formed and around the display unit. The thin film transistor has the same structure as that of the thin film transistor.

1 is a perspective view of a liquid crystal display 1 to which the present invention is applied. 1 is a schematic view of a liquid crystal display 1. FIG. 2 is a schematic diagram of a scanning circuit unit 50. FIG. FIG. _{3 is} an equivalent circuit diagram of scanning line selection units DC _{1 to} DC ₄ . ₄ is a timing chart of bit signals S ₁ and S ₂ , scanning signals X _{1 to} X ₄ , an enable signal OE, and a precharge signal PRE.

Explanation of symbols

1 Liquid crystal display 10 Insulating transparent substrate (substrate)
20 Display Unit 23 Thin Film Transistor (Transistor of Display Unit)
61-65 Thin film transistors (transistors in the scanning circuit)
50 Scanning circuit section

Claims (13)

A plurality of scanning lines on the substrate, a scanning circuit unit connected to the plurality of scanning lines and outputting a scanning signal to the scanning lines, and connected to each of the plurality of scanning lines in the display region of the substrate, In a display having a plurality of first switching elements driven by a scanning signal,
The scanning circuit unit includes a decoder circuit having a plurality of scanning line selection units connected to each of the plurality of scanning lines and supplying a scanning signal to the plurality of scanning lines,
Each of the plurality of scanning line selection units includes a plurality of second switching elements each having a semiconductor layer made of the same material as the first switching element.   The display according to claim 1, wherein the semiconductor layer is made of amorphous silicon.   The display according to claim 1, wherein the semiconductor layer is made of polysilicon.   The display according to claim 1, wherein the semiconductor layer is made of single crystal silicon.   The display according to claim 1, wherein the semiconductor layer is an N-type semiconductor.   The display according to claim 1, wherein the semiconductor layer is a P-type semiconductor. The decoder circuit includes a first power supply line to which a first constant potential is supplied, and a second power supply line to which a second constant potential different from the first constant potential is supplied,
The plurality of second switching elements include a precharge switching element connected to the first power supply line and a discharge switching element connected to the second power supply line. Item 7. The display according to any one of Items 1 to 6. The display includes control means for controlling the plurality of second switching elements,
The control means turns off the discharge switching elements of all the scanning line selection units included in the decoder circuit, and turns on the precharge switching elements of all the scanning line selection units included in the decoder circuit. Thus, a precharge operation for accumulating charges from the first power supply line to all the scan line selection units is performed, and then the precharge switching elements of all the scan line selection units are turned off, and the plurality of scans are performed. By turning on a discharge switching element of a scanning line selection unit connected to a scanning line that is not selected among the lines, a discharging operation for discharging the charge from the scanning line selection unit to the second power supply line is performed, 8. The display according to claim 7, wherein the scanning signal is output only to a scanning line selected from the plurality of scanning lines. Rei.   The plurality of second switching elements further include a signal output switching element connected to one of the plurality of scanning lines, and the scanning line selection unit includes the precharge switching element and the signal output switching element. The display according to claim 7, further comprising a capacitor for accumulating charges on a wiring connecting the two. The display includes control means for controlling the plurality of second switching elements,
The control means turns off discharge switching elements and signal output switching elements of all the scanning line selection units included in the decoder circuit, and precharges all the scanning line selection units included in the decoder circuit. By turning on the switching element, a precharge operation for accumulating charges from the first power supply line to all the scanning line selection units and the capacitors is performed, and then the precharge switching of all the scanning line selection units is performed. By turning off the element and turning on the discharge switching element of the scanning line selection unit connected to the scanning line that is not selected among the plurality of scanning lines, the capacitance of the scanning line selection unit and the scanning line selection unit is A discharge operation for discharging the charge to the second power supply line is performed, and the signal output switches of all the scanning line selection units are operated. The display of claim 9 which turns on the quenching device, and outputs the scanning signal only to the scanning line selected among the plurality of scan lines.   The display according to any one of claims 1 to 10, wherein the decoder circuit is a NOR type.   12. The display according to claim 1, wherein each of the first plurality of switching elements and the plurality of second switching elements is a transistor having an inverted staggered structure.   12. The display according to claim 1, wherein each of the first plurality of switching elements and the plurality of second switching elements is a transistor having a coplanar structure.

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